diff --git a/libpresifuzz_feedbacks/spike.log b/libpresifuzz_feedbacks/spike.log new file mode 100644 index 0000000..982b10c --- /dev/null +++ b/libpresifuzz_feedbacks/spike.log @@ -0,0 +1,83655 @@ +core 0: 0x00001000 (0x00000297) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t0, 0x0 +core 0: 3 0x00001000 (0x00000297) x5 0x00001000 +core 0: 0x00001004 (0x02028593) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a1, t0, 32 +core 0: 3 0x00001004 (0x02028593) x11 0x00001020 +core 0: 0x00001008 (0xf1402573) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] csrr a0, mhartid +core 0: 3 0x00001008 (0xf1402573) x10 0x00000000 +core 0: 0x0000100c (0x0182a283) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] lw t0, 24(t0) +core 0: 3 0x0000100c (0x0182a283) x5 0x80000000 mem 0x00001018 +core 0: 0x00001010 (0x00028067) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] jr t0 +core 0: 3 0x00001010 (0x00028067) +core 0: 0x80000000 (0x00000297) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t0, 0x0 +core 0: 3 0x80000000 (0x00000297) x5 0x80000000 +core 0: 0x80000004 (0x11428293) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t0, t0, 276 +core 0: 3 0x80000004 (0x11428293) x5 0x80000114 +core 0: 0x80000008 (0x30529073) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] csrw mtvec, t0 +core 0: 3 0x80000008 (0x30529073) c773_mtvec 0x80000114 +core 0: 0x8000000c (0x00001e97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x8000000c (0x00001e97) x29 0x8000100c +core 0: 0x80000010 (0xff4e8e93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t4, t4, -12 +core 0: 3 0x80000010 (0xff4e8e93) x29 0x80001000 +core 0: 0x80000014 (0x000ea023) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] sw zero, 0(t4) +core 0: 3 0x80000014 (0x000ea023) mem 0x80001000 0x00000000 +core 0: 0x80000018 (0x00001097) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc ra, 0x1 +core 0: 3 0x80000018 (0x00001097) x1 0x80001018 +core 0: 0x8000001c (0xfe808093) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi ra, ra, -24 +core 0: 3 0x8000001c (0xfe808093) x1 0x80001000 +core 0: 0x80000020 (0x00001117) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc sp, 0x1 +core 0: 3 0x80000020 (0x00001117) x2 0x80001020 +core 0: 0x80000024 (0xfe010113) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi sp, sp, -32 +core 0: 3 0x80000024 (0xfe010113) x2 0x80001000 +core 0: 0x80000028 (0x00001197) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc gp, 0x1 +core 0: 3 0x80000028 (0x00001197) x3 0x80001028 +core 0: 0x8000002c (0xfd818193) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi gp, gp, -40 +core 0: 3 0x8000002c (0xfd818193) x3 0x80001000 +core 0: 0x80000030 (0x00001217) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc tp, 0x1 +core 0: 3 0x80000030 (0x00001217) x4 0x80001030 +core 0: 0x80000034 (0xfd020213) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi tp, tp, -48 +core 0: 3 0x80000034 (0xfd020213) x4 0x80001000 +core 0: 0x80000038 (0x00001297) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t0, 0x1 +core 0: 3 0x80000038 (0x00001297) x5 0x80001038 +core 0: 0x8000003c (0xfc828293) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t0, t0, -56 +core 0: 3 0x8000003c (0xfc828293) x5 0x80001000 +core 0: 0x80000040 (0x00001317) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t1, 0x1 +core 0: 3 0x80000040 (0x00001317) x6 0x80001040 +core 0: 0x80000044 (0xfc030313) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t1, t1, -64 +core 0: 3 0x80000044 (0xfc030313) x6 0x80001000 +core 0: 0x80000048 (0x00001397) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t2, 0x1 +core 0: 3 0x80000048 (0x00001397) x7 0x80001048 +core 0: 0x8000004c (0xfb838393) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t2, t2, -72 +core 0: 3 0x8000004c (0xfb838393) x7 0x80001000 +core 0: 0x80000050 (0x00001417) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s0, 0x1 +core 0: 3 0x80000050 (0x00001417) x8 0x80001050 +core 0: 0x80000054 (0xfb040413) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s0, s0, -80 +core 0: 3 0x80000054 (0xfb040413) x8 0x80001000 +core 0: 0x80000058 (0x00001497) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s1, 0x1 +core 0: 3 0x80000058 (0x00001497) x9 0x80001058 +core 0: 0x8000005c (0xfa848493) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s1, s1, -88 +core 0: 3 0x8000005c (0xfa848493) x9 0x80001000 +core 0: 0x80000060 (0x00001517) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a0, 0x1 +core 0: 3 0x80000060 (0x00001517) x10 0x80001060 +core 0: 0x80000064 (0xfa050513) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a0, a0, -96 +core 0: 3 0x80000064 (0xfa050513) x10 0x80001000 +core 0: 0x80000068 (0x00001597) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a1, 0x1 +core 0: 3 0x80000068 (0x00001597) x11 0x80001068 +core 0: 0x8000006c (0xf9858593) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a1, a1, -104 +core 0: 3 0x8000006c (0xf9858593) x11 0x80001000 +core 0: 0x80000070 (0x00001617) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a2, 0x1 +core 0: 3 0x80000070 (0x00001617) x12 0x80001070 +core 0: 0x80000074 (0xf9060613) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a2, a2, -112 +core 0: 3 0x80000074 (0xf9060613) x12 0x80001000 +core 0: 0x80000078 (0x00001697) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a3, 0x1 +core 0: 3 0x80000078 (0x00001697) x13 0x80001078 +core 0: 0x8000007c (0xf8868693) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a3, a3, -120 +core 0: 3 0x8000007c (0xf8868693) x13 0x80001000 +core 0: 0x80000080 (0x00001717) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a4, 0x1 +core 0: 3 0x80000080 (0x00001717) x14 0x80001080 +core 0: 0x80000084 (0xf8070713) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a4, a4, -128 +core 0: 3 0x80000084 (0xf8070713) x14 0x80001000 +core 0: 0x80000088 (0x00001797) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a5, 0x1 +core 0: 3 0x80000088 (0x00001797) x15 0x80001088 +core 0: 0x8000008c (0xf7878793) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a5, a5, -136 +core 0: 3 0x8000008c (0xf7878793) x15 0x80001000 +core 0: 0x80000090 (0x00001817) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a6, 0x1 +core 0: 3 0x80000090 (0x00001817) x16 0x80001090 +core 0: 0x80000094 (0xf7080813) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a6, a6, -144 +core 0: 3 0x80000094 (0xf7080813) x16 0x80001000 +core 0: 0x80000098 (0x00001897) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc a7, 0x1 +core 0: 3 0x80000098 (0x00001897) x17 0x80001098 +core 0: 0x8000009c (0xf6888893) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi a7, a7, -152 +core 0: 3 0x8000009c (0xf6888893) x17 0x80001000 +core 0: 0x800000a0 (0x00001917) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s2, 0x1 +core 0: 3 0x800000a0 (0x00001917) x18 0x800010a0 +core 0: 0x800000a4 (0xf6090913) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s2, s2, -160 +core 0: 3 0x800000a4 (0xf6090913) x18 0x80001000 +core 0: 0x800000a8 (0x00001997) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s3, 0x1 +core 0: 3 0x800000a8 (0x00001997) x19 0x800010a8 +core 0: 0x800000ac (0xf5898993) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s3, s3, -168 +core 0: 3 0x800000ac (0xf5898993) x19 0x80001000 +core 0: 0x800000b0 (0x00001a17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s4, 0x1 +core 0: 3 0x800000b0 (0x00001a17) x20 0x800010b0 +core 0: 0x800000b4 (0xf50a0a13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s4, s4, -176 +core 0: 3 0x800000b4 (0xf50a0a13) x20 0x80001000 +core 0: 0x800000b8 (0x00001a97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s5, 0x1 +core 0: 3 0x800000b8 (0x00001a97) x21 0x800010b8 +core 0: 0x800000bc (0xf48a8a93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s5, s5, -184 +core 0: 3 0x800000bc (0xf48a8a93) x21 0x80001000 +core 0: 0x800000c0 (0x00001b17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s6, 0x1 +core 0: 3 0x800000c0 (0x00001b17) x22 0x800010c0 +core 0: 0x800000c4 (0xf40b0b13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s6, s6, -192 +core 0: 3 0x800000c4 (0xf40b0b13) x22 0x80001000 +core 0: 0x800000c8 (0x00001b97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s7, 0x1 +core 0: 3 0x800000c8 (0x00001b97) x23 0x800010c8 +core 0: 0x800000cc (0xf38b8b93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s7, s7, -200 +core 0: 3 0x800000cc (0xf38b8b93) x23 0x80001000 +core 0: 0x800000d0 (0x00001c17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s8, 0x1 +core 0: 3 0x800000d0 (0x00001c17) x24 0x800010d0 +core 0: 0x800000d4 (0xf30c0c13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s8, s8, -208 +core 0: 3 0x800000d4 (0xf30c0c13) x24 0x80001000 +core 0: 0x800000d8 (0x00001c97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s9, 0x1 +core 0: 3 0x800000d8 (0x00001c97) x25 0x800010d8 +core 0: 0x800000dc (0xf28c8c93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s9, s9, -216 +core 0: 3 0x800000dc (0xf28c8c93) x25 0x80001000 +core 0: 0x800000e0 (0x00001d17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s10, 0x1 +core 0: 3 0x800000e0 (0x00001d17) x26 0x800010e0 +core 0: 0x800000e4 (0xf20d0d13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s10, s10, -224 +core 0: 3 0x800000e4 (0xf20d0d13) x26 0x80001000 +core 0: 0x800000e8 (0x00001d97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc s11, 0x1 +core 0: 3 0x800000e8 (0x00001d97) x27 0x800010e8 +core 0: 0x800000ec (0xf18d8d93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi s11, s11, -232 +core 0: 3 0x800000ec (0xf18d8d93) x27 0x80001000 +core 0: 0x800000f0 (0x00001e17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t3, 0x1 +core 0: 3 0x800000f0 (0x00001e17) x28 0x800010f0 +core 0: 0x800000f4 (0xf10e0e13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t3, t3, -240 +core 0: 3 0x800000f4 (0xf10e0e13) x28 0x80001000 +core 0: 0x800000f8 (0x00001e97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x800000f8 (0x00001e97) x29 0x800010f8 +core 0: 0x800000fc (0xf08e8e93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t4, t4, -248 +core 0: 3 0x800000fc (0xf08e8e93) x29 0x80001000 +core 0: 0x80000100 (0x00001f17) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t5, 0x1 +core 0: 3 0x80000100 (0x00001f17) x30 0x80001100 +core 0: 0x80000104 (0xf00f0f13) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t5, t5, -256 +core 0: 3 0x80000104 (0xf00f0f13) x30 0x80001000 +core 0: 0x80000108 (0x00001f97) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] auipc t6, 0x1 +core 0: 3 0x80000108 (0x00001f97) x31 0x80001108 +core 0: 0x8000010c (0xef8f8f93) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] addi t6, t6, -264 +core 0: 3 0x8000010c (0xef8f8f93) x31 0x80001000 +core 0: 0x80000110 (0x6f50006f) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] j pc + 0xef4 +core 0: 3 0x80000110 (0x6f50006f) +core 0: 0x80001004 (0xdeadbeef) [0x0,0,00,00,00,00000000,00000000,00000000,40000000] jal t4, pc - 0x24a16 +core 0: 3 0x80001004 (0xdeadbeef) x29 0x80001008 +core 0: exception trap_instruction_access_fault, epc 0x7ffdc5ee +core 0: tval 0x7ffdc5ee +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x1800,0,00,01,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x7ffdc5ee +core 0: 0x80000118 (0x00028303) [0x1800,0,00,01,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: exception trap_load_access_fault, epc 0x80000118 +core 0: tval 0x7ffdc5ee +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000118 +core 0: 0x80000118 (0x00028303) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000003 mem 0x80000118 +core 0: 0x8000011c (0x0000450d) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000000 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000001 +core 0: 0x80000130 (0x00004fa9) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000001 +core 0: 0x8000013a (0x00a31363) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x8000011a +core 0: 0x80000140 (0x00000289) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x8000011c +core 0: 0x80000142 (0x34129073) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x8000011c +core 0: 0x80000146 (0x30200073) [0x1800,0,00,05,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000080 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000001 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000002 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000002 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x8000011e +core 0: 0x80000140 (0x00000289) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x80000120 +core 0: 0x80000142 (0x34129073) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x80000120 +core 0: 0x80000146 (0x30200073) [0x80,0,00,05,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: 0x80000120 (0x1e9700a3) [0x88,0,00,05,00,00000000,00000000,00000000,40000000] sb s1, 481(a4) +core 0: 0 0x80000120 (0x1e9700a3) mem 0x800011e1 0x00 +core 0: 0x80000124 (0x00000000) [0x88,0,00,05,00,00000000,00000000,00000000,40000000] c.unimp +core 0: exception trap_illegal_instruction, epc 0x80000124 +core 0: tval 0x00000000 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000124 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000000 mem 0x80000124 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000000 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000002 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000003 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000003 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x80000140 (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x80000126 +core 0: 0x80000142 (0x34129073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x80000126 +core 0: 0x80000146 (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: 0x80000126 (0xedee8e93) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 0 0x80000126 (0xedee8e93) x29 0x80000ede +core 0: 0x8000012a (0x000eaf03) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: exception trap_load_address_misaligned, epc 0x8000012a +core 0: tval 0x80000ede +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x8000012a +core 0: 0x80000118 (0x00028303) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000003 mem 0x8000012a +core 0: 0x8000011c (0x0000450d) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000003 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000004 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000004 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x8000012c +core 0: 0x80000140 (0x00000289) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x8000012e +core 0: 0x80000142 (0x34129073) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x8000012e +core 0: 0x80000146 (0x30200073) [0x80,0,00,04,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: 0x8000012e (0x00000f05) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 0 0x8000012e (0x0f05) x30 0x00000005 +core 0: 0x80000130 (0x00004fa9) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 0 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 0 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 0 0x80000136 (0x01eea023) mem 0x80001000 0x00000005 +core 0: 0x8000013a (0x00a31363) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 0 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 0 0x8000013e (0x0289) x5 0x80000130 +core 0: 0x80000140 (0x00000289) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 0 0x80000140 (0x0289) x5 0x80000132 +core 0: 0x80000142 (0x34129073) [0x88,0,00,04,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: exception trap_illegal_instruction, epc 0x80000142 +core 0: tval 0x34129073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000142 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000142 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000005 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000006 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000006 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x80000144 +core 0: 0x80000140 (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x80000146 +core 0: 0x80000142 (0x34129073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x80000146 +core 0: 0x80000146 (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end_handler_ret +core 0: 0x80000146 (0x30200073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: exception trap_illegal_instruction, epc 0x80000146 +core 0: tval 0x30200073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000146 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000146 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000006 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000007 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000007 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x80000148 +core 0: 0x80000140 (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x8000014a +core 0: 0x80000142 (0x34129073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x8000014a +core 0: 0x80000146 (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: 0x8000014a (0x00000013) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] nop +core 0: 0 0x8000014a (0x00000013) +core 0: 0x8000014e (0x00000001) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] c.nop +core 0: 0 0x8000014e (0x0001) +core 0: 0x80000150 (0x00000e17) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 0 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 0 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: exception trap_illegal_instruction, epc 0x80000158 +core 0: tval 0x141e1073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000158 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000158 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000007 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000008 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000008 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x8000015a +core 0: 0x80000140 (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x8000015c +core 0: 0x80000142 (0x34129073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x8000015c +core 0: 0x80000146 (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: 0x8000015c (0x30200073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: exception trap_illegal_instruction, epc 0x8000015c +core 0: tval 0x30200073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x8000015c +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x8000015c +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000008 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x00000009 +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000136 (0x01eea023) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] sw t5, 0(t4) +core 0: 3 0x80000136 (0x01eea023) mem 0x80001000 0x00000009 +core 0: 0x8000013a (0x00a31363) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] bne t1, a0, pc + 6 +core 0: 3 0x8000013a (0x00a31363) +core 0: 0x8000013e (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x8000013e (0x0289) x5 0x8000015e +core 0: 0x80000140 (0x00000289) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t0, 2 +core 0: 3 0x80000140 (0x0289) x5 0x80000160 +core 0: 0x80000142 (0x34129073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw mepc, t0 +core 0: 3 0x80000142 (0x34129073) c833_mepc 0x80000160 +core 0: 0x80000146 (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x80000146 (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi +core 0: exception trap_illegal_instruction, epc 0x80000160 +core 0: tval 0x10500073 +core 0: >>>> exception_entry +core 0: 0x80000114 (0x341022f3) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrr t0, mepc +core 0: 3 0x80000114 (0x341022f3) x5 0x80000160 +core 0: 0x80000118 (0x00028303) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lb t1, 0(t0) +core 0: 3 0x80000118 (0x00028303) x6 0x00000073 mem 0x80000160 +core 0: 0x8000011c (0x0000450d) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li a0, 3 +core 0: 3 0x8000011c (0x450d) x10 0x00000003 +core 0: 0x8000011e (0x00a37333) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] and t1, t1, a0 +core 0: 3 0x8000011e (0x00a37333) x6 0x00000003 +core 0: 0x80000122 (0x00001e97) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t4, 0x1 +core 0: 3 0x80000122 (0x00001e97) x29 0x80001122 +core 0: 0x80000126 (0xedee8e93) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t4, t4, -290 +core 0: 3 0x80000126 (0xedee8e93) x29 0x80001000 +core 0: 0x8000012a (0x000eaf03) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] lw t5, 0(t4) +core 0: 3 0x8000012a (0x000eaf03) x30 0x00000009 mem 0x80001000 +core 0: 0x8000012e (0x00000f05) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.addi t5, 1 +core 0: 3 0x8000012e (0x0f05) x30 0x0000000a +core 0: 0x80000130 (0x00004fa9) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] c.li t6, 10 +core 0: 3 0x80000130 (0x4fa9) x31 0x0000000a +core 0: 0x80000132 (0x01ff0f63) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] beq t5, t6, pc + 30 +core 0: 3 0x80000132 (0x01ff0f63) +core 0: 0x80000150 (0x00000e17) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] auipc t3, 0x0 +core 0: 3 0x80000150 (0x00000e17) x28 0x80000150 +core 0: 0x80000154 (0x010e0e13) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] addi t3, t3, 16 +core 0: 3 0x80000154 (0x010e0e13) x28 0x80000160 +core 0: 0x80000158 (0x141e1073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] csrw sepc, t3 +core 0: 3 0x80000158 (0x141e1073) c321_sepc 0x80000160 +core 0: 0x8000015c (0x30200073) [0x80,0,00,02,00,00000000,00000000,00000000,40000000] mret +core 0: 3 0x8000015c (0x30200073) c1957_tcontrol 0x00000000 c784_mstatush 0x00000000 c768_mstatus 0x00000088 +core 0: >>>> end +core 0: 0x80000160 (0x10500073) [0x88,0,00,02,00,00000000,00000000,00000000,40000000] wfi diff --git a/libpresifuzz_feedbacks/src/csr_feedback.rs b/libpresifuzz_feedbacks/src/csr_feedback.rs index 9311971..d6faaf4 100644 --- a/libpresifuzz_feedbacks/src/csr_feedback.rs +++ b/libpresifuzz_feedbacks/src/csr_feedback.rs @@ -365,7 +365,7 @@ mod tests { let mut mgr = NopEventManager::new(); let _ = spike_trace_observer.post_exec(&mut state, &input, &ExitKind::Ok); - // println!("{:?}", spike_trace_observer.trace.len()) + println!("{:?}", spike_trace_observer.trace()); let observers = tuple_list!(spike_trace_observer); feedback.is_interesting(&mut state, &mut mgr, &input, &observers, &ExitKind::Ok); diff --git a/libpresifuzz_observers/src/trace_observer.rs b/libpresifuzz_observers/src/trace_observer.rs index 772fcc3..56b0bc7 100644 --- a/libpresifuzz_observers/src/trace_observer.rs +++ b/libpresifuzz_observers/src/trace_observer.rs @@ -12,6 +12,7 @@ use libafl::{ use core::{fmt::Debug}; use serde::{Deserialize, Serialize}; use libafl_bolts::{HasLen, Named}; +use std::fmt::{self, Display, Formatter}; use std::fs::File; @@ -100,6 +101,16 @@ impl CSRLog { } } +impl Display for CSRLog { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + write!( + f, + "CSRLog {{ mstatus: {}, frm: {}, fflags: {}, mcause: {}, scause: {}, medeleg: {}, mcounteren: {}, scounteren: {} }}", + self.mstatus, self.frm, self.fflags, self.mcause, self.scause, self.medeleg, self.mcounteren, self.scounteren + ) + } +} + #[derive(Copy, Clone, Serialize, Deserialize, Debug)] pub enum OpType { Read, @@ -113,6 +124,15 @@ impl PartialEq for OpType { } } +impl Display for OpType { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + match self { + OpType::Read => write!(f, "Read"), + OpType::Write => write!(f, "Write"), + } + } +} + #[derive(Copy, Clone, Serialize, Deserialize, Debug)] pub struct MemOp { pub op_type: OpType, @@ -130,6 +150,16 @@ impl PartialEq for MemOp { } } +impl Display for MemOp { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + write!( + f, + "MemOp {{ op_type: {}, address: {}, value: {} }}", + self.op_type, self.address, self.value + ) + } +} + #[derive(Clone, Serialize, Deserialize, Debug)] pub struct RegOp { pub op_type: OpType, @@ -146,6 +176,16 @@ impl PartialEq for RegOp { } } +impl Display for RegOp { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + write!( + f, + "RegOp {{ op_type: {}, name: {}, value: {} }}", + self.op_type, self.name, self.value + ) + } +} + #[derive(Clone, Serialize, Deserialize, Debug)] pub enum OpLog { RegOp(RegOp), @@ -162,6 +202,15 @@ impl PartialEq for OpLog { } } +impl Display for OpLog { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + match self { + OpLog::RegOp(reg_op) => write!(f, "RegOp({})", reg_op), + OpLog::MemOp(mem_op) => write!(f, "MemOp({})", mem_op), + } + } +} + #[derive(Clone, Serialize, Deserialize, Debug)] pub struct TraceLog { pub pc: u64, @@ -170,6 +219,22 @@ pub struct TraceLog { pub csr: Option, } +impl Display for TraceLog { + fn fmt(&self, f: &mut Formatter<'_>) -> fmt::Result { + write!( + f, + "TraceLog {{ pc: {}, inst: {}, ops: {:?}, csr: {} }}", + self.pc, + self.inst, + self.ops.iter().map(|op| format!("{}", op)).collect::>().join(", "), + match &self.csr { + Some(csr_log) => format!("{}", csr_log), + None => "None".to_string(), + } + ) + } +} + pub trait ExecTraceParser { fn new() -> Self; fn parse(&self, trace_filename: &str) -> Result, Error> ; @@ -328,6 +393,8 @@ impl ExecTraceParser for ProcessorFuzzExecTraceObserver if let Ok(log_line) = &line { + println!("{}",log_line); + if let Some(caps) = spike_store_commit_re.captures(log_line) { for (i, cap) in caps.iter().skip(3).enumerate() {