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Use a per-task stack canary for stack protector #29
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arm64 background: arm64 compiler changes: arm64 kernel implementation: |
Clang support needed: |
GCC support for RISCV proposed: |
(I'm removing the "fixed" labels for arm32 and arm64 since there isn't Clang support yet...) |
PowerPC isn't supported either in Clang, is it? By the way, RISC-V support for |
Hm, I may need to split up the per-arch issues and per-compiler issues into separate bugs. Or a task list, perhaps. |
Okay, I've tried to collect the matrix in the bug description. |
https://git.kernel.org/linus/fea2fed201ee5647699018a56fbb6a5e8cc053a5 in v5.12 (riscv per-task canary support for gcc) |
Also tracked at ClangBuiltLinux#289 |
Implemented in Clang for arm64 now: llvm/llvm-project@0f41778 |
I think there's a leak of the canary though: llvm/llvm-project#46338 (originally https://bugs.llvm.org/show_bug.cgi?id=50467) |
Thanks for the heads-up! |
I just accepted https://reviews.llvm.org/D129346 which should close out llvm/llvm-project#48553. Therefor, I have marked x86_32: -mstack-protector-guard-reg=fs -mstack-protector-guard-symbol=__stack_chk_guard, or old %gs offset before v5.13 |
llvm/llvm-project#46685 has been closed |
clang support for PowerPC was merged in llvm/llvm-project@44b020a (20.0.0) and the kernel was updated to support clang’s implementation with my changes in the 6.13 pull request. |
Some architectures don't have compiler support for a per-task stack canary, so the canary value is the same across all kernel threads. This means a stack memory exposure of the canary value from one task can be used for attacks against all other kernel tasks, making such exposures much more severe. To avoid this, the stack canary must be different for each kernel thread, which requires compiler support as well as kernel support.
Recent implementations use the compiler arguments similar to the form
-mstack-protector-guard=sysreg -mstack-protector-guard-reg=$REGISTER -mstack-protector-guard-offset=$OFFSET
(see implementations below).Linux/compiler/architecture support matrix
Implementation weaknesses
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