From c5b008965ea335b80e567074eced04745b5ca295 Mon Sep 17 00:00:00 2001
From: Vincenzo Maisto <maisto_v@libero.it>
Date: Sat, 2 Dec 2023 15:00:35 +0100
Subject: [PATCH] tmp commit

---
 Bender.lock                                   |   6 +-
 Bender.yml                                    |  11 +-
 RVV_TEST.md                                   |  19 +-
 hw/cheshire_soc.sv                            |  11 +-
 hw/mmu_stub.sv                                |  20 +-
 sw/sw.mk                                      |   4 +-
 sw/tests/mock_rvv_test_vstart_indexed         | Bin 0 -> 22320 bytes
 sw/tests/mock_rvv_test_vstart_indexed.cc      | 239 ++++++++++++++++++
 sw/tests/rvv_test.h                           |  18 +-
 ... => rvv_test_vstart_mmu_stub_page_fault.c} |  81 +++---
 sw/tests/rvv_test_vstart_strided_mmu_stub.c   |   9 +
 ..._test_vstart_strided_mmu_stub_page_fault.c |   9 +
 .../rvv_test_vstart_unit_stride_mmu_stub.c    |   9 +
 ...t_vstart_unit_stride_mmu_stub_page_fault.c |   9 +
 sw/tests/rvv_test_vstart_vadd_mmu_stub.c      |   9 +
 target/common/ara.mk                          |   4 +-
 target/sim/src/fixture_cheshire_soc.sv        |   8 +
 target/sim/vsim/mmu_stub_run.tcl              |  13 +-
 target/sim/vsim/start.cheshire_soc.tcl        |   4 +-
 target/sim/vsim/vsim.mk                       |   3 +-
 target/xilinx/scripts/tcl/debug_gui.tcl       |   5 +
 target/xilinx/src/cheshire_top_xilinx.sv      |  12 +-
 target/xilinx/xilinx/xlnx_vio/tcl/run.tcl     |   4 +-
 util.mk                                       |  29 ++-
 24 files changed, 454 insertions(+), 82 deletions(-)
 create mode 100755 sw/tests/mock_rvv_test_vstart_indexed
 create mode 100644 sw/tests/mock_rvv_test_vstart_indexed.cc
 rename sw/tests/{rvv_test_mmu_stub.c => rvv_test_vstart_mmu_stub_page_fault.c} (57%)
 create mode 100644 sw/tests/rvv_test_vstart_strided_mmu_stub.c
 create mode 100644 sw/tests/rvv_test_vstart_strided_mmu_stub_page_fault.c
 create mode 100644 sw/tests/rvv_test_vstart_unit_stride_mmu_stub.c
 create mode 100644 sw/tests/rvv_test_vstart_unit_stride_mmu_stub_page_fault.c
 create mode 100644 sw/tests/rvv_test_vstart_vadd_mmu_stub.c

diff --git a/Bender.lock b/Bender.lock
index 5f353f9e..a123e791 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -46,8 +46,8 @@ packages:
     - register_interface
     - tech_cells_generic
   axi_riscv_atomics:
-    revision: c3c3f2b65071841035c4e081c61c9b7be801d749
-    version: 0.8.1
+    revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e
+    version: 0.8.2
     source:
       Git: https://github.com/pulp-platform/axi_riscv_atomics.git
     dependencies:
@@ -130,7 +130,7 @@ packages:
     - register_interface
   irq_router:
     revision: d1d31350b24f3965b3a51e1bc96c71eb34e94db3
-    version: null
+    version: 0.0.1-beta.1
     source:
       Git: https://github.com/pulp-platform/irq_router.git
     dependencies:
diff --git a/Bender.yml b/Bender.yml
index ad81d53a..626325e2 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -13,22 +13,22 @@ package:
 
 dependencies:
   apb_uart:                 { git: "https://github.com/pulp-platform/apb_uart.git",               version: 0.2.1  }
-  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: 0.39.0 }
+  axi:                      { git: "https://github.com/pulp-platform/axi.git",                    version: =0.39.0 }
   axi_llc:                  { git: "https://github.com/pulp-platform/axi_llc.git",                version: 0.2.1  }
-  axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: 0.8.1  }
+  axi_riscv_atomics:        { git: "https://github.com/pulp-platform/axi_riscv_atomics.git",      version: =0.8.1  }
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.1  }
-  clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: ^0.2.0 }
+  clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0 }
   common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.29.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
   cva6:                     { git: "https://github.com/MaistoV/cva6_fork.git",                rev: "ara_cheshire" } 
   ara:                      { git: "https://github.com/MaistoV/ara_fork.git",                 rev: "ara_cheshire" }
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   rev: 437ffa9    }  # TODO: master commit; use next release once out
   opentitan_peripherals:    { git: "https://github.com/pulp-platform/opentitan_peripherals.git",  version: 0.4.0  }
-  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: ^0.4.1 }
+  register_interface:       { git: "https://github.com/pulp-platform/register_interface.git",     version: =0.4.1 }
   riscv-dbg:                { git: "https://github.com/pulp-platform/riscv-dbg.git",              version: 0.8.0  }
   serial_link:              { git: "https://github.com/pulp-platform/serial_link.git",            version: 1.1.0  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
-  irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: d1d3135    }  # TODO: master commit; use next release once out
+  irq_router:               { git: "https://github.com/pulp-platform/irq_router.git",             rev: =0.0.1-beta.1    }  # TODO: master commit; use next release once out
 
 export_include_dirs:
   - hw/include
@@ -42,6 +42,7 @@ sources:
   - hw/regs/axi_rt_reg_top.sv
   - hw/cheshire_pkg.sv
   - hw/cheshire_soc.sv
+  - hw/mmu_stub.sv
 
   - target: any(simulation, test)
     files:
diff --git a/RVV_TEST.md b/RVV_TEST.md
index 94e9af35..c207a6ed 100644
--- a/RVV_TEST.md
+++ b/RVV_TEST.md
@@ -1,5 +1,5 @@
 # RVV_TEST light-weight framework
-> **_NOTE:_** This is not close to what a structured verification pipeline should look like, but it is an acceptable solution for the short time frames we have.
+> **NOTE:** This is not close to what a structured verification pipeline should look like, but it is an acceptable solution for the short time frames we have.
 
 A set of utility make targets are defined to build and automate the tests for the extensions performed on Ara integrated in Cheshire and perform regression.
 
@@ -55,4 +55,19 @@ Unset these variables for subsequent runs:
 ````console
 $ unset RVV_TEST RVV_TEST_ELF VSIM_ARGS ARA_NR_LANES TEST_COMMENT
 ````
- 
\ No newline at end of file
+
+# MMU Stub
+The design features a stub MMU in `cheshire_soc`, attached to Ara MMU port, which emulates address translation and exception page fault generation.
+
+- This module is instatiated only if the variable `MMU_STUB` is defined and equals `1`. If not so, instructions in the next bullets will cause the simulation build to fail. Otherwise its outputs are tied to zero. 
+
+> TODO: route its I/O to CVA6
+
+- Emulated translation is enabled only if the test name, i.e., the .c source, contains the string `mmu_stub`. E.g., `rvv_test_mmu_stub.c`.
+
+- Page faults are unconditionally generated if the test name **also** contains the string `page_fault`. E.g., `rvv_test_mmu_stub_page_fault.c`.
+
+Rebember to unset the `MMU_STUB` variable if necessary.
+````console
+$ unset MMU_STUB
+````
\ No newline at end of file
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index 5553abd2..8a496005 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -729,8 +729,9 @@ module cheshire_soc import cheshire_pkg::*; #(
       .axi_resp_i      ( axi_ara_wide_resp )
     );
 
+
     // DEBUG: MMU stub
-    // TODO: instantiate conditionally
+`ifdef MMU_STUB
     mmu_stub i_mmu_stub (
       .clk_i                  ( clk_i                       ),
       .rst_ni                 ( rst_ni                      ),
@@ -746,6 +747,14 @@ module cheshire_soc import cheshire_pkg::*; #(
       .paddr_o                ( mmu_paddr_cva6_acc          ),                 
       .exception_o            ( mmu_exception_cva6_acc      ) 
     );
+`else // !MMU_STUB     
+    // TODO: route these to CVA6
+    assign mmu_dtlb_hit_cva6_acc  = '0;
+    assign mmu_dtlb_ppn_cva6_acc  = '0;
+    assign mmu_valid_cva6_acc     = '0;
+    assign mmu_paddr_cva6_acc     = '0;
+    assign mmu_exception_cva6_acc = '0;
+`endif // MMU_STUB
 
     // Issue invalidations to CVA6 L1D$
     axi_inval_filter #(
diff --git a/hw/mmu_stub.sv b/hw/mmu_stub.sv
index ae251d67..3e354b31 100644
--- a/hw/mmu_stub.sv
+++ b/hw/mmu_stub.sv
@@ -9,8 +9,8 @@
 module mmu_stub (
     input  logic                          clk_i,
     input  logic                          rst_ni,
-    input  logic                          en_ld_st_translation_i,  // Enable bahaviour
-    input  logic                          trigger_exception_i,     // Emulate exception generation on requests
+    input  logic                          en_ld_st_translation_i,  // Enable behaviour
+    input  logic                          trigger_exception_i,     // Emulate exception generation on requests (load/store page faults)
     input  ariane_pkg::exception_t        misaligned_ex_i,         // Ignored
     input  logic                          req_i,
     input  logic [riscv::VLEN-1:0]        vaddr_i,
@@ -29,9 +29,11 @@ module mmu_stub (
   logic [riscv::PLEN-1:0] mock_paddr_d, mock_paddr_q;
   logic [riscv::VLEN-1:0] vaddr_d, vaddr_q;
   logic                   valid_d, valid_q;
+  logic                   is_store_q, is_store_d;
   `FF(mock_paddr_q, mock_paddr_d, '0, clk_i, rst_ni)
   `FF(vaddr_q     , vaddr_d     , '0, clk_i, rst_ni)
   `FF(valid_q     , valid_d     , '0, clk_i, rst_ni)
+  `FF(is_store_q  , is_store_d  , '0, clk_i, rst_ni)
 
   // Combinatorial logic
   always_comb begin : mmu_stub
@@ -46,19 +48,19 @@ module mmu_stub (
     mock_paddr_d = mock_paddr_q;
     valid_d      = valid_q;
     vaddr_d      = vaddr_q;
+    is_store_d   = is_store_q;
 
     // If trasnlation is enabled
     if ( en_ld_st_translation_i ) begin : enable_translation
       // Cycle 0
       if ( req_i ) begin : req_valid
-          // For next cycle
+          // Sample inputs, for next cycle
+          mock_paddr_d = vaddr_i; // Mock, just pass back the same vaddr
+          vaddr_d      = vaddr_i;
+          is_store_d   = is_store_i;
+
           // Pull up valid
           valid_d = 1'b1;
-          // Mock, just pass back the same vaddr
-          mock_paddr_d = vaddr_i;
-
-          // Sample vaddr_i in case of exception
-          vaddr_d = vaddr_i;
 
           // DTBL hit, assume 100%
           // NOTE: Ara does not use these
@@ -79,7 +81,7 @@ module mmu_stub (
       // Mock exception logic
       if ( trigger_exception_i & valid_q ) begin : exception
         exception_o.valid = 1'b1;
-        exception_o.cause = ( is_store_i ) ? riscv::STORE_PAGE_FAULT : riscv::LOAD_PAGE_FAULT;
+        exception_o.cause = ( is_store_q ) ? riscv::STORE_PAGE_FAULT : riscv::LOAD_PAGE_FAULT;
         exception_o.tval  = {'0, vaddr_q};
       end : exception
     end : enable_translation
diff --git a/sw/sw.mk b/sw/sw.mk
index aa2d5703..5fac090c 100644
--- a/sw/sw.mk
+++ b/sw/sw.mk
@@ -93,10 +93,10 @@ CHS_SW_GEN_HDRS += $(OTPROOT)/.generated
 # TODO: track headers with gcc -MM!
 
 # All objects require up-to-date patches and headers
-%.o: %.c $(CHS_SW_GEN_HDRS)
+%.o: %.c $(CHS_SW_GEN_HDRS) $(CHS_SW_RVV_TEST_HDRS)
 	$(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@ 
 
-%.o: %.S $(CHS_SW_GEN_HDRS)
+%.o: %.S $(CHS_SW_GEN_HDRS) $(CHS_SW_RVV_TEST_HDRS)
 	$(CHS_SW_CC) $(CHS_SW_INCLUDES) $(CHS_SW_CCFLAGS) -c $< -o $@
 
 define chs_ld_elf_rule
diff --git a/sw/tests/mock_rvv_test_vstart_indexed b/sw/tests/mock_rvv_test_vstart_indexed
new file mode 100755
index 0000000000000000000000000000000000000000..a8b3f154dcef76c55047875a0966d461243839fb
GIT binary patch
literal 22320
zcmeHPeQX@Zb)UTxCEAvbCtI!=*|FBP2vf3oBqdX!WGTL*c+}FMJ|a<x+*IB>-W|z<
zk9X|do<g}OOqY_N3&Vs!<CF-{mVY%$925fD7^;BEloU&{Tc9+MI)a@hbQ%X#=^{)M
zJBnS4eQ##o-tOM6q6X-PksImwW`6VDn>TMhc6N4mo{RQ$`4ojw@Uc%bOf4=8b4dJU
z?DSrqlvq2vjfL6$?2~LcAj{wv<~c}3jOcZ#nrN-$^8-b>cAo&+ePJFUdY^z9QL+$e
zjm#4yEK`DBsS`<}jHw(zIkXjw7UBMwjXo;vh@nwDsQfR&C>NA+K`BRcRvJc>>W6CZ
z*DLk*`ofUHbQlTi<bTVQirx2)k;M3PKrl=P!aPEByMP%{lKTwE@%qX9-$a6vVZSWT
z%P&mYPgGWyHD}U&TOMo9B%3nnY;mM%q<u@%md8ScTxb)oH|j^;U3(7llCZr=723Q8
zeu!cIja}aueY5Q^(mO`~@}D2<-8QnMY=07E=?BqU4sF1xx^UkC*qtso+UbVh<AHw$
za20;e5CcGUf|v$BCD1Kf*l^J(u;F|<YxFZ+M_ex$@w}lA#nV}~tEanTr@kq)Db&XF
z?%v&cGL=saqzgtW-@AKfCYMe1#``iUkQ^AwWu>GpSX~*>e?I<CftdIQ{aD&qT${cP
zTV#Vw&#jB`81^CbJB4`*PJIpY7A?4SJYKip*8W(p#<<EA@R#}l0;&ba{y^aub@zXu
zjlEl|jn{PFt1|8QjNx0F)yBSCdy!Z;U25xq?4^cI_*=Iw3^7a(V&1j6B?t}MFpX8Z
zHVaAA+xqX_rPrU<N<Y@dezLf)xBK!;3yd=D^7)xnNG`uo1A6X$ZLP|FIf?ui`$Ki>
zj`89qwTT_Sh74_@=0A{Zy>8qMCVma$VB&2{b9L)Rk@KRY!2c@eZ@YkG!wv2H4Zl`e
z)XvX8p(&TN*KZhWK*5kyP`fnOU$?HaERW@n?sx&RS@EueTIrqnXQ39CYQ_Lj4qu$S
z*k3jd>yP{kUqnXj`FB|tgZdn2AOZ4V^l|p1r6sL&JPZh?UgoKGnL5W)EtneTLRu+$
zUAr7z1X-qyM;Eonqu1-kjzK%w7>+lB2nHxi1#*K&qw`$s`9Gdt0)a0)3<~D8i8ZeX
zWx@pI0w_Xht>n|jqVvkaKS6nOf+aeK<rTJT;|CW(__~JN04lR%b5Cd`k(gLX3c20N
z747_w!M{P!Hm59{)h1qGXP1`FpvJ!&g+E&9`@hg$ghH+&1p2P>LWX&)Y@JXxtBtd|
zmyXq-itS4Ap|f$2Id=#;%gZD1hijex`bVIj_pbry@Sb`u2{j5Bc2!w80T#?k3ud_m
z9U!^LD|LNhr4JIbrAzqN;xf~yAb5>8p)xzMru8INc2-&VThMt$>b$~rJ_-u1cqo93
z(wbLd55yQqUr`ob1L+wlJ;SBfg7l0w{sJ~B=T$lHjI!_p$XSHWaR%ra&fCmm<5Hn%
zUENFIKky=OVPQhS8D-%z6n0t`cG@)cw8d23CwYUP*2b3!QQk*R3sX-?=~E!RSm=Qw
zPE|-_^J!aomoy$adjce!ZTG_usqJ2b$qgKFN?G_8=)%fP1D)o!{UMK)JBP3hv<F2-
zMHd{0X-hWH74Cu=ZR-Uv;fpRNeBLynQJ65TEF2dmTsZd}cC`~`S8E1dFmh43mi<qN
z*#_y9bjTE%TsQU)Fy?Fwe3)T31=mkX-br3P9AHyWq8wn8)&U0dT}AE80XBKl0d`Ur
za*`J^3<aFDw2;}C?E~yZ5OOxs)(@zWmh(z^=&=m2lVX64N()B01)I%kit#mSu|^Ii
z;271E*TnQOsw`ZD32g*=KiBj8-(!@|Wli8&OjtCCJ^^!5c{<}P%EBd3GE7Rwd6e7J
z2E2${l$cI|jwSNUA<C1=!Z}bjSXPEnQyEW`d#PC`RL1knA;^=cY&<#zSA!U885aa+
z+?|vtk7rT6SzxZWFk?QB>2ZPLtjo113#Y-(LuETL3U*EvV!+E2ZmNSqwIDch8v%e}
z^SVo?Sbv>5#m^xZ%0;cp!k@}2?Gvgv!77bFxdJn%sCHyguu8RpSrGIV=PY-8;mIp}
zHo0J^XWwwK=c~Vx_ADg97*wEK`y<qQ`M3r|_8^S%9&|e}VM1BBCM>>iZqh#1cY;C~
z>r=|LhheNwzB~ol^Y>#ZsOwc)U*PpV^11HP_amR}F1;T)7%6=e>Ft?lSRYi`L2aT5
z>4BaN@8DW${u}Ru&hsDnjdiVW$@NK3>4Toq`<<nqMV8k5KpVTLXj}iK_;0w*`uyR@
zA4CpEo{s3&H3nY~fdNSQ`b@6KaII+#L%GB=dj7}}-AEM-{fJoTrnAY^NGcghBv?aX
zTSMV?b|jOFCkvQT8#0+900kqLPZijKVj__$6qs_a|MBgh7}t_2m_G`1AJ9WUM}cO5
zZUL|0^*{xO;stOLXb`752zZ}?L3wsRQ$~Wyy(?GLPC{M~u>0V*_}<b|Gct6p2qM-3
zzm=eu*0k#}3w~3;hj}az><ZLBS$D@5YDd`<YaidZdHsV3qb{`N1jzm?E^;G*;0fQ(
zRm=T9TmeOL9bW=?A1sbiKv`EH_!VC?Q2%9rG@wo_iv}9MRHFr2PAt~~?PDu;1;W`t
zdnC{j2{d*D)Q&)XM<Cb{sO5Hl55z}657~(7s-fzEst2kbsCuC4fvN|p9;kYt>Vc{U
zsvf9%pz48}d0-Zvbzqp5RNgk5&wy6)T)6*T7Ur>4GTj~!=}*Wslg~x(mFZeZ*HT*M
z<9#v)%75?1QV!EozAzH=*>21)(s<vG;fybggx${nGWM*b_*@S|y&&vvNr}LYp$M=~
zg@JY{_`N)&X@3B3*)iaAKMaGizJ%AxG}#^FTnwIri$LYWZ8@*cytE&-B6ynox+v3c
z%6uvQe@5szw$p$&WPN`sDdz9mxpSM^2v2M`sO_P)P>Z^$Wm9WQTkB(L<Nj1q)#8T0
zn_Am8{5P1}@fjqxBksRo$J-TIuWTM}ZQ1fE#@5MxX;S3DAoyzX#cVd69Z&}n35QW2
zD>zNwcs85sOJ`kq&3-KP4rhu3z?zK@rM9V35Y<tC6XkE*wfA#uV-0kw<+idm@@`gV
z!ybV>FxV4IWa5QE#_qD^ZA|p*!}*+%N*L)}76%87Gg(g8-u=DZT~9H-k@$Ny*+=-3
z<3oq^$bkb<;M%+A0OULDS%Krg+%MvFe1LalhpyaE+R*#+P-}fS2T!U~`AS{O@p<`b
z`0*fgiMr)e@l1Lki?~;N(t9ODoo!TY&uV+Rjpge2#Ch?N>iDeAx6ltBsLr?I>Lai1
zzdP4YwYnaH{=e~Kw;sav9IkKiRa>Y1)TRxxZE;Oj=5=2WIAyBqt?K$2?whLjLlO7!
zQoSFN7tHGYZT0@Px?fSTe#XrZ+x}C$)%*sA_MY5$D37Qc4_()Zy7AEd>R-$KHa8yH
za}CSAS2vy(xrV@Z*fDsm3-DEU3~f@^$7LS|_p$y5_SN`)ontTTmiE<9@PBh(&0`(O
z?WZ<vkZpP^>qw`}&GeIA>NB^Z-znqOA89|3Xth5w_HpQs)%Lul`;L#z{8DYtYJ2{F
zzK{G}zy7<e`RIB~^ta`qwddd5WDQDd&!}8u;2P2^_~GGYyDwak?T4rEy{@>Q8Ls#;
z^Zfv;GC!=m=)C|tzMRGUVJpPrezt<SJ$LuR16O)pZx!;x(|vmGZ^v&p-w&|kcbM-<
z*zuKYM*7r_uQKm3?0A6DTHlV>G0nyAez<d?@5Al<tJ$0@KRm&e?_=2c?_#yC_!{{B
zJ!WO)aX-9mLEjBqGyS-7k?&jB@q1XKD_+mSuDJQs&#DH#8(+&}4^G=K*w%pW&VSCI
zk6SZ#V8XY`e2;+gc6;D)iPJii_=_I+ga`gt9{5EM{4EdsS04CEtT5EeX=j7PX@3~S
zG3<~y-KPqav8O!r6g}`4Jn)x1@V7kh4?Xa8xKeVd*LDy5u*9A9JtlFw=cf986L7bF
z@*T-f_d~@0s>Eq-CH!rPJN^G_5BzSwd%ZS!;0HYLoCp3D5B!t|{))t%_5F#&>AsEX
ztH8&p*e*_7mAKPCI{<g{vj(^i-fp3N3ex|i#A9;bg7Cu<pLXB{z!iAwi{=gNP8j}#
z<CXK+H>DnW-%W5c_8rb&IUjxxa5wwC>h(*mXEpn7U6@px)J>0%ZyMZLG2h+=xB_pb
zIp^E^B)@asZsvI9{NKU#RL;YP0KXIcFRu$+94sA#h-z9~j=atB%6S{UW_LX|<7<Ei
z;VrsH)mT{x#Qq%c)zDt}!8s4I!TL~-ukw2LZ4do39{7&{$8w$5mv;eIMTxe*9|FGG
zSI71_u8+0L(a!R97MhiZdjLnj(RfKo{9(=y^`iR9di4SgVtpTsNlrmpP!EhFny<hN
z9^Qcn>ZkdnS>hV-qaLR}d!;?J&&R(x1evGM9^XBzh3t`fQh=*6ZY2+(9-qs)rMXzh
z;~_82@HS2}obIA;d8{d)N)E;iapFsJdvhpM{tujR984l_w1#plBwv`*)7i8UN;uPc
zDw}j-p~0Nt#E{Po4;8bS^fRf<QC9)4%n<DP=8fX8tB^-tC^eFHH_M&@;zl~5=Tn(n
z!dhQDZm+jJ&t6Y^UZo%G`7ZvjGjIi!ez7xE`p2Hnl>lV-p`FL!FMB3eVE3Dz%m}B&
zjT9bfgH9Yyr-UixhVo*=ew51eH}P(kJ5Uw?u%hpkF*L-D*WLzpey=<i-#Y{={a$9M
z^m#eY-QVSWhp)>SZhjWW4J8Ui;TGPEWf#cPh|Fx8e=M2(;OL6BDXZq$C=1g-!6?GX
zGznHd#Yi`X;N{m`7C!FQ^<+*T$mIIs89fQ#dl&S0afBsuL&KSr0pEvzYIDnGcP1Un
z(Bt`h{3uk@$RB0mWz}SHXy_=2SW>*EHrC(tO}egk?T_q^>d`%&I-IOzSCC|S=Tmzk
zySsPVbA&5(9bSvpqngy9b?#^SuAaReksf_-SJ#1PuihK!=!v3Me()2z8mn^Cqn_}<
zsBqYJFjOiTH{$F_zF+5+;UCn?Go>7y&I6{L*{DdIA_X?tkCf7rg`7SZ&nEG>sqVeN
zl}u;#Vj%@SD4UOi&a{Mi3{ep1D->io{G2OYhvTfs#dyw@`{7lg!qFik-p8Q3<pmw2
z7=JAprtvJiFCB_>bT=9C0ht=e7DIi-G@MG7h7pdbL44aflsuXReS#W!k#i)KFW}48
zoJ}Tl$b(5djsh|^oPi4fuWQIijX<0?TPUC7EfGo$%04%k1X)T63DNn41jRvdd?*c<
z!~wkC!JiN>Kqv!Ou@DS{A?Vt|E?${X+%WR#z9Jl@V7+wzR&o431D7axn}UJ%XXqS0
z`aVPC3SNpMeF%Ol;79Vbk3;9&sgP$4w0<J26(Ux7+V3%>!u7-`sZ+iaa5!QiN99lX
z!klwT0%Sj}t8g#O8umZ}_qa)(_K(g;;FM&BWfAui$=6H#vq1guBl(y=%yVK0LZI(b
zM5@w%PeTTN6GHN|AN8h`m&g8@&lHJ|=rbUX-<VLE_O0fnyebQJ+Am>lANrK!X@9F$
zIyxp9o&KZxAA@{k?T~zf%fdW1DCJuuj`H~Y%IUu^1BU$%?ZZINy{Du+eLo~}MOhR_
zT7sWdp7zyd9OaV?f2I!!qF;5$(|UVR%17yg9;txjNZ;2T^0ZIaE*lP?pIU=dYeLfy
zvyMO7&(oy*A(K-?$bST5|Fp`}z8{?zxt$m#b(a5<L!R~r=VbZw4tZz!Gmww0vb&Y{
z5#{-qPJT)g{YQ|+=l3K}`;E1?D1Q}XvG0&P-6zxeoOBK+^)D)y+VO3WMgNgJ?O)Ex
z2hJ+wSp&%v{V8Nx<(V22?5ZG*f|!3vj_A)I$0|?vtBtA<akdxoTElygKwV@%?SDL~
z3NDofwn#Dw%M@cDKn!)Zn23mw{O>z(DxatyA~=6jpncerszA<sl5zxftB=D(&KUl*
z;J+%zAI{_Z;YWU>`3JM9?m|NRt=9y7jv8KOlHJ6M-z~Yx|JfeF@d<~3Bgy^?<_-7^

literal 0
HcmV?d00001

diff --git a/sw/tests/mock_rvv_test_vstart_indexed.cc b/sw/tests/mock_rvv_test_vstart_indexed.cc
new file mode 100644
index 00000000..a8f0fbc1
--- /dev/null
+++ b/sw/tests/mock_rvv_test_vstart_indexed.cc
@@ -0,0 +1,239 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// #include "regs/cheshire.h"
+// #include "dif/clint.h"
+// #include "dif/uart.h"
+// #include "params.h"
+// #include "util.h"
+// #include "encoding.h"
+// #include "rvv_test.h"
+
+///////////////////////////////////////////////////////////////////////////////
+// Mock logic
+// Build with:
+// gcc mock_rvv_test_vstart_indexed.cc -o mock_rvv_test_vstart_indexed
+
+#include <stdio.h>
+#include <stdint.h>
+
+#define ARA_NR_LANES                                2
+#define VLMAX                                       (1024 * ARA_NR_LANES)
+#define RVV_TEST_AVL(EEW)                           (VLMAX / (EEW))
+#define RVV_TEST_INIT(vl, avl)                      vl = ( avl );
+#define RVV_TEST_ASSERT( expression, file, line )   if ( !(expression) ) { printf("%s:%s\n", file, line); return 1; }
+#define RVV_TEST_PASSED()                           printf("Success\n");
+#define RVV_TEST_CLEANUP(msg,val)                   printf("%s: %llu\n", msg, val);
+uint64_t vrf_mock       [RVV_TEST_AVL(64)]; 
+uint64_t vrf_mock_index [RVV_TEST_AVL(64)];
+  
+///////////////////////////////////////////////////////////////////////////////
+
+#define BIT_SHIFT         5
+#define INDEXED_MEM_SIZE  ( RVV_TEST_AVL(64) << BIT_SHIFT )
+
+int main(void) {
+    // Vector configuration parameters and variables
+    uint64_t avl = RVV_TEST_AVL(64);
+    uint64_t vl;
+    // vcsr_dump_t vcsr_state = {0};
+
+    // Helper variables and arrays
+    uint64_t array_load [INDEXED_MEM_SIZE]; // oversize this
+    uint64_t array_store[INDEXED_MEM_SIZE]; // oversize this
+
+    uint64_t* address_load = array_load;
+    uint64_t* address_store = array_store;
+    uint64_t store_val, preload_val, prestart_val;
+
+    // Simplification: EEW-wide indexes
+    uint64_t array_index [RVV_TEST_AVL(64)] ;
+    uint64_t* address_index = array_index;
+
+    // Enalbe RVV
+    // enable_rvv();
+    // vcsr_dump ( vcsr_state );
+
+    //////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////
+    // START OF TESTS
+    //////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////
+
+    //////////////////////////////////////////////////////////////////
+    // TEST: Zero and non-zero vstart indexed load
+    //////////////////////////////////////////////////////////////////
+    RVV_TEST_INIT( vl, avl );
+
+    // Loop over vstart values
+    for ( uint64_t vstart_val = 0; vstart_val < vl; vstart_val++ ) {
+      RVV_TEST_INIT( vl, avl );
+      
+      preload_val = -1;
+      prestart_val = -2;
+
+      // Init source memory 
+      for ( uint64_t i = 0; i < INDEXED_MEM_SIZE; i++ ) {
+          address_load[i] = preload_val;
+      }
+      // Init index memory
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          // Constrain the target memory space to +/- (2^BIT_SHIFT)*sizeof(uint64_t) bytes
+          // NOTE:to ease testing, indexes should not overlap
+          address_index[i] = (((2 << BIT_SHIFT) -1) & ( vstart_val + vl + i )) * sizeof(uint64_t);
+          // printf("%llu ", address_index[i]);
+      }
+
+      // Compose a mask for indexed memory:
+      //  - 0: the element must to be left untouched
+      //  - 1: the element is a target
+      uint8_t bit_mask_indexed [INDEXED_MEM_SIZE] = {0};
+      for ( uint64_t i = 0; i < vl; i++ ) {
+        // Check for overlapping indexes
+        if ( bit_mask_indexed[ address_index[ i ] ] == 1 ) {
+          RVV_TEST_ASSERT ( 0, __FILE__, __LINE__ );
+        }
+        bit_mask_indexed[ address_index[ i ] ] = 1;
+      }
+      // Init indexed memory
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          *( ((uint8_t*)address_load) + address_index[i] ) = vstart_val + vl + i;
+      }
+
+      // Load index array
+      // asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_index));
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          vrf_mock_index[i] = address_index[i];
+      }
+      
+      // Load prestart
+      // asm volatile ("vmv.v.x	v24   , %0" :: "r"(prestart_val));
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          vrf_mock[i] = prestart_val;
+      }
+
+      // Set vstart
+      // asm volatile ("csrs     vstart, %0"   :: "r"(vstart_val) );
+      // Test target: load (gather) vr group body from indexed memory
+      // asm volatile ("vluxei64.v	v24   , (%0), v0" : "+&r"(address_load));
+      for ( uint64_t i = vstart_val; i < vl; i++ ) {
+          vrf_mock[i] = *( ((uint8_t*)address_load) + vrf_mock_index[i]) ;
+      }
+      
+      // Store whole vr group back to memory
+      // asm volatile ("vse64.v	v24   , (%0)" : "+&r"(address_store));
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          address_store[i] = vrf_mock[i];
+      }
+
+      // Check pre-start
+      for ( uint64_t i = 0; i < vstart_val; i++ ) {
+          RVV_TEST_ASSERT ( address_store[i] == prestart_val, __FILE__, __LINE__ );
+      }
+      // Check body
+      for ( uint64_t i = vstart_val; i < vl; i++ ) {
+          RVV_TEST_ASSERT ( address_store[i] == *( ((uint8_t*)address_load) + address_index[i] ), __FILE__, __LINE__ );
+      }
+
+      RVV_TEST_CLEANUP("vloads", vstart_val);
+    }
+
+
+    //////////////////////////////////////////////////////////////////
+    // TEST: Zero and non-zero vstart indexed stores
+    //////////////////////////////////////////////////////////////////
+    RVV_TEST_INIT( vl, avl );
+
+    // Loop over vstart values
+    for ( uint64_t vstart_val = 0; vstart_val < vl; vstart_val++ ) {
+      RVV_TEST_INIT( vl, avl );
+        
+      preload_val = 1;
+
+      // Init index memory
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          // Constrain the target memory space to +/- X*sizeof(uint64_t) bytes
+          // NOTE: to ease testing, indexes should not overlap
+          // NOTE: simplification, align offsets to 64-bits words
+          address_index[i] = (((2 << BIT_SHIFT) -1) & ( vstart_val + vl + i )) * sizeof(uint64_t);
+          // printf("%llu ", address_index[i]);
+      }
+      // Compose a mask for indexed memory:
+      //  - 0: the element must to be left untouched
+      //  - 1: the element is a target
+      uint8_t bit_mask_indexed [INDEXED_MEM_SIZE] = {0};
+      for ( uint64_t i = 0; i < vl; i++ ) {
+        // Check for overlapping indexes
+        if ( bit_mask_indexed[ address_index[ i ] ] == 1 ) {
+          RVV_TEST_ASSERT ( 0, __FILE__, __LINE__ );
+        }
+        bit_mask_indexed[ address_index[ i ] ] = 1;
+      }
+      // Init source memory
+      for ( uint64_t i = 0; i < vl; i++ ) {
+        address_load[i] = vstart_val + vl + i;
+      }
+      // Init whole target memory
+      for ( uint64_t i = 0; i < INDEXED_MEM_SIZE; i++ ) {
+        address_store[i] = preload_val;
+      }
+
+      // Load index array
+      // asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_index));
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          vrf_mock_index[i] = address_index[i];
+      }
+
+      // Load data        
+    //   asm volatile ("vle64.v	v24   , (%0)" : "+&r"(address_load));
+      for ( uint64_t i = 0; i < vl; i++ ) {
+          vrf_mock[i] = address_load[i];
+      }
+
+      // Set vstart
+    //   asm volatile ("csrs       vstart, %0"   :: "r"(vstart_val) );
+      // Test target: store (scatter) vr group body to indexed memory
+    //   asm volatile ("vsuxei64.v	v24   , (%0), v0" : "+&r"(address_store));
+      for ( uint64_t i = vstart_val; i < vl; i++ ) {
+        uint64_t* dest_addr = (uint64_t*)( ((uint8_t*)address_store) + address_index[i] );
+        *dest_addr = vrf_mock[i];
+      }
+
+
+      // Check pre-start
+      for ( uint64_t i = 0; i < vstart_val; i++ ) {
+        uint64_t* dest_addr = (uint64_t*)( ((uint8_t*)address_store) + address_index[i] );
+        RVV_TEST_ASSERT ( *dest_addr == preload_val, __FILE__, __LINE__ );
+      }
+      // Check body
+      for ( uint64_t i = vstart_val; i < vl; i++ ) {
+        uint64_t* dest_addr = (uint64_t*)( ((uint8_t*)address_store) + address_index[i] );
+        RVV_TEST_ASSERT ( *dest_addr == address_load[i], __FILE__, __LINE__ );
+      }
+      // Check untouched memory
+      for ( uint64_t i = 0; i < INDEXED_MEM_SIZE; i++ ) {
+          if ( bit_mask_indexed == 0 ) {
+            RVV_TEST_ASSERT ( address_store[i] == preload_val, __FILE__, __LINE__ );
+          }
+      }
+
+      RVV_TEST_CLEANUP("vstores", vstart_val);
+    }
+
+    //////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////
+    // END OF TESTS
+    //////////////////////////////////////////////////////////////////
+    //////////////////////////////////////////////////////////////////
+
+RVV_TEST_pass:
+    RVV_TEST_PASSED() 
+
+// RVV_TEST_error:
+//     RVV_TEST_FAILED()
+  
+  return 0;
+}
diff --git a/sw/tests/rvv_test.h b/sw/tests/rvv_test.h
index 8b1abb3d..02987f9b 100644
--- a/sw/tests/rvv_test.h
+++ b/sw/tests/rvv_test.h
@@ -9,7 +9,11 @@
 // Quick workaround:
 #define RVV_TEST_ASSERT( expression )     if ( !(expression) ) { goto RVV_TEST_error; }
 #define RVV_TEST_ASSERT_EXCEPTION( val )  RVV_TEST_ASSERT ( exception == (uint64_t)(val) );
-#define RVV_TEST_CLEAN_EXCEPTION()        exception = 0;
+#define RVV_TEST_ASSERT_EXCEPTION_EXTENDED( valid, tval, cause )  RVV_TEST_ASSERT ( ( exception == (uint64_t)(valid) )    \
+                                                                            & ( mtval == (uint64_t)(tval) ) \
+                                                                            & ( mcause == (uint64_t)(cause) ) \
+                                                                            );
+#define RVV_TEST_CLEAN_EXCEPTION()        exception = 0; mtval = 0; mcause = 0;
 #define RVV_TEST_PASSED()                 asm volatile ( "li %0, %1" : "=r" (magic_out) : "i"(RVV_TEST_MAGIC));
 #define RVV_TEST_FAILED()                 asm volatile ( "nop;nop;nop;nop;" );
 
@@ -21,6 +25,8 @@
 // Helper test variables
 typedef uint64_t vcsr_dump_t [5];
 uint64_t exception;
+uint64_t mtval;
+uint64_t mcause;
 uint64_t magic_out;
 
 void enable_rvv() {
@@ -61,7 +67,17 @@ void vcsr_dump ( vcsr_dump_t vcsr_state ) {
 
 // Override default weak trap vector
 void trap_vector () {
+    // Set exception flag
     exception = 1;
+
+    // Save tval and mcause
+    mtval = 0;
+    mcause = 0;
+    asm volatile ("csrr %0, mtval" : "=r"(mtval));
+    asm volatile ("csrr %0, mcause" : "=r"(mcause));
+
+    // Move PC ahead
+    // NOTE: PC = PC + 4, valid only for non-compressed trapping instructions
     asm volatile (
         "nop;"
         "csrr	t6, mepc;" 
diff --git a/sw/tests/rvv_test_mmu_stub.c b/sw/tests/rvv_test_vstart_mmu_stub_page_fault.c
similarity index 57%
rename from sw/tests/rvv_test_mmu_stub.c
rename to sw/tests/rvv_test_vstart_mmu_stub_page_fault.c
index b0a05eee..fd119949 100644
--- a/sw/tests/rvv_test_mmu_stub.c
+++ b/sw/tests/rvv_test_vstart_mmu_stub_page_fault.c
@@ -12,13 +12,11 @@
 #include "encoding.h"
 #include "rvv_test.h"
 
-// TODO: Run both exception and no exception tests in the same run
-
 int main(void) {
 
     // Vector configuration parameters and variables
     uint64_t avl = RVV_TEST_AVL(64);
-    uint64_t vl;
+    uint64_t vl, vstart_read;
     vcsr_dump_t vcsr_state = {0};
 
     // Helper variables and arrays
@@ -38,7 +36,29 @@ int main(void) {
     //////////////////////////////////////////////////////////////////
 
     //////////////////////////////////////////////////////////////////
-    // TEST: No exceptions, interaction with vstart
+    // TEST: Exception generation: vector load
+    //////////////////////////////////////////////////////////////////
+    // RVV_TEST_INIT( vl, avl );
+
+    // asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_load));
+    // RVV_TEST_ASSERT_EXCEPTION_EXTENDED(1, address_load, CAUSE_LOAD_PAGE_FAULT)
+    // RVV_TEST_CLEAN_EXCEPTION()
+    
+    // RVV_TEST_CLEANUP();
+
+    // //////////////////////////////////////////////////////////////////
+    // // TEST: Exception generation: vector store
+    // //////////////////////////////////////////////////////////////////
+    // RVV_TEST_INIT( vl, avl );
+
+    // asm volatile ("vse64.v	v0   , (%0)" : "+&r"(address_store));
+    // RVV_TEST_ASSERT_EXCEPTION_EXTENDED(1, address_store, CAUSE_STORE_PAGE_FAULT)
+    // RVV_TEST_CLEAN_EXCEPTION()
+    
+    // RVV_TEST_CLEANUP();
+    
+    //////////////////////////////////////////////////////////////////
+    // TEST: Exception generation and non-zero vstart: vector load
     //////////////////////////////////////////////////////////////////
     // RVV_TEST_INIT( vl, avl );
 
@@ -46,51 +66,38 @@ int main(void) {
     // for ( uint64_t vstart_val = 0; vstart_val < vl; vstart_val++ ) {
     //   RVV_TEST_INIT( vl, avl );
 
-    //   // Init memory
-    //   for ( uint64_t i = 0; i < vl; i++ ) {
-    //     address_load[i] = i;
-    //   }
-
-    //   asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_load));
     //   asm volatile ("csrs     vstart, %0"   :: "r"(vstart_val) );
-    //   asm volatile ("vadd.vv  v0, v0, v0");
-    //   asm volatile ("vse64.v	v0   , (%0)" : "+&r"(address_store));
-
-    //   // Check pre-start
-    //   for ( uint64_t i = 0; i < vstart_val; i++ ) {
-    //     RVV_TEST_ASSERT ( address_store[i] == i );
-    //   }
-    //   // Check body
-    //   for ( uint64_t i = vstart_val; i < vl; i++ ) {
-    //     RVV_TEST_ASSERT ( address_store[i] == 2*i );
-    //   }
+    //   asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_load));
+    //   RVV_TEST_ASSERT_EXCEPTION_EXTENDED(1, address_load + vstart_val, CAUSE_LOAD_PAGE_FAULT)
+    //   RVV_TEST_CLEAN_EXCEPTION()
 
+    //   vstart_read = -1;
+    //   asm volatile ("csrr  %0, vstart"  : "=r"(vstart_read) );
+    //   RVV_TEST_ASSERT ( vstart_read == vstart_val )
+    
     //   RVV_TEST_CLEANUP();
     // }
 
     //////////////////////////////////////////////////////////////////
-    // TEST: Exception generation: vector load
+    // TEST: Exception generation and non-zero vstart: vector store
     //////////////////////////////////////////////////////////////////
     RVV_TEST_INIT( vl, avl );
 
-    asm volatile ("vle64.v	v0   , (%0)" : "+&r"(address_load));
-    RVV_TEST_ASSERT_EXCEPTION(1)
-    RVV_TEST_ASSERT_MTVAL(address_load)
-    RVV_TEST_CLEAN_EXCEPTION()
-    
-    RVV_TEST_CLEANUP();
+    // Loop over vstart values
+    for ( uint64_t vstart_val = 0; vstart_val < vl; vstart_val++ ) {
+      RVV_TEST_INIT( vl, avl );
 
-    //////////////////////////////////////////////////////////////////
-    // TEST: Exception generation: vector stores
-    //////////////////////////////////////////////////////////////////
-    RVV_TEST_INIT( vl, avl );
+      asm volatile ("csrs     vstart, %0"   :: "r"(vstart_val) );
+      asm volatile ("vse64.v	v0   , (%0)" : "+&r"(address_store));
+      RVV_TEST_ASSERT_EXCEPTION_EXTENDED(1, address_store + vstart_val, CAUSE_STORE_PAGE_FAULT)
+      RVV_TEST_CLEAN_EXCEPTION()
 
-    asm volatile ("vse64.v	v0   , (%0)" : "+&r"(address_store));
-    RVV_TEST_ASSERT_EXCEPTION(1)
-    RVV_TEST_ASSERT_MTVAL(address_store)
-    RVV_TEST_CLEAN_EXCEPTION()
+      vstart_read = -1;
+      asm volatile ("csrr  %0, vstart"  : "=r"(vstart_read) );
+      RVV_TEST_ASSERT ( vstart_read == vstart_val )
     
-    RVV_TEST_CLEANUP();
+      RVV_TEST_CLEANUP();
+    }
 
     //////////////////////////////////////////////////////////////////
     //////////////////////////////////////////////////////////////////
diff --git a/sw/tests/rvv_test_vstart_strided_mmu_stub.c b/sw/tests/rvv_test_vstart_strided_mmu_stub.c
new file mode 100644
index 00000000..467454c3
--- /dev/null
+++ b/sw/tests/rvv_test_vstart_strided_mmu_stub.c
@@ -0,0 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// Keep the source code is exactly the same
+// Just enable MMU stub with the name of this file
+#include "rvv_test_vstart_strided.c"
diff --git a/sw/tests/rvv_test_vstart_strided_mmu_stub_page_fault.c b/sw/tests/rvv_test_vstart_strided_mmu_stub_page_fault.c
new file mode 100644
index 00000000..35add107
--- /dev/null
+++ b/sw/tests/rvv_test_vstart_strided_mmu_stub_page_fault.c
@@ -0,0 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// Keep the source code is exactly the same
+// Just enable MMU stub and page fault generation with the name of this file
+#include "rvv_test_vstart_strided.c"
diff --git a/sw/tests/rvv_test_vstart_unit_stride_mmu_stub.c b/sw/tests/rvv_test_vstart_unit_stride_mmu_stub.c
new file mode 100644
index 00000000..c80a63d8
--- /dev/null
+++ b/sw/tests/rvv_test_vstart_unit_stride_mmu_stub.c
@@ -0,0 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// Keep the source code is exactly the same
+// Just enable MMU stub with the name of this file
+#include "rvv_test_vstart_unit_stride.c"
diff --git a/sw/tests/rvv_test_vstart_unit_stride_mmu_stub_page_fault.c b/sw/tests/rvv_test_vstart_unit_stride_mmu_stub_page_fault.c
new file mode 100644
index 00000000..c80a63d8
--- /dev/null
+++ b/sw/tests/rvv_test_vstart_unit_stride_mmu_stub_page_fault.c
@@ -0,0 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// Keep the source code is exactly the same
+// Just enable MMU stub with the name of this file
+#include "rvv_test_vstart_unit_stride.c"
diff --git a/sw/tests/rvv_test_vstart_vadd_mmu_stub.c b/sw/tests/rvv_test_vstart_vadd_mmu_stub.c
new file mode 100644
index 00000000..31148002
--- /dev/null
+++ b/sw/tests/rvv_test_vstart_vadd_mmu_stub.c
@@ -0,0 +1,9 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Vincenzo Maisto <vincenzo.maisto2@unina.it>
+
+// Keep the source code is exactly the same
+// Just enable MMU stub with the name of this file
+#include "rvv_test_vstart_vadd.c"
diff --git a/target/common/ara.mk b/target/common/ara.mk
index 5233b9e9..741341ce 100644
--- a/target/common/ara.mk
+++ b/target/common/ara.mk
@@ -54,7 +54,7 @@ ifeq ($(ARA),1)
 # 		BENDER_ARA_DEFS += --define ARA_INTEGRATION_V0_3 (not yet implemented)
 #	endif
 else
-# 	Exclude RVV
+# 	Exclude V from MISA
 	BENDER_ARA_TARGETS += -t cv64a6_imafdc_sv39
 endif
 
@@ -62,6 +62,6 @@ endif
 # # Instantiate MMU interface in CVA6 and Ara
 # BENDER_ARA_DEFS += --define ACC_MMU_INTERFACE
 # Prioritize Ara translation requests to MMU
-BENDER_ARA_DEFS += --define MMU_ACC_PRIORITY
+# BENDER_ARA_DEFS += --define MMU_ACC_PRIORITY
 
 xilinx_targs := $(BENDER_ARA_TARGETS) $(BENDER_ARA_DEFS)
\ No newline at end of file
diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
index 2c7ebac8..df66b95d 100644
--- a/target/sim/src/fixture_cheshire_soc.sv
+++ b/target/sim/src/fixture_cheshire_soc.sv
@@ -57,6 +57,12 @@ module fixture_cheshire_soc;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;
 
+  logic xvio_mmu_exception;
+  logic xvio_en_ld_st_translation;
+  // Force these in simulation
+  assign xvio_mmu_exception = '0; 
+  assign xvio_en_ld_st_translation = '0;
+  
   cheshire_soc #(
     .Cfg                ( DutCfg ),
     .ExtHartinfo        ( '0 ),
@@ -69,6 +75,8 @@ module fixture_cheshire_soc;
     .reg_ext_req_t      ( reg_req_t ),
     .reg_ext_rsp_t      ( reg_rsp_t )
   ) dut (
+    .xvio_en_ld_st_translation_i ( xvio_en_ld_st_translation ),
+    .xvio_mmu_exception_i ( xvio_mmu_exception ),
     .clk_i              ( clk       ),
     .rst_ni             ( rst_n     ),
     .test_mode_i        ( test_mode ),
diff --git a/target/sim/vsim/mmu_stub_run.tcl b/target/sim/vsim/mmu_stub_run.tcl
index 9890c2d8..bd530b8f 100644
--- a/target/sim/vsim/mmu_stub_run.tcl
+++ b/target/sim/vsim/mmu_stub_run.tcl
@@ -1,8 +1,15 @@
 
 add wave sim:/tb_cheshire_soc/fix/dut/xvio_mmu_exception_i
 add wave sim:/tb_cheshire_soc/fix/dut/xvio_en_ld_st_translation_i
-add wave -group mmu_stub sim:/tb_cheshire_soc/fix/dut/gen_cva6_cores[0].i_mmu_stub/*
+
+if { $::env(MMU_STUB) eq "1"} {
+    add wave -group mmu_stub sim:/tb_cheshire_soc/fix/dut/gen_cva6_cores[0].i_mmu_stub/*
+}
 run 100
-force -deposit sim:/tb_cheshire_soc/fix/dut/xvio_mmu_exception_i        1'h1 0
-force -deposit sim:/tb_cheshire_soc/fix/dut/xvio_en_ld_st_translation_i 1'h1 0
+if {[string first "mmu_stub" $BINARY] != -1} {
+    force -deposit sim:/tb_cheshire_soc/fix/dut/xvio_mmu_exception_i 1'h1 0
+    if {[string first "page_fault" $BINARY] != -1} {
+        force -deposit sim:/tb_cheshire_soc/fix/dut/xvio_en_ld_st_translation_i 1'h1 0
+    }
+}
 run -a
diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl
index 0d1dea22..312933fa 100644
--- a/target/sim/vsim/start.cheshire_soc.tcl
+++ b/target/sim/vsim/start.cheshire_soc.tcl
@@ -13,7 +13,7 @@ set TESTBENCH tb_cheshire_soc
 # Default on fast simulation flags.
 if {![info exists VOPTARGS]} {
     # Log all signals
-    set VOPTARGS "-O5 -permissive +acc=p+tb_cheshire_soc/fix/dut. -debugdb"
+    set VOPTARGS "-O5 -permissive +acc=+tb_cheshire_soc/fix/dut. -debugdb"
 }
 
 # Suppress (vopt-7033) Variable '' driven in a combinational block, may not be driven by any other process.
@@ -28,5 +28,7 @@ if {[info exists IMAGE]}    { append pargs "+IMAGE=${IMAGE} " }
 
 eval "vsim -c ${TESTBENCH} -t 1ns -vopt -debugdb -voptargs=\"${VOPTARGS}\"" ${pargs} ${flags}
 
+log -r /*
+
 set StdArithNoWarnings 1
 set NumericStdNoWarnings 1
diff --git a/target/sim/vsim/vsim.mk b/target/sim/vsim/vsim.mk
index 4df505c7..69ff3651 100644
--- a/target/sim/vsim/vsim.mk
+++ b/target/sim/vsim/vsim.mk
@@ -36,9 +36,8 @@ chs-sim-run: $(CHS_VSIM_DIR)/compile.cheshire_soc.tcl $(CHS_VSIM_DIR)/start.ches
 	cd $(VSIM_ROOT); $(VSIM) $(VSIM_ARGS) -do $(word 1,$^) \
 						-do "set BINARY $(BINARY)" \
 						-do $(word 2,$^) \
-						-do "log -r /*"  \
 						-do $(word 3,$^) \
-						-do "run -a"
+						-do $(CHS_VSIM_DIR)/mmu_stub_run.tcl
 
 # Remove the simulation prefix
 $(CHS_VSIM_DIR)/%.post-sim.tcl: $(CHS_VSIM_DIR)/%.tcl
diff --git a/target/xilinx/scripts/tcl/debug_gui.tcl b/target/xilinx/scripts/tcl/debug_gui.tcl
index 04506cab..fc058cd3 100644
--- a/target/xilinx/scripts/tcl/debug_gui.tcl
+++ b/target/xilinx/scripts/tcl/debug_gui.tcl
@@ -38,6 +38,11 @@ set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes {i_cheshire_soc/gen_cva
 # CVA6 exception valid
 # set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes {i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/commit_stage_i/exception_o[valid]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu37p_0] -filter {CELL_NAME=~"u_ila_0"}]]
 
+# Debug, PC hang
+set_property TRIGGER_COMPARE_VALUE eq1'bR [get_hw_probes {i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/commit_stage_i/commit_instr_i[0][valid]} -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu37p_0] -filter {CELL_NAME=~"u_ila_0"}]]
+set_property TRIGGER_COMPARE_VALUE eq64'hFFFF_FFFF_8000_331X [get_hw_probes {i_cheshire_soc/gen_cva6_cores[0].i_core_cva6/pc_commit} -of_objects [get_hw_ilas -of_objects [get_hw_devices xcvu37p_0] -filter {CELL_NAME=~"u_ila_0"}]]
+
+
 # Set trigger control
 set_property CONTROL.TRIGGER_CONDITION OR [get_hw_ilas -of_objects [get_hw_devices xcvu37p_0] -filter {CELL_NAME=~"u_ila_0"}]
 set_property CONTROL.TRIGGER_POSITION 4096 [get_hw_ilas -of_objects [get_hw_devices xcvu37p_0] -filter {CELL_NAME=~"u_ila_0"}]
diff --git a/target/xilinx/src/cheshire_top_xilinx.sv b/target/xilinx/src/cheshire_top_xilinx.sv
index 968537b5..84fe0ae7 100644
--- a/target/xilinx/src/cheshire_top_xilinx.sv
+++ b/target/xilinx/src/cheshire_top_xilinx.sv
@@ -133,6 +133,9 @@ module cheshire_top_xilinx
     Dma               : 1,
     SerialLink        : 0,
     Vga               : 1,
+    AxiRt             : 0,
+    Clic              : 0,
+    IrqRouter         : 0,
     // Debug
     DbgIdCode         : CheshireIdCode,
     DbgMaxReqs        : 4,
@@ -267,7 +270,8 @@ module cheshire_top_xilinx
   ///////////////////
   // VIOs          //
   ///////////////////
-
+  logic       xvio_mmu_exception;
+  logic       xvio_en_ld_st_translation;
   logic       vio_reset, vio_boot_mode_sel;
   logic [1:0] boot_mode, vio_boot_mode;
 
@@ -276,7 +280,9 @@ module cheshire_top_xilinx
     .clk(soc_clk),
     .probe_out0(vio_reset),
     .probe_out1(vio_boot_mode),
-    .probe_out2(vio_boot_mode_sel)
+    .probe_out2(vio_boot_mode_sel),
+    .probe_out3(xvio_mmu_exception),
+    .probe_out4(xvio_en_ld_st_translation)    
   );
 `else
   assign vio_reset = '0;
@@ -514,6 +520,8 @@ module cheshire_top_xilinx
     .reg_ext_req_t      ( reg_req_t ),
     .reg_ext_rsp_t      ( reg_req_t )
   ) i_cheshire_soc (
+    .xvio_en_ld_st_translation_i ( xvio_en_ld_st_translation ),
+    .xvio_mmu_exception_i ( xvio_mmu_exception ),
     .clk_i              ( soc_clk ),
     .rst_ni             ( rst_n   ),
     .test_mode_i        ( testmode_i ),
diff --git a/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl b/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl
index 4d563236..eb07105b 100644
--- a/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl
+++ b/target/xilinx/xilinx/xlnx_vio/tcl/run.tcl
@@ -15,10 +15,12 @@ set_property board_part $boardName [current_project]
 create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $ipName
 
 if {$::env(BOARD) eq "vcu128"} {
-set_property -dict [list CONFIG.C_NUM_PROBE_OUT {3} \
+set_property -dict [list CONFIG.C_NUM_PROBE_OUT {5} \
                          CONFIG.C_PROBE_OUT0_INIT_VAL {0x0} \
                          CONFIG.C_PROBE_OUT1_INIT_VAL {0x2} \
                          CONFIG.C_PROBE_OUT2_INIT_VAL {0x1} \
+                         CONFIG.C_PROBE_OUT3_INIT_VAL {0x0} \
+                         CONFIG.C_PROBE_OUT4_INIT_VAL {0x0} \
                          CONFIG.C_PROBE_OUT1_WIDTH {2} \
                          CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
                          CONFIG.C_NUM_PROBE_IN {0} \
diff --git a/util.mk b/util.mk
index a94d1068..9197fa39 100644
--- a/util.mk
+++ b/util.mk
@@ -10,6 +10,10 @@
 
 ## NOTE: this is very much not the correct way to do it, but time is tight...
 
+MMU_STUB ?= 1
+ifeq ($(MMU_STUB), 1)
+	BENDER_ARA_DEFS += --define MMU_STUB
+endif
 # Test macros
 RVV_TEST_MAGIC 			?= f0f0f0f0f0f0f0f0
 RVV_TEST_ARA_NR_LANES 	?= 2 4 #8
@@ -18,6 +22,8 @@ ALIGN_VSTORES := $(shell echo "32 * $(ARA_NR_LANES) / 8" | bc -l | sed -E "s/\..
 
 # Software artifacts
 CHS_SW_RVV_TEST_DIR ?= $(CHS_SW_DIR)/tests
+CHS_SW_RVV_TEST_HDRS := $(CHS_SW_RVV_TEST_DIR)/rvv_test.h
+
 RVV_TEST_SRC 	?= $(wildcard $(CHS_SW_RVV_TEST_DIR)/rvv_test_*.c)
 RVV_TEST_ELF 	?= $(RVV_TEST_SRC:.c=.spm.elf)
 
@@ -39,13 +45,14 @@ rvv-test-run rvv-test-report: RVV_TEST_RESULT_FILE=$(RVV_TEST_RESULT_DIR)/result
 rvv-test-run rvv-test-report: RVV_TEST_RESULT_DIR_LANES=$(RVV_TEST_RESULT_DIR)/ara_$(ARA_NR_LANES)_lanes
 rvv-test-run rvv-test-report: RVV_TEST_TRACE=$(RVV_TEST_RESULT_DIR)/ara_$(ARA_NR_LANES)_lanes/trace_hart_0.log 
 rvv-test-run rvv-test-report: VSIM_ROOT=$(RVV_TEST_RESULT_DIR_LANES)
-rvv-test-run: chs-sw-all
+#	TODO: add switch to stop on first failure
+rvv-test-run: chs-sw-all $(RVV_TEST_ELF)
 #	Clear old results
 	rm -rf $(RVV_TEST_RESULT_DIR_LANES)/*
 	mkdir -p $(RVV_TEST_RESULT_DIR_LANES)
 	mkdir -p $(VSIM_ROOT)
-#	TODO: add switch to stop on first failure
-	BINARY=$(RVV_TEST_ELF) 				\
+	BINARY=$(RVV_TEST_ELF) 					\
+	MMU_STUB=$(MMU_STUB) 					\
 		VSIM_ROOT=$(VSIM_ROOT) 				\
 		$(MAKE) chs-sim-clean chs-sim-run 
 	RVV_TEST_NAME=$(RVV_TEST_NAME) $(MAKE) rvv-test-report
@@ -55,17 +62,17 @@ TEST_COMMENT ?= "None"
 REPORT_FILE_ALL ?= $(CHS_RVV_TEST_RESULT_DIR)/report_all.txt
 rvv-test-report: $(RVV_TEST_TRACE) 
 #	Compose test report
-	printf "$(RVV_TEST_NAME)," 					>> $(RVV_TEST_RESULT_FILE)
-	printf " ARA_NR_LANES=$(ARA_NR_LANES)," 	>> $(RVV_TEST_RESULT_FILE)
-	grep --quiet $(RVV_TEST_MAGIC) $(RVV_TEST_TRACE) 	\
+	@printf "$(RVV_TEST_NAME)," 					>> $(RVV_TEST_RESULT_FILE)
+	@printf " ARA_NR_LANES=$(ARA_NR_LANES)," 	>> $(RVV_TEST_RESULT_FILE)
+	@grep --quiet $(RVV_TEST_MAGIC) $(RVV_TEST_TRACE) 	\
 		&& printf " PASSED," 					>> $(RVV_TEST_RESULT_FILE) \
 		|| printf " FAILED," 					>> $(RVV_TEST_RESULT_FILE)
-	printf " $(shell date $(DATE_FORMAT))," 	>> $(RVV_TEST_RESULT_FILE)
-	printf " Notes: \"$(TEST_COMMENT)\", " 		>> $(RVV_TEST_RESULT_FILE)
-	printf " VSIM_ROOT=$(VSIM_ROOT)" 			>> $(RVV_TEST_RESULT_FILE)
-	printf "\n"									>> $(RVV_TEST_RESULT_FILE)
+	@printf " $(shell date $(DATE_FORMAT))," 	>> $(RVV_TEST_RESULT_FILE)
+	@printf " Notes: \"$(TEST_COMMENT)\", " 		>> $(RVV_TEST_RESULT_FILE)
+	@printf " VSIM_ROOT=$(VSIM_ROOT)" 			>> $(RVV_TEST_RESULT_FILE)
+	@printf "\n"									>> $(RVV_TEST_RESULT_FILE)
 # 	Dump to general result report and terminal
-	tail -n1 $(RVV_TEST_RESULT_FILE) >> $(REPORT_FILE_ALL)
+	@tail -n1 $(RVV_TEST_RESULT_FILE) >> $(REPORT_FILE_ALL)
 	@printf "[INFO] Test report: "; tail -n1 $(RVV_TEST_RESULT_FILE)
 	@echo "[INFO] Check trace log at : $(RVV_TEST_TRACE)"
 	@echo "[INFO] Check transcript at: $(RVV_TEST_RESULT_DIR)/transcript"