diff --git a/src/architecture/generic.rs b/src/architecture/generic.rs
index 0f68247..e55fac5 100644
--- a/src/architecture/generic.rs
+++ b/src/architecture/generic.rs
@@ -5,7 +5,7 @@ use std::{hash, path::PathBuf};
 use super::riscv::MMUMode as RiscVMMUMode;
 
 /// Enumerates types of memory regions.
-#[derive(Serialize, Deserialize, Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Ord, PartialOrd, Hash, Default)]
 pub enum MemoryRegionType {
     #[default]
     RAM,
@@ -13,7 +13,7 @@ pub enum MemoryRegionType {
 }
 
 /// Represents a memory region with a start and end address.
-#[derive(Serialize, Deserialize, Debug, Clone, Copy, PartialEq, Eq, Hash, Default)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Ord, PartialOrd, Hash, Default)]
 pub struct MemoryRegion {
     pub region_type: MemoryRegionType,
     pub start_address: u64,
@@ -65,7 +65,7 @@ impl MemoryRegion {
 }
 
 /// Represents a memory space with regions.
-#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Hash, Default)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Ord, PartialOrd, Hash, Default)]
 pub struct MemorySpace {
     pub regions: Vec<MemoryRegion>,
 }
@@ -93,7 +93,7 @@ impl MemorySpace {
 /// Represents a CPU register with a value.
 /// Depending on the architecture, the *validity* changes.
 pub trait CPURegister {
-    type Value: hash::Hash + Eq + Copy + Default;
+    type Value: hash::Hash + Eq + Default;
 
     fn is_valid(&self) -> Result<Self::Value>;
 }
@@ -103,8 +103,8 @@ pub trait CPURegister {
 /// There is also auxiliary information about the page such as a present bit, a dirty or modified bit,
 /// address space or process ID information, amongst others.
 pub trait PageTableEntry {
-    type Address: hash::Hash + Eq + Copy + Default;
-    type Flags: hash::Hash + Eq + Copy + Default;
+    type Address: hash::Hash + Eq + Default;
+    type Flags: hash::Hash + Eq + Default;
 
     fn is_dirty(&self) -> bool;
     fn is_accessed(&self) -> bool;
@@ -119,14 +119,14 @@ pub trait PageTableEntry {
 /// It is used to translate virtual addresses to physical addresses and to manage the memory permissions of the pages.
 /// It is also used to store additional information about the pages, such as the status of the page, the address space or process ID, amongst others.
 pub trait PageTable {
-    type Entries: hash::Hash + Eq + Copy + Default + PageTableEntry;
+    type Entries: hash::Hash + Eq + Default + PageTableEntry;
 
     // fn apply_on_entries(function: FnMut(PageTableEntry) -> Vec<?> ) -> ? // FIXME: to be defined, but is it necessary?
 }
 
 /// Enumerates types of supported machines.
 /// This enum is used to specify the type of machine that is being parsed.
-#[derive(Serialize, Deserialize, Debug, Clone, Copy, PartialEq, Eq, Hash)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Ord, PartialOrd, Hash)]
 pub enum MachineType {
     RiscV(RiscVMMUMode),
 }
@@ -139,7 +139,7 @@ impl Default for MachineType {
 
 /// Represents a machine with a type, MMU, CPU, memory regions, and an associated dump file.
 /// It is used to store the machine's configuration, memory regions, and the dump file that is being used.
-#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Hash, Default)]
+#[derive(Serialize, Deserialize, Debug, Clone, PartialEq, Eq, Ord, PartialOrd, Hash, Default)]
 pub struct Machine {
     /// Type of the machine and its associated MMU mode.
     pub machine_type: MachineType,
diff --git a/src/architecture/riscv.rs b/src/architecture/riscv.rs
index 43d0543..74444c1 100644
--- a/src/architecture/riscv.rs
+++ b/src/architecture/riscv.rs
@@ -4,7 +4,7 @@ use anyhow::Result;
 use serde::{Deserialize, Serialize};
 
 /// Represents a RISC-V CPU register associated with a value.
-#[derive(Debug, Clone, Copy, Serialize, Deserialize, Default, Hash, Eq, PartialEq)]
+#[derive(Debug, Clone, Serialize, Deserialize, Default, Hash, Eq, PartialEq, Ord, PartialOrd)]
 pub struct CPURegister {
     pub value: u64,
 }
@@ -27,7 +27,7 @@ impl CPURegister {
 /// It holds the mapping between a virtual address of a page and the address of a physical frame.
 /// There is also auxiliary information about the page such as a present bit, a dirty or modified bit,
 /// address space or process ID information, amongst others.
-#[derive(Debug, Clone, Copy, Serialize, Deserialize, Hash, Eq, PartialEq)]
+#[derive(Debug, Clone, Serialize, Deserialize, Hash, Eq, PartialEq, Ord, PartialOrd)]
 pub struct PageTableEntry {
     pub address: u64,
     pub flags: u64,
@@ -76,7 +76,7 @@ impl PageTableEntryTrait for PageTableEntry {
 /// Enumerates RISC-V MMU modes.
 /// The MMU modes are used to determine the number of bits used for virtual and physical addresses.
 /// The modes are named after the number of bits used for the virtual address space.
-#[derive(Debug, Clone, Copy, Serialize, Deserialize, Hash, Eq, PartialEq, Default)]
+#[derive(Debug, Clone, Serialize, Deserialize, Hash, Eq, PartialEq, Ord, PartialOrd, Default)]
 pub enum MMUMode {
     #[default]
     SV32,
@@ -85,7 +85,7 @@ pub enum MMUMode {
 }
 
 /// Represents a RISC-V CPU.
-#[derive(Debug, Clone, Serialize, Deserialize, Default, Hash, Eq, PartialEq)]
+#[derive(Debug, Clone, Serialize, Deserialize, Default, Hash, Eq, PartialEq, Ord, PartialOrd)]
 pub struct CPU {
     pub registers: Vec<CPURegister>,
 }
@@ -99,7 +99,7 @@ impl CPU {
 }
 
 /// Represents a RISC-V MMU.
-#[derive(Debug, Clone, Serialize, Deserialize, Default, Hash, Eq, PartialEq)]
+#[derive(Debug, Clone, Serialize, Deserialize, Default, Hash, Eq, PartialEq, Ord, PartialOrd)]
 pub struct MMU {
     pub mode: MMUMode,
 }