diff --git a/Arcade-DonkeyKong.sv b/Arcade-DonkeyKong.sv
index 9af4bb6..ede191e 100644
--- a/Arcade-DonkeyKong.sv
+++ b/Arcade-DonkeyKong.sv
@@ -194,6 +194,13 @@ wire [1:0] ar = status[20:19];
 assign VIDEO_ARX = (!ar) ? ((status[2]|mod_pestplace)  ? 8'd8 : 8'd7) : (ar - 1'd1);
 assign VIDEO_ARY = (!ar) ? ((status[2]|mod_pestplace)  ? 8'd7 : 8'd8) : 12'd0;
 
+// Status Bit Map:
+//             Upper                             Lower
+// 0         1         2         3          4         5         6
+// 01234567890123456789012345678901 23456789012345678901234567890123
+// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
+// XXXXXX X           XXXXXXXXXXXXX
+
 `include "build_id.v"
 localparam CONF_STR = {
 	"A.DKONG;;",
@@ -202,7 +209,8 @@ localparam CONF_STR = {
 	"O35,Scandoubler Fx,None,HQ2x,CRT 25%,CRT 50%,CRT 75%;",
 	"H1O7,Flip Screen,Off,On;",
 	"OOS,Analog Video H-Pos,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31;",
-        "OTV,Analog Video V-Pos,0,1,2,3,4,5,6,7;",
+	"OTV,Analog Video V-Pos,0,1,2,3,4,5,6,7;",
+	"O6,Sound Effects,Sampled,Emulated;",
 	"H2ON,Autosave Hiscores,Off,On;",
 	"P1,Pause options;",
 	"P1OL,Pause when OSD is open,On,Off;",
@@ -464,6 +472,7 @@ dkong_top dkong(
 	.O_PIX(clk_pix),
 
 	.flip_screen(status[7]),
+	.use_emulated_sfx(status[6]),
 	.H_OFFSET(status[28:24]),
 	.V_OFFSET(status[31:29]),
 
diff --git a/files.qip b/files.qip
index b4d29cd..76ada43 100644
--- a/files.qip
+++ b/files.qip
@@ -2,7 +2,7 @@ set_global_assignment -name VERILOG_FILE rtl/dkong_top.v
 set_global_assignment -name VERILOG_FILE rtl/dkong_dma.v
 set_global_assignment -name VHDL_FILE rtl/dpram.vhd
 set_global_assignment -name VERILOG_FILE rtl/i8035ip.v
-set_global_assignment -name VERILOG_FILE rtl/dkong_wav_sound.v
+set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkong_wav_sound.sv
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/dkong_soundboard.sv
 set_global_assignment -name VERILOG_FILE rtl/dkong_vram.v
 set_global_assignment -name VERILOG_FILE rtl/dkong_sound.v
diff --git a/releases/Arcade-DonkeyKong_20240122.rbf b/releases/Arcade-DonkeyKong_20240122.rbf
new file mode 100644
index 0000000..65f0a11
Binary files /dev/null and b/releases/Arcade-DonkeyKong_20240122.rbf differ
diff --git a/rtl/dkong_soundboard.sv b/rtl/dkong_soundboard.sv
index 65fe314..4cd6fc9 100644
--- a/rtl/dkong_soundboard.sv
+++ b/rtl/dkong_soundboard.sv
@@ -3,6 +3,7 @@ module dkong_soundboard #(
 ) (
 	input         W_CLK_24576M,
 	input         W_RESETn,
+	input         use_emulated_sfx,
 	input         I_DKJR,   /// 1 = Emulate Donkey Kong JR, 3 or PestPlace (async not a problem)
 	input         W_W0_WE,
 	input         W_W1_WE,
@@ -36,14 +37,14 @@ wire    I8035_T1;
 wire    I8035_RSTn;
 
 // emulate 6 MHz crystal oscillor
-localparam increment_width = 17; // ceil(RATE_decimal_precision * 3.32192)
+localparam increment_width = 17; // increment_width = ceil(RATE_decimal_precision * 3.32192)
 reg [increment_width:0] count; // one longer for overflow bit.
-localparam X1_RATE = 6000000;
-localparam [increment_width:0] increment = (X1_RATE / W_CLK_24576M_RATE) * 2**increment_width;
+localparam int fraction_mutliplier = (1<<<increment_width);
+// This somehow refuses to work:
+localparam I8035_CLK_FRACTION = 6000000.0 / W_CLK_24576M_RATE;
 
 always @(posedge W_CLK_24576M) begin
-	count[increment_width] <= 1'b0; // keep overflow bit for just one cycle
-	count <= count + increment;
+	count <= {1'b0, count[increment_width - 1:0]} + (increment_width + 1)'(fraction_mutliplier * I8035_CLK_FRACTION);
 end
 assign I8035_CLK_EN = count[increment_width];
 
@@ -99,7 +100,7 @@ dkong_sound Digtal_sound
 //----    DAC  I/F     ------------------------
 
 localparam SAMPLE_RATE = 48000;
-localparam [8:0] clocks_per_sample = 24000000 / 48000;
+localparam [9:0] clocks_per_sample = 10'(W_CLK_24576M_RATE / SAMPLE_RATE);
 
 wire signed[15:0] W_D_S_DATB;
 
@@ -118,7 +119,7 @@ iir_2nd_order filter
 (
 	.clk(W_CLK_24576M),
 	.reset(~W_RESETn),
-	.div({3'd0, clocks_per_sample}),
+	.div(clocks_per_sample),
 	.A2(-18'sd26649),
 	.A3(18'sd11453),
 	.B1(18'sd215),
@@ -134,20 +135,20 @@ dkong_wav_sound #(
 ) Analog_sound (
 	.I_CLK(W_CLK_24576M),
 	.I_RSTn(W_RESETn),
-	.I_SW(I_DKJR ? 2'b00 : W_6H_Q[2:1]),
+	.I_SW(I_DKJR ? 3'b00 : {W_6H_Q[2:1],W_6H_Q[0] | use_emulated_sfx}),
 	.O_ROM_AB(WAV_ROM_A)
 );
 
-reg[8:0] audio_clk_counter;
+reg[9:0] audio_clk_counter;
 reg audio_clk_en;
 always@(posedge W_CLK_24576M, negedge W_RESETn) begin
 	if(!W_RESETn)begin
 		audio_clk_en <= 0;
 		audio_clk_counter <= 0;
 	end else begin
-		if(audio_clk_counter != (clocks_per_sample - 9'd1))begin
+		if(audio_clk_counter != (clocks_per_sample - 1'd1)) begin
 			audio_clk_en <= 0;
-			audio_clk_counter <= audio_clk_counter + 9'd1;
+			audio_clk_counter <= audio_clk_counter + 1'd1;
 		end else begin
 			audio_clk_en <= 1;
 			audio_clk_counter <= 0;
@@ -156,25 +157,30 @@ always@(posedge W_CLK_24576M, negedge W_RESETn) begin
 end
 
 wire signed[15:0] walk_out;
-dk_walk #(.CLOCK_RATE(W_CLK_24576M_RATE),.SAMPLE_RATE(SAMPLE_RATE)) walk (
+dk_walk #(
+	.CLOCK_RATE(W_CLK_24576M_RATE),
+	.SAMPLE_RATE(SAMPLE_RATE)
+) walk (
 	.clk(W_CLK_24576M),
 	.I_RSTn(W_RESETn),
 	.audio_clk_en(audio_clk_en),
-	.walk_en(~W_6H_Q[0]),
+	.walk_en(~W_6H_Q[0] & use_emulated_sfx),
 	.out(walk_out)
 );
 
 //  SOUND MIXER (WAV + DIG ) -----------------------
 
-wire signed[15:0] sound_mix =
-	(I_DKJR ? 16'd0 : {{3{~WAV_ROM_DO[7]}}, WAV_ROM_DO[6:0],6'b0}) +
-	{{3{W_D_S_DATC[15]}},W_D_S_DATC[14:2]} + {{5{W_D_S_DATC[15]}},W_D_S_DATC[14:4]} +
-	walk_out;
+wire signed[16:0] sound_mix =
+	(I_DKJR ? 17'd0 : {{4{~WAV_ROM_DO[7]}}, WAV_ROM_DO[6:0],6'b0}) +
+	{{4{W_D_S_DATC[15]}},W_D_S_DATC[14:2]} + {{6{W_D_S_DATC[15]}},W_D_S_DATC[14:4]} +
+	{{2{walk_out[15]}},walk_out[14:0]};
 
-always@(posedge W_CLK_24576M_RATE) begin
-	if (audio_clk_en) begin
-		O_SOUND_DAT <= sound_mix;
-	end
+
+always@(posedge W_CLK_24576M) begin
+	O_SOUND_DAT <=
+		sound_mix[16:15] == 2'b01 ? 16'h7FFF :
+		sound_mix[16:15] == 2'b10 ? 16'h8000 :
+		sound_mix[15:0];
 end
 
 endmodule
diff --git a/rtl/dkong_top.v b/rtl/dkong_top.v
index 8e7c39d..3eb9e90 100644
--- a/rtl/dkong_top.v
+++ b/rtl/dkong_top.v
@@ -20,13 +20,29 @@
 // 2005- 2- 9 Data on the ROM are initialized at the time of the start.
 //            added device.
 //            changed module I/O.
+//
+// This description is largely based on the TKG4 schematics, with some extensions
+// to support Radarscope and Donkey Kong Jr (although MiSter currently has a separate DKJR core).
+//
+// In the schematics, ICs are denoted by their position on the board, i.e. IC 6M
+// is the IC in column 6, row M. Unfortunataly, this makes reverse lookup from
+// Verilog to schematic hard, but at least ICs with similar coordinates are often cloase
+// together in the schematic too.
+// In the Verilog description, signals were orignally named by the source IC and pin
+// name. Later changes did not always follow this convention.
+// This naming can be confusing, because is not always unique:
+// e.g. IC 4H occurs both on the VIDEO and CPU board.
+//
+// Contrary to Radarscope and TGK2, the TKG4 does not really have a sound board,
+// so even in that code, numbering and naming of the TKG4 CPU board is largely
+// followed.
+//
 //================================================================================
 
 module dkong_top
 (
 	//    FPGA_USE
 	input  I_CLK_24576M,
-	input  I_CLK_24M,
 	input  I_RESETn,
 	output O_PIX,
 
@@ -43,6 +59,7 @@ module dkong_top
 
 	//    VGA (VIDEO) IF
 	input flip_screen,
+	input use_emulated_sfx,
 	input [8:0] H_OFFSET,
 	input [8:0] V_OFFSET,
 
@@ -112,7 +129,7 @@ wire   W_SW2_OEn ;
 wire   W_SW3_OEn ;
 wire   W_DIP_OEn ;
 
-wire   [2:0]W_4H_Q;
+wire   [1:0]W_4H_Q;
 wire   [7:0]W_5H_Q;
 wire   [7:0]W_6H_Q;
 wire   [4:0]W_3D_Q;
@@ -568,6 +585,7 @@ dkong_col_pal cpal
 dkong_soundboard dkong_soundboard(
 	.W_CLK_24576M(W_CLK_24576M & ~paused),
 	.W_RESETn(W_RESETn),
+	.use_emulated_sfx(use_emulated_sfx),
 	.I_DKJR(I_DKJR),
 	.O_SOUND_DAT(O_SOUND_DAT),
 	.O_SACK(W_SACK),
diff --git a/rtl/dkong_wav_sound.v b/rtl/dkong_wav_sound.sv
similarity index 90%
rename from rtl/dkong_wav_sound.v
rename to rtl/dkong_wav_sound.sv
index aacd5ba..f1b53f4 100644
--- a/rtl/dkong_wav_sound.v
+++ b/rtl/dkong_wav_sound.sv
@@ -1,135 +1,139 @@
-//===============================================================================
-// FPGA DONKEY KONG WAVE SOUND
-//
-// Version : 4.00
-//
-// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
-//
-// Important !
-//
-// This program is freeware for non-commercial use.
-// An author does no guarantee about this program.
-// You can use this under your own risk.
-//
-// 2004- 9 -7  Added Gorilla roar sound. K.degawa
-// 2005- 2 -9  removed Gorilla roar sound. K.degawa
-//             It was optimized to become the smallest.
-//================================================================================
-
-
-module dkong_wav_sound #(
-  parameter CLOCK_RATE = 24000000
-)(
-  input I_CLK,
-  input I_RSTn,
-  input [2:1]I_SW,
-
-  output [18:0] O_ROM_AB
-);
-
-localparam WAV_SAMPLE_RATE = 11025; // Hz
-localparam Sample_cnt = CLOCK_RATE / WAV_SAMPLE_RATE;
-
-localparam Wlk1_adr = 16'h0000; // 10000 - 107FF
-localparam Wlk1_cnt = 16'h07d0; // 10000 - 107CF
-localparam Wlk2_adr = 16'h0800; // 10800 - 10FFF
-localparam Wlk2_cnt = 16'h07d0; // 10800 - 10FCF
-localparam Jump_adr = 16'h1000; // 11000 - 12FFF
-localparam Jump_cnt = 16'h1e20; // 11000 - 12E1F
-localparam Foot_adr = 16'h3000; // 13000 - 14FFF
-localparam Foot_cnt = 16'h1750; // 13000 - 1474F
-localparam Wlk3_adr = 16'h4800; // 14800 - 14FFF
-localparam Wlk3_cnt = 16'h07d0; // 14800 - 14FCF
-// Contrary to comment in header, the Gorilla roar sound is still in the mra file:
-// parameter Roar_adr = 16'h5000; // 15000 - 198FF
-// parameter Roar_cnt = 16'h4900; // 15000 - 198FF
-// However, it is not used, and seems to be too loud.
-// It seemd that either the original board produced the roar by the digital
-// synthesizer, or was this was moved there for the emulator.
-
-reg   [11:0]sample;
-reg   sample_pls;
-
-always@(posedge I_CLK or negedge I_RSTn)
-begin
-  if(! I_RSTn)begin
-    sample <= 0;
-    sample_pls <= 0;
-  end else begin
-    sample <= (sample == Sample_cnt - 1'b1) ? 12'b0 : sample+1'b1;
-    sample_pls <= (sample == Sample_cnt - 1'b1)? 1'b1 : 1'b0 ;
-  end
-end
-
-//-----------  WALK SOUND ------------------------------------------
-reg    [2:0]status0;
-reg    [2:0]status1;
-reg    [15:0]ad_cnt;
-reg    [15:0]end_cnt;
-reg    [1:0]steps_cnt;
-reg    old_foot_rq;
-reg    old_jump_rq;
-wire   foot_rq = I_SW[2];
-wire   jump_rq = I_SW[1];
-
-always@(posedge I_CLK or negedge I_RSTn)
-begin
-  if(! I_RSTn)begin
-    status0 <= 0;
-    status1 <= 0;
-    end_cnt <= Foot_cnt;
-    ad_cnt  <= 0;
-    steps_cnt <= 2'b01;
-  end else begin
-    status0[0] = ~old_foot_rq & foot_rq;
-    old_foot_rq = foot_rq;
-    status0[2] <= ~old_jump_rq & jump_rq;
-    old_jump_rq = jump_rq;
-    if(status0 > status1)begin
-      if(status0[2])begin
-        status1 <= 3'b111;
-        ad_cnt <= Jump_adr;
-        end_cnt <= Jump_cnt;
-        steps_cnt <= 2'b01;
-      end else if(status0[1])begin
-        status1 <= 3'b011;
-        case (steps_cnt)
-            2'b01: begin
-                ad_cnt <= Wlk1_adr;
-                end_cnt <= Wlk1_cnt;
-                steps_cnt <= 2'b10;
-                end
-            2'b10: begin
-                ad_cnt <= Wlk2_adr;
-                end_cnt <= Wlk2_cnt;
-                steps_cnt <= 2'b11;
-                end
-            2'b11: begin
-                ad_cnt <= Wlk3_adr;
-                end_cnt <= Wlk3_cnt;
-                steps_cnt <= 2'b01;
-                end
-        endcase
-      end else begin
-        status1 <= 3'b001;
-        ad_cnt <= Foot_adr;
-        end_cnt <= Foot_cnt;
-        steps_cnt <= 2'b01;
-      end
-    end else begin
-      if(sample_pls)begin
-        if(!end_cnt)begin
-          status1 <= 3'b000;
-        end else begin
-          end_cnt <= end_cnt-1;
-          ad_cnt <= ad_cnt+1;
-        end
-      end
-    end
-  end
-end
-
-assign O_ROM_AB  = {3'b001,ad_cnt};
-
-
-endmodule
+//===============================================================================
+// FPGA DONKEY KONG WAVE SOUND
+//
+// Version : 4.00
+//
+// Copyright(c) 2003 - 2004 Katsumi Degawa , All rights reserved
+//
+// Important !
+//
+// This program is freeware for non-commercial use.
+// An author does no guarantee about this program.
+// You can use this under your own risk.
+//
+// 2004- 9 -7  Added Gorilla roar sound. K.degawa
+// 2005- 2 -9  removed Gorilla roar sound. K.degawa
+//             It was optimized to become the smallest.
+//================================================================================
+
+
+module dkong_wav_sound #(
+  parameter CLOCK_RATE = 24000000
+)(
+  input I_CLK,
+  input I_RSTn,
+  input [2:0]I_SW,
+
+  output [18:0] O_ROM_AB
+);
+
+localparam WAV_SAMPLE_RATE = 11025; // Hz
+localparam [11:0] Sample_cnt = 12'(CLOCK_RATE / WAV_SAMPLE_RATE);
+
+localparam Wlk1_adr = 16'h0000; // 10000 - 107FF
+localparam Wlk1_cnt = 16'h07d0; // 10000 - 107CF
+localparam Wlk2_adr = 16'h0800; // 10800 - 10FFF
+localparam Wlk2_cnt = 16'h07d0; // 10800 - 10FCF
+localparam Jump_adr = 16'h1000; // 11000 - 12FFF
+localparam Jump_cnt = 16'h1e20; // 11000 - 12E1F
+localparam Foot_adr = 16'h3000; // 13000 - 14FFF
+localparam Foot_cnt = 16'h1750; // 13000 - 1474F
+localparam Wlk3_adr = 16'h4800; // 14800 - 14FFF
+localparam Wlk3_cnt = 16'h07d0; // 14800 - 14FCF
+// Contrary to comment in header, the Gorilla roar sound is still in the mra file:
+// localparam Roar_adr = 16'h5000; // 15000 - 198FF
+// localparam Roar_cnt = 16'h4900; // 15000 - 198FF
+// However, it is not used, and seems to be too loud.
+// It seemd that either the original board produced the roar by the digital
+// synthesizer, or was this was moved there for the emulator.
+
+reg   [11:0]sample;
+reg   sample_pls;
+
+always@(posedge I_CLK or negedge I_RSTn)
+begin
+  if(! I_RSTn)begin
+    sample <= 0;
+    sample_pls <= 0;
+  end else begin
+    sample <= (sample == Sample_cnt - 1'b1) ? 12'b0 : sample+1'b1;
+    sample_pls <= (sample == Sample_cnt - 1'b1)? 1'b1 : 1'b0 ;
+  end
+end
+
+//-----------  WALK SOUND ------------------------------------------
+reg    [2:0]status0;
+reg    [2:0]status1;
+reg    [15:0]ad_cnt;
+reg    [15:0]end_cnt;
+reg    [1:0]steps_cnt;
+reg    old_foot_rq;
+reg    old_jump_rq;
+reg    old_step_rq;
+wire   foot_rq = I_SW[2];
+wire   jump_rq = I_SW[1];
+wire   step_rq = I_SW[0];
+
+always@(posedge I_CLK or negedge I_RSTn)
+begin
+  if(! I_RSTn)begin
+    status0 <= 0;
+    status1 <= 0;
+    end_cnt <= Foot_cnt;
+    ad_cnt  <= 0;
+    steps_cnt <= 2'b01;
+  end else begin
+    status0[0] = ~old_foot_rq & foot_rq;
+    old_foot_rq = foot_rq;
+	 status0[1] = ~old_step_rq & step_rq;
+	 old_step_rq = step_rq;
+    status0[2] <= ~old_jump_rq & jump_rq;
+    old_jump_rq = jump_rq;
+    if(status0 > status1)begin
+      if(status0[2])begin
+        status1 <= 3'b111;
+        ad_cnt <= Jump_adr;
+        end_cnt <= Jump_cnt;
+        steps_cnt <= 2'b01;
+      end else if(status0[1])begin
+        status1 <= 3'b011;
+        case (steps_cnt)
+            2'b01: begin
+                ad_cnt <= Wlk1_adr;
+                end_cnt <= Wlk1_cnt;
+                steps_cnt <= 2'b10;
+                end
+            2'b10: begin
+                ad_cnt <= Wlk2_adr;
+                end_cnt <= Wlk2_cnt;
+                steps_cnt <= 2'b11;
+                end
+            2'b11: begin
+                ad_cnt <= Wlk3_adr;
+                end_cnt <= Wlk3_cnt;
+                steps_cnt <= 2'b01;
+                end
+        endcase
+      end else begin
+        status1 <= 3'b001;
+        ad_cnt <= Foot_adr;
+        end_cnt <= Foot_cnt;
+        steps_cnt <= 2'b01;
+      end
+    end else begin
+      if(sample_pls)begin
+        if(!end_cnt)begin
+          status1 <= 3'b000;
+        end else begin
+          end_cnt <= end_cnt-1'b1;
+          ad_cnt <= ad_cnt+1'b1;
+        end
+      end
+    end
+  end
+end
+
+assign O_ROM_AB  = {3'b001,ad_cnt};
+
+
+endmodule
diff --git a/rtl/mister-discrete/astable_555_vco.sv b/rtl/mister-discrete/astable_555_vco.sv
index 44cfb7f..4ab95e3 100644
--- a/rtl/mister-discrete/astable_555_vco.sv
+++ b/rtl/mister-discrete/astable_555_vco.sv
@@ -1,12 +1,12 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete invertor square wave oscilator test bench
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
  *
  *  Model taken from the equation on https://electronics.stackexchange.com/questions/101530/what-is-the-equation-for-the-555-timer-control-voltage
- *  
+ *
  *  th=C⋅(R1+R2)⋅ln(1+v_control/(2*(VCC−v_control)))
  *  tl=C⋅R2⋅ln(2)
  *
@@ -36,13 +36,13 @@
  *        |          |
  *        |          ^
  *       gnd       Reset
- * 
+ *
  *     Drawing based on a drawing from MAME discrete
  *
  ********************************************************************************/
 module astable_555_vco#(
     parameter CLOCK_RATE = 50000000,
-    parameter longint SAMPLE_RATE = 48000,
+    parameter SAMPLE_RATE = 48000,
     parameter R1 = 47000,
     parameter R2 = 27000,
     parameter C_35_SHIFTED = 1134 // 33 nanofarad
@@ -57,17 +57,17 @@ module astable_555_vco#(
     localparam ln2_16_SHIFTED = 45426;
     localparam[63:0] C_R2_ln2_27_SHIFTED = C_35_SHIFTED * R2 * ln2_16_SHIFTED >> 24;
     localparam[63:0] C_R1_R2_35_SHIFTED = C_35_SHIFTED * (R1 + R2);
-    localparam[31:0] CYCLES_LOW = C_R2_ln2_27_SHIFTED * CLOCK_RATE >> 27;
-    localparam[31:0] CLOCK_RATE_C_R1_R2 = C_R1_R2_35_SHIFTED * CLOCK_RATE >> 35;
+    localparam[31:0] CYCLES_LOW = 32'(C_R2_ln2_27_SHIFTED * CLOCK_RATE >> 27);
+    localparam[31:0] CLOCK_RATE_C_R1_R2 = 32'(C_R1_R2_35_SHIFTED * CLOCK_RATE >> 35);
 
     wire signed[15:0] v_control_safe;
 
     reg[15:0] v_control_divided_two_vcc_minus_vcontrol = 3000;
     reg[15:0] two_vcc_minus_vcontrol = 3000;
-    
+
     wire [11:0] ln_vc_vcc_vc_8_shifted;
-    reg[23:0] to_log_8_shifted = 1000;
-    
+    reg[23:0] to_log_8_shifted;
+
     natural_log natlog(
         .in_8_shifted(to_log_8_shifted),
         .I_RSTn(I_RSTn),
@@ -76,15 +76,15 @@ module astable_555_vco#(
     );
 
     reg[32:0] WAVE_LENGTH;
-    reg[31:0] CYCLES_HIGH = 1000;
+    reg[31:0] CYCLES_HIGH;
 
-    assign v_control_safe = v_control < 32767 ? v_control : 32766;
+    assign v_control_safe = v_control < 16'h7fff ? v_control : 16'h7ffe;
 
     assign WAVE_LENGTH = CYCLES_HIGH + CYCLES_LOW;
 
-    reg[63:0] wave_length_counter = 0;
+    reg[63:0] wave_length_counter;
 
-    reg signed[15:0] unfiltered_out = 0;
+    reg signed[15:0] unfiltered_out;
 
     rate_of_change_limiter #(
         .SAMPLE_RATE(SAMPLE_RATE),
@@ -105,18 +105,18 @@ module astable_555_vco#(
             CYCLES_HIGH <= 1000;
         end else begin
             v_control_divided_two_vcc_minus_vcontrol <= v_control_safe / (two_vcc_minus_vcontrol >> 8);
-            two_vcc_minus_vcontrol <= (VCC << 1) - (v_control_safe << 1);
-            to_log_8_shifted <= (1 << 8) + v_control_divided_two_vcc_minus_vcontrol;
+            two_vcc_minus_vcontrol <= 16'((VCC << 1) - (v_control_safe << 1));
+            to_log_8_shifted <= 24'((1 << 8) + v_control_divided_two_vcc_minus_vcontrol);
             CYCLES_HIGH <= ((CLOCK_RATE_C_R1_R2 >> 4) * ln_vc_vcc_vc_8_shifted) >> 4; // C⋅(R1+R2)⋅ln(1+v_control/(2*(VCC−v_control)))
 
             if(wave_length_counter < WAVE_LENGTH)begin
             wave_length_counter <= wave_length_counter + 1;
-            end else begin 
+            end else begin
                 wave_length_counter <= 0;
             end
 
             if(audio_clk_en)begin
-                unfiltered_out <= wave_length_counter < CYCLES_HIGH ? 16384 : 0;
+                unfiltered_out <= wave_length_counter < CYCLES_HIGH ? 16'd16384 : '0;
             end
         end
     end
diff --git a/rtl/mister-discrete/dk_walk.sv b/rtl/mister-discrete/dk_walk.sv
index c270d20..58d1a70 100644
--- a/rtl/mister-discrete/dk_walk.sv
+++ b/rtl/mister-discrete/dk_walk.sv
@@ -1,8 +1,8 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete example circuit - dk walk
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
  *
  ********************************************************************************/
@@ -22,7 +22,7 @@ module dk_walk #(
 
     wire signed[15:0] walk_en_5volts;
     wire signed[15:0] walk_en_5volts_filtered;
-    assign walk_en_5volts =  walk_en ? 0 : 'd6826; // 2^14 * 5/12 = 6826 , for 5 volts
+    assign walk_en_5volts =  walk_en ? '0 : 16'd6826; // 2^14 * 5/12 = 6826 , for 5 volts
 
     // filter to simulate transfer rate of invertors
     rate_of_change_limiter #(
@@ -36,7 +36,7 @@ module dk_walk #(
         .out(walk_en_5volts_filtered)
     );
 
-    assign mixer_input[0] = walk_en_5volts_filtered; 
+    assign mixer_input[0] = walk_en_5volts_filtered;
     assign mixer_input[1] = square_osc_out;
 
     localparam SAMPLE_RATE_SHIFT = 3;
@@ -110,8 +110,8 @@ module dk_walk #(
     );
 
     wire signed[15:0] walk_enveloped;
-    assign walk_enveloped = astable_555_out > 1000 ? walk_en_filtered : 0;
-    
+    assign walk_enveloped = astable_555_out > 1000 ? walk_en_filtered : 16'd0;
+
     wire signed[15:0] walk_enveloped_high_passed;
 
     resistor_capacitor_high_pass_filter #(
@@ -149,7 +149,7 @@ module dk_walk #(
             if(walk_enveloped_band_passed > 0) begin //TODO: hack to simulate diode connection coming from ground
                 out <= walk_enveloped_band_passed + (walk_enveloped_band_passed >>> 1);
             end else begin
-                out <= walk_enveloped_band_passed >>> 1 + (walk_enveloped_band_passed >>> 2);
+                out <= (walk_enveloped_band_passed >>> 1) + (walk_enveloped_band_passed >>> 2);
             end
         end
     end
diff --git a/rtl/mister-discrete/invertor_square_wave_oscilator.sv b/rtl/mister-discrete/invertor_square_wave_oscilator.sv
index c85fab8..1c2b5fa 100644
--- a/rtl/mister-discrete/invertor_square_wave_oscilator.sv
+++ b/rtl/mister-discrete/invertor_square_wave_oscilator.sv
@@ -1,19 +1,19 @@
 /*********************************************************************************\
- *  
+ *
  *  MiSTer Discrete invertor square wave oscilator
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
  *
  *
  *  Simplified model of the below circuit.
- *  This model does not take the  transfer functions of the invertors 
+ *  This model does not take the  transfer functions of the invertors
  *  into account:
- * 
+ *
  *  f = 1 / 2.2 R1C1
  *  This equation was found on:
  *  https://www.gadgetronicx.com/square-wave-generator-logic-gates/
- *  
+ *
  *  The equation didn't coincide with the circuit simulated version.
  *  It looks like the above formula is to obtain the SWITCHING feequency.
  *  The actualy frequency is twice lower.
@@ -26,7 +26,7 @@
  *     |  |/     |  |/     |
  *     Z         Z         |
  *     Z         Z R1     --- C
- *     Z         Z        --- 
+ *     Z         Z        ---
  *     |         |         |
  *     '---------+---------'
  *
@@ -72,12 +72,12 @@ module invertor_square_wave_oscilator#(
         end else begin
             if(wave_length_counter < WAVE_LENGTH)begin
                 wave_length_counter <= wave_length_counter + 1;
-            end else begin 
+            end else begin
                 wave_length_counter <= 0;
             end
 
             if (audio_clk_en) begin
-                unfiltered_out <=  wave_length_counter < HALF_WAVE_LENGTH ? 16384 : 0;
+                unfiltered_out <=  wave_length_counter < HALF_WAVE_LENGTH ? 16'd16384 : '0;
             end
         end
     end
diff --git a/rtl/mister-discrete/natural_log.sv b/rtl/mister-discrete/natural_log.sv
index 8ac3e89..cb1b7a5 100644
--- a/rtl/mister-discrete/natural_log.sv
+++ b/rtl/mister-discrete/natural_log.sv
@@ -1,13 +1,13 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete natural log core
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
  *
  ********************************************************************************/
 module natural_log(input clk, input[23:0] in_8_shifted, input I_RSTn, output reg[11:0] out_8_shifted);
-    
+
     localparam RATIO_16_SHIFTED = 45426; // 1 / log2(e)
 
     wire[11:0] log2_x;
@@ -23,7 +23,7 @@ module natural_log(input clk, input[23:0] in_8_shifted, input I_RSTn, output reg
         if(!I_RSTn)begin
             out_8_shifted <= 0;
         end else if(log2_x)begin
-            out_8_shifted <= RATIO_16_SHIFTED * log2_x >> 16; 
+            out_8_shifted <= 12'(RATIO_16_SHIFTED * log2_x >> 16);
         end
     end
 
diff --git a/rtl/mister-discrete/rate_of_change_limiter.sv b/rtl/mister-discrete/rate_of_change_limiter.sv
index 8255e3c..c317cf0 100644
--- a/rtl/mister-discrete/rate_of_change_limiter.sv
+++ b/rtl/mister-discrete/rate_of_change_limiter.sv
@@ -18,11 +18,11 @@ module rate_of_change_limiter #(
             out <= 0;
         end else if(audio_clk_en) begin
             if(difference < -MAX_CHANGE_PER_SAMPLE)begin
-                out <= out - MAX_CHANGE_PER_SAMPLE;
+                out <= out - 16'(MAX_CHANGE_PER_SAMPLE);
             end else if(difference > MAX_CHANGE_PER_SAMPLE) begin
-                out <= out + MAX_CHANGE_PER_SAMPLE;
+                out <= out + 16'(MAX_CHANGE_PER_SAMPLE);
             end else begin
-                out <= in; 
+                out <= in;
             end
         end
     end
diff --git a/rtl/mister-discrete/resistive_two_way_mixer.sv b/rtl/mister-discrete/resistive_two_way_mixer.sv
index b98341e..d6fa3b7 100644
--- a/rtl/mister-discrete/resistive_two_way_mixer.sv
+++ b/rtl/mister-discrete/resistive_two_way_mixer.sv
@@ -1,14 +1,14 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete resistive two way mixer
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
  *
  *   inputs[0]    inputs[1]
  *        V         V
- *        |         |       
- *        |         |       
+ *        |         |
+ *        |         |
  *        Z         Z
  *     R0 Z         Z R1
  *        Z         Z
@@ -18,27 +18,33 @@
  *             |
  *             V
  *            out
- *          
+ *
+ * This assumes that input 0 and 1 are driven by voltage outputs with
+ * low enough output inpedance, and out drives a voltage input with high enough
+ * input inpedance. (high and low enough compared to R0 and R1 at all
+ * relveant frequencies)
+ *
  ********************************************************************************/
 module resistive_two_way_mixer #(
     parameter longint R0 = 10000,
     parameter longint R1 = 10000
-) ( 
+) (
     input clk,
     input I_RSTn,
     input audio_clk_en,
     input[15:0] inputs[1:0],
     output reg[15:0] out = 0
 );
-    localparam integer R0_RATIO_16_SHIFTED = ((R1 <<< 16) / R0);
-    localparam integer R1_RATIO_16_SHIFTED = ((R0 <<< 16) / R1);
+    // r0:       65536, r1:       65536, norm:                 32768
+    localparam integer R0_RATIO_16_SHIFTED = 32'((R1 <<< 16) / R0);
+    localparam integer R1_RATIO_16_SHIFTED = 32'((R0 <<< 16) / R1);
     localparam longint NORMALIZATION_RATIO_16_SHIFTED = (1 <<< 32)/(R0_RATIO_16_SHIFTED+R1_RATIO_16_SHIFTED);
-    
+
     always@(posedge clk, negedge I_RSTn) begin
         if(!I_RSTn)begin
             out <= 0;
         end else if(audio_clk_en)begin
-            out <= (R0_RATIO_16_SHIFTED * inputs[0] + R1_RATIO_16_SHIFTED * inputs[1]) * NORMALIZATION_RATIO_16_SHIFTED >>> 32;
+            out <= 16'((R0_RATIO_16_SHIFTED * inputs[0] + R1_RATIO_16_SHIFTED * inputs[1]) * NORMALIZATION_RATIO_16_SHIFTED >>> 32);
         end
     end
 endmodule
\ No newline at end of file
diff --git a/rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv b/rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv
index e7639d4..a6e3d91 100644
--- a/rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv
+++ b/rtl/mister-discrete/resistor_capacitor_high_pass_filter.sv
@@ -1,18 +1,18 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete resistor_capacitor_low_pass filter
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
- *         
+ *
  *  based on https://en.wikipedia.org/wiki/Low-pass_filter
- * 
+ *
  ********************************************************************************/
 module resistor_capacitor_high_pass_filter #(
     parameter SAMPLE_RATE = 48000,
     parameter R = 47000,
-    parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35 
-) ( 
+    parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35
+) (
     input clk,
     input I_RSTn,
     input audio_clk_en,
@@ -22,7 +22,7 @@ module resistor_capacitor_high_pass_filter #(
     localparam longint DELTA_T_32_SHIFTED = (1 <<< 32) / SAMPLE_RATE;
     localparam longint R_C_32_SHIFTED = R * C_35_SHIFTED >>> 3;
     localparam longint SMOOTHING_FACTOR_ALPHA_16_SHIFTED = (R_C_32_SHIFTED <<< 16) / (R_C_32_SHIFTED + DELTA_T_32_SHIFTED);
-    
+
     wire[7:0] random_number;
 
     LFSR lfsr(
@@ -38,9 +38,9 @@ module resistor_capacitor_high_pass_filter #(
             out <= 0;
             last_in <= 0;
         end else if(audio_clk_en)begin
-            out <= SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (out + in - last_in) >> 16;
-            last_in <= in + ((random_number >>> 6) - 2); // add noise to help convergence to 0
+            out <= 16'(SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (out + in - last_in) >> 16);
+            last_in <= 16'(in + ((random_number >>> 6) - 2)); // add noise to help convergence to 0
         end
     end
-    
+
 endmodule
\ No newline at end of file
diff --git a/rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv b/rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv
index df74e1b..ef6db80 100644
--- a/rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv
+++ b/rtl/mister-discrete/resistor_capacitor_low_pass_filter.sv
@@ -1,19 +1,19 @@
 /********************************************************************************\
- * 
+ *
  *  MiSTer Discrete resistor_capacitor_low_pass filter
  *
- *  Copyright 2022 by Jegor van Opdorp. 
+ *  Copyright 2022 by Jegor van Opdorp.
  *  This program is free software under the terms of the GPLv3, see LICENCSE.txt
- *         
+ *
  *  based on https://en.wikipedia.org/wiki/Low-pass_filter
  *  and https://zipcpu.com/dsp/2017/08/19/simple-filter.html
- * 
+ *
  ********************************************************************************/
 module resistor_capacitor_low_pass_filter #(
     parameter SAMPLE_RATE = 48000,
     parameter R = 47000,
-    parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35 
-) ( 
+    parameter C_35_SHIFTED = 1615 // 0.000000047 farads <<< 35
+) (
     input clk,
     input I_RSTn,
     input audio_clk_en,
@@ -28,8 +28,8 @@ module resistor_capacitor_low_pass_filter #(
         if(!I_RSTn)begin
             out <= 0;
         end else if(audio_clk_en)begin
-            out <= out + (SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (in - out) >>> 16);
+            out <= out + 16'(SMOOTHING_FACTOR_ALPHA_16_SHIFTED * (in - out) >>> 16);
         end
     end
-    
+
 endmodule
\ No newline at end of file