From a105e5627823f26bc08603101a3cd5d152c42777 Mon Sep 17 00:00:00 2001 From: Yuta Date: Sun, 14 Jan 2024 18:43:01 +0900 Subject: [PATCH] supports Vivado2023.2 and latest open-nic shell/driver --- RELEASE_NOTES | 18 +-- hw/lib/common/constraints/au200_general.xdc | 9 ++ .../constraints/au200_vcu1525_timing.tcl | 1 + hw/lib/common/constraints/au250_general.xdc | 26 ++-- hw/lib/common/constraints/au250_timing.tcl | 1 + hw/lib/common/constraints/au280_general.xdc | 10 +- hw/lib/common/constraints/au280_timing.tcl | 1 + hw/lib/common/constraints/vcu1525_general.xdc | 8 ++ hw/lib/common/hdl/nf_attachment.sv | 2 +- hw/lib/common/hdl/top.v | 72 ++++++++++- hw/lib/common/hdl/top_wrapper.sv | 66 ++++++++++ hw/lib/xilinx/cam_v1_1_0/cam.tcl | 3 +- hw/lib/xilinx/tcam_v1_1_0/tcam.tcl | 1 + .../xilinx_shell_v1_0_0/hdl/open_nic_shell.sv | 78 +++++++++-- .../xilinx_shell_v1_0_0/xilinx_shell.tcl | 54 +++++++- .../reference_nic/hw/tcl/reference_nic.tcl | 90 ++++++++++++- .../hw/tcl/reference_router.tcl | 90 ++++++++++++- .../hw/tcl/reference_switch.tcl | 90 ++++++++++++- .../hw/tcl/reference_switch_lite.tcl | 90 ++++++++++++- sw/driver/opennic-driver.patch | 122 +++++++++++------- tools/settings.sh | 3 +- 21 files changed, 723 insertions(+), 112 deletions(-) diff --git a/RELEASE_NOTES b/RELEASE_NOTES index 65f2fe9..4d051c9 100644 --- a/RELEASE_NOTES +++ b/RELEASE_NOTES @@ -26,22 +26,12 @@ # # @NETFPGA_LICENSE_HEADER_END@ # -GIT VERSION 1.0.0 +GIT VERSION 1.1.0 This release contains: 1. Designs - - reference design for L2 switch, router, nic on Alveo series FPGA cards - (e.g., U200, U250, U280) and VCU1525 - - Linux driver (open-nic-driver), hardware testing and simulation enviroments are included. - - library cores to build reference_switch, reference_switch_lite, reference_router, - reference_nic and simulation and hardware testings + - support Vivado 2023.2 + - support OpenNIC Shell open-nic-shell (commit: 8077751) + - support OpenNIC Driver open-nic-driver (commit: cbac3b9) -2. Notes - - For U280 board, please use 320MHz for reference_switch_lite project to fix timing closure, - and use 300MHz for reference_router project to fix timing closure - To change the running freq., please refer to each tcl file. - e.g., NetFPGA-PLUS/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl - - scone is not fully tested. -3. Wiki - - Please refer to our wiki: https://github.com/NetFPGA/NetFPGA-PLUS/wiki diff --git a/hw/lib/common/constraints/au200_general.xdc b/hw/lib/common/constraints/au200_general.xdc index 20851bb..bc3dde0 100644 --- a/hw/lib/common/constraints/au200_general.xdc +++ b/hw/lib/common/constraints/au200_general.xdc @@ -136,6 +136,15 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]] set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]] set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]] set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]] + + +# Satellite Core +set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd] +set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12} [get_ports satellite_uart_0_rxd] +set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[0]] +set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[1]] +set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[2]] +set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[3]] ########################################################################## # Timing ########################################################################## diff --git a/hw/lib/common/constraints/au200_vcu1525_timing.tcl b/hw/lib/common/constraints/au200_vcu1525_timing.tcl index 7926c1d..b6edb7a 100644 --- a/hw/lib/common/constraints/au200_vcu1525_timing.tcl +++ b/hw/lib/common/constraints/au200_vcu1525_timing.tcl @@ -15,6 +15,7 @@ # limitations under the License. # # ************************************************************************* +create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk] set_false_path -through [get_ports pci_rst_n] set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] diff --git a/hw/lib/common/constraints/au250_general.xdc b/hw/lib/common/constraints/au250_general.xdc index d1a71d6..0c1cc88 100644 --- a/hw/lib/common/constraints/au250_general.xdc +++ b/hw/lib/common/constraints/au250_general.xdc @@ -135,21 +135,31 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]] set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]] set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]] set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]] + +# Satellite Core +set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd] +set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12} [get_ports satellite_uart_0_rxd] +set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[0]] +set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[1]] +set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[2]] +set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[3]] ########################################################################## # Timing ########################################################################## -# CMAC user clock -create_clock -period 3.103 -name cmac_clk_0 [get_pins -hier -filter name=~*cmac_port[0]*cmac_gtwiz_userclk_tx_inst/txoutclk_out[0]] -create_clock -period 3.103 -name cmac_clk_1 [get_pins -hier -filter name=~*cmac_port[1]*cmac_gtwiz_userclk_tx_inst/txoutclk_out[0]] +# axis_aclk needs to be specified +create_clock -period 4.000 -name axis_aclk [get_pins -hier -filter name=~*u_top_wrapper/xilinx_nic_shell/axis_aclk] -# Datapath Clock - 340MHz +# Datapath Clock - 340MHz (called core_clk internally apparently) create_clock -period 2.941 -name dp_clk [get_pins -hier -filter name=~*u_clk_wiz_1/clk_out1] +# PCIe clock 100MHz +create_clock -period 10.000 -name pcie_refclk [get_ports pci_clk_p] + set_false_path -from [get_clocks axis_aclk] -to [get_clocks dp_clk] set_false_path -from [get_clocks dp_clk] -to [get_clocks axis_aclk] -set_false_path -from [get_clocks cmac_clk_1] -to [get_clocks dp_clk] -set_false_path -from [get_clocks dp_clk] -to [get_clocks cmac_clk_1] -set_false_path -from [get_clocks cmac_clk_0] -to [get_clocks dp_clk] -set_false_path -from [get_clocks dp_clk] -to [get_clocks cmac_clk_0] +set_false_path -from [get_clocks dp_clk] -to [get_clocks {txoutclk_out[0]}] +set_false_path -from [get_clocks {txoutclk_out[0]}] -to [get_clocks dp_clk] +set_false_path -from [get_clocks dp_clk] -to [get_clocks {txoutclk_out[0]_1}] +set_false_path -from [get_clocks {txoutclk_out[0]_1}] -to [get_clocks dp_clk] set_false_path -from [get_clocks clk_out1_qdma_subsystem_clk_div] -to [get_clocks axis_aclk] set_false_path -from [get_clocks dp_clk] -to [get_clocks clk_out1_qdma_subsystem_clk_div] diff --git a/hw/lib/common/constraints/au250_timing.tcl b/hw/lib/common/constraints/au250_timing.tcl index eadf009..994be34 100644 --- a/hw/lib/common/constraints/au250_timing.tcl +++ b/hw/lib/common/constraints/au250_timing.tcl @@ -15,6 +15,7 @@ # limitations under the License. # # ************************************************************************* +# QDMA clock set_false_path -through [get_ports pci_rst_n] set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] diff --git a/hw/lib/common/constraints/au280_general.xdc b/hw/lib/common/constraints/au280_general.xdc index 370dd54..c0e4786 100644 --- a/hw/lib/common/constraints/au280_general.xdc +++ b/hw/lib/common/constraints/au280_general.xdc @@ -67,8 +67,14 @@ set_property PACKAGE_PIN H30 [get_ports QSFP1_RESET] set_property IOSTANDARD LVCMOS18 [get_ports QSFP1_RESET] # HBM -set_property PACKAGE_PIN D32 [get_ports STAT_CATTRIP] -set_property IOSTANDARD LVCMOS18 [get_ports STAT_CATTRIP] +set_property -dict {PACKAGE_PIN D32 IOSTANDARD LVCMOS18 PULLDOWN TRUE} [get_ports hbm_cattrip] + +set_property -dict {PACKAGE_PIN D29 IOSTANDARD LVCMOS18} [get_ports satellite_uart_0_txd] +set_property -dict {PACKAGE_PIN E28 IOSTANDARD LVCMOS18} [get_ports satellite_uart_0_rxd] +set_property -dict {PACKAGE_PIN K28 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[0]] +set_property -dict {PACKAGE_PIN J29 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[1]] +set_property -dict {PACKAGE_PIN K29 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[2]] +set_property -dict {PACKAGE_PIN J31 IOSTANDARD LVCMOS18} [get_ports satellite_gpio[3]] ########################################################################## # Timing ########################################################################## diff --git a/hw/lib/common/constraints/au280_timing.tcl b/hw/lib/common/constraints/au280_timing.tcl index 63c2faf..d1e0022 100644 --- a/hw/lib/common/constraints/au280_timing.tcl +++ b/hw/lib/common/constraints/au280_timing.tcl @@ -15,6 +15,7 @@ # limitations under the License. # # ************************************************************************* +create_clock -period 4.000 -name axis_aclk [get_nets u_top_wrapper/axis_aclk] set_false_path -through [get_ports pci_rst_n] set axis_aclk [get_clocks -of_object [get_nets u_top_wrapper/axis_aclk]] diff --git a/hw/lib/common/constraints/vcu1525_general.xdc b/hw/lib/common/constraints/vcu1525_general.xdc index d31bc85..00ca799 100644 --- a/hw/lib/common/constraints/vcu1525_general.xdc +++ b/hw/lib/common/constraints/vcu1525_general.xdc @@ -133,6 +133,14 @@ set_property -dict { LOC T2 } [get_ports QSFP1_RX_P[1]] set_property -dict { LOC T1 } [get_ports QSFP1_RX_N[1]] set_property -dict { LOC U4 } [get_ports QSFP1_RX_P[0]] set_property -dict { LOC U3 } [get_ports QSFP1_RX_N[0]] + +# Satellite Core +set_property -dict {PACKAGE_PIN BB19 IOSTANDARD LVCMOS12 DRIVE 8} [get_ports satellite_uart_0_txd] +set_property -dict {PACKAGE_PIN BA19 IOSTANDARD LVCMOS12} [get_ports satellite_uart_0_rxd] +set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[0]] +set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[1]] +set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[2]] +set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS12} [get_ports satellite_gpio[3]] ########################################################################## # Timing ########################################################################## diff --git a/hw/lib/common/hdl/nf_attachment.sv b/hw/lib/common/hdl/nf_attachment.sv index 4548b82..4aca5ff 100644 --- a/hw/lib/common/hdl/nf_attachment.sv +++ b/hw/lib/common/hdl/nf_attachment.sv @@ -271,7 +271,7 @@ module nf_attachment #( wire S2_AXI_BVALID, S1_AXI_BVALID, S0_AXI_BVALID; wire S2_AXI_AWREADY, S1_AXI_AWREADY, S0_AXI_AWREADY; - axi_crossbar_0 u_crossbar_m0 ( + axi_crossbar_1 u_crossbar_m1 ( .aclk (axil_aclk), .aresetn (!axil_rst), .s_axi_awaddr (m0_axil_awaddr ), diff --git a/hw/lib/common/hdl/top.v b/hw/lib/common/hdl/top.v index eb0d946..db27bc5 100644 --- a/hw/lib/common/hdl/top.v +++ b/hw/lib/common/hdl/top.v @@ -36,8 +36,34 @@ module top #( parameter NF_C_S_AXI_DATA_WIDTH = 32, parameter NF_C_S_AXI_ADDR_WIDTH = 32 )( -`ifdef BOARD_AU280 - output wire STAT_CATTRIP, +`ifdef __au280__ + output wire hbm_cattrip, + input wire [3:0] satellite_gpio, +`elsif __au50__ + output wire hbm_cattrip, + input wire [1:0] satellite_gpio, +`elsif __au55n__ + output wire hbm_cattrip, + input wire [3:0] satellite_gpio, +`elsif __au55c__ + output wire hbm_cattrip, + input wire [3:0] satellite_gpio, +`elsif __au200__ + //output [1:0] qsfp_resetl, + //input [1:0] qsfp_modprsl, + //input [1:0] qsfp_intl, + //output [1:0] qsfp_lpmode, + //output [1:0] qsfp_modsell, + input wire [3:0] satellite_gpio, +`elsif __au250__ + //output [1:0] qsfp_resetl, + //input [1:0] qsfp_modprsl, + //input [1:0] qsfp_intl, + //output [1:0] qsfp_lpmode, + //output [1:0] qsfp_modsell, + input wire [3:0] satellite_gpio, +`elsif __au45n__ + input wire [1:0] satellite_gpio, `endif input wire QSFP0_CLOCK_P, input wire QSFP0_CLOCK_N, @@ -82,6 +108,10 @@ module top #( input wire [3:0] QSFP1_RX_P, input wire [3:0] QSFP1_RX_N, + // Satellite core + input wire satellite_uart_0_rxd, + output wire satellite_uart_0_txd, + input wire sysclk_p, input wire sysclk_n, @@ -95,9 +125,9 @@ module top #( input wire [15:0] pcie_rxn ); -`ifdef BOARD_AU280 - assign STAT_CATTRIP = 1'b0; -`endif +//`ifdef BOARD_AU280 +// assign STAT_CATTRIP = 1'b0; +//`endif `ifndef BOARD_AU280 // QSFP Clock for 156.25MHz (2'b01) @@ -505,6 +535,35 @@ module top #( .C_TDATA_WIDTH (C_IF_DATA_WIDTH), .C_TUSER_WIDTH (C_IF_TUSER_WIDTH) ) u_top_wrapper ( +`ifdef __au280__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au50__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au55n__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au55c__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au200__ + .qsfp_resetl (/*qsfp_resetl */), + .qsfp_modprsl (/*qsfp_modprsl */), + .qsfp_intl (/*qsfp_intl */), + .qsfp_lpmode (/*qsfp_lpmode */), + .qsfp_modsell (/*qsfp_modsell */), + .satellite_gpio (satellite_gpio), +`elsif __au250__ + .qsfp_resetl (/*qsfp_resetl */), + .qsfp_modprsl (/*qsfp_modprsl */), + .qsfp_intl (/*qsfp_intl */), + .qsfp_lpmode (/*qsfp_lpmode */), + .qsfp_modsell (/*qsfp_modsell */), + .satellite_gpio (satellite_gpio), +`elsif __au45n__ + .satellite_gpio (satellite_gpio), +`endif // QSFP port0 .qsfp0_rxp (QSFP0_RX_P), .qsfp0_rxn (QSFP0_RX_N), @@ -530,6 +589,9 @@ module top #( .pcie_clk_p (pci_clk_p), .pcie_clk_n (pci_clk_n), .pcie_rst_n (pci_rst_n), + // Satellite core + .satellite_uart_0_rxd(satellite_uart_0_rxd), + .satellite_uart_0_txd(satellite_uart_0_txd), .m_axil_awvalid (m_axil_awvalid), .m_axil_awaddr (m_axil_awaddr ), diff --git a/hw/lib/common/hdl/top_wrapper.sv b/hw/lib/common/hdl/top_wrapper.sv index 830f7e7..e34f0dc 100644 --- a/hw/lib/common/hdl/top_wrapper.sv +++ b/hw/lib/common/hdl/top_wrapper.sv @@ -29,6 +29,35 @@ module top_wrapper #( parameter C_TDATA_WIDTH = 512, parameter C_TUSER_WIDTH = 128 )( +`ifdef __au280__ + output hbm_cattrip, + input [3:0] satellite_gpio, +`elsif __au50__ + output hbm_cattrip, + input [1:0] satellite_gpio, +`elsif __au55n__ + output hbm_cattrip, + input [3:0] satellite_gpio, +`elsif __au55c__ + output hbm_cattrip, + input [3:0] satellite_gpio, +`elsif __au200__ + output [1:0] qsfp_resetl, + input [1:0] qsfp_modprsl, + input [1:0] qsfp_intl, + output [1:0] qsfp_lpmode, + output [1:0] qsfp_modsell, + input [3:0] satellite_gpio, +`elsif __au250__ + output [1:0] qsfp_resetl, + input [1:0] qsfp_modprsl, + input [1:0] qsfp_intl, + output [1:0] qsfp_lpmode, + output [1:0] qsfp_modsell, + input [3:0] satellite_gpio, +`elsif __au45n__ + input [1:0] satellite_gpio, +`endif // QSFP port0 input [3:0] qsfp0_rxp, input [3:0] qsfp0_rxn, @@ -55,6 +84,10 @@ module top_wrapper #( input pcie_clk_n, input pcie_rst_n, + // Satellite core + input satellite_uart_0_rxd, + output satellite_uart_0_txd, + output m_axil_awvalid, output [31:0] m_axil_awaddr, input m_axil_awready, @@ -399,6 +432,39 @@ module top_wrapper #( .qsfp_txn ({qsfp1_txn, qsfp0_txn}), .qsfp_refclk_p ({qsfp1_clk_p, qsfp0_clk_p}), .qsfp_refclk_n ({qsfp1_clk_n, qsfp0_clk_n}), + + .satellite_uart_0_rxd(satellite_uart_0_rxd), + .satellite_uart_0_txd(satellite_uart_0_txd), +`ifdef __au280__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au50__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au55n__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au55c__ + .hbm_cattrip (hbm_cattrip ), + .satellite_gpio (satellite_gpio), +`elsif __au200__ + .qsfp_resetl (qsfp_resetl ), + .qsfp_modprsl (qsfp_modprsl ), + .qsfp_intl (qsfp_intl ), + .qsfp_lpmode (qsfp_lpmode ), + .qsfp_modsell (qsfp_modsell ), + .satellite_gpio (satellite_gpio), +`elsif __au250__ + .qsfp_resetl (qsfp_resetl ), + .qsfp_modprsl (qsfp_modprsl ), + .qsfp_intl (qsfp_intl ), + .qsfp_lpmode (qsfp_lpmode ), + .qsfp_modsell (qsfp_modsell ), + .satellite_gpio (satellite_gpio), +`elsif __au45n__ + .satellite_gpio (satellite_gpio), +`endif + `else // !`ifdef __synthesis__ .s_axil_awvalid (), .s_axil_awaddr (), diff --git a/hw/lib/xilinx/cam_v1_1_0/cam.tcl b/hw/lib/xilinx/cam_v1_1_0/cam.tcl index 3f9ca96..f8cb04f 100644 --- a/hw/lib/xilinx/cam_v1_1_0/cam.tcl +++ b/hw/lib/xilinx/cam_v1_1_0/cam.tcl @@ -31,9 +31,10 @@ set lib_name xilinx set ip_version 1.1 set design cam -set device $::env(DEVICE) +set device $::env(DEVICE) set proj_dir ip_proj +set_param board.repoPaths $::env(BOARD_FILE_PATH) # Project setting create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip diff --git a/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl b/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl index 10b6cde..0c6ef4f 100644 --- a/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl +++ b/hw/lib/xilinx/tcam_v1_1_0/tcam.tcl @@ -33,6 +33,7 @@ set design tcam set device $::env(DEVICE) set proj_dir ip_proj +set_param board.repoPaths $::env(BOARD_FILE_PATH) # Project setting create_project -name ${design} -force -dir "./${proj_dir}" -part ${device} -ip diff --git a/hw/lib/xilinx/xilinx_shell_v1_0_0/hdl/open_nic_shell.sv b/hw/lib/xilinx/xilinx_shell_v1_0_0/hdl/open_nic_shell.sv index 3b2316e..b15b355 100644 --- a/hw/lib/xilinx/xilinx_shell_v1_0_0/hdl/open_nic_shell.sv +++ b/hw/lib/xilinx/xilinx_shell_v1_0_0/hdl/open_nic_shell.sv @@ -19,17 +19,23 @@ //`define __synthesis__ `timescale 1ns/1ps module open_nic_shell #( - parameter int MAX_PKT_LEN = 1518, - parameter int MIN_PKT_LEN = 64, - parameter int USE_PHYS_FUNC = 1, - parameter int NUM_PHYS_FUNC = 2, - parameter int NUM_QUEUE = 2048, - parameter int NUM_CMAC_PORT = 2 + parameter [31:0] BUILD_TIMESTAMP = 32'h01010000, + parameter int MAX_PKT_LEN = 1518, + parameter int MIN_PKT_LEN = 64, + parameter int NUM_QDMA = 1, + parameter int USE_PHYS_FUNC = 1, + parameter int NUM_PHYS_FUNC = 2, + parameter int NUM_QUEUE = 2048, + parameter int NUM_CMAC_PORT = 2 ) ( `ifndef sim -`ifdef __au280__ - output hbm_cattrip, // Fix the CATTRIP issue for AU280 custom flow -`endif + output hbm_cattrip, + input [3:0] satellite_gpio, + output [1:0] qsfp_resetl, + input [1:0] qsfp_modprsl, + input [1:0] qsfp_intl, + output [1:0] qsfp_lpmode, + output [1:0] qsfp_modsell, input [15:0] pcie_rxp, input [15:0] pcie_rxn, @@ -45,6 +51,9 @@ module open_nic_shell #( output [4*NUM_CMAC_PORT-1:0] qsfp_txn, input [NUM_CMAC_PORT-1:0] qsfp_refclk_p, input [NUM_CMAC_PORT-1:0] qsfp_refclk_n, + + input satellite_uart_0_rxd, + output satellite_uart_0_txd, `else // !`ifndef sim input s_axil_sim_awvalid, input [31:0] s_axil_sim_awaddr, @@ -370,7 +379,9 @@ module open_nic_shell #( endgenerate system_config #( - .NUM_CMAC_PORT (NUM_CMAC_PORT) + .BUILD_TIMESTAMP (BUILD_TIMESTAMP), + .NUM_QDMA (NUM_QDMA), + .NUM_CMAC_PORT (NUM_CMAC_PORT) ) system_config_inst ( `ifndef sim .s_axil_awvalid (axil_pcie_awvalid), @@ -498,6 +509,41 @@ module open_nic_shell #( .user_rstn (user_rstn), .user_rst_done (user_rst_done), + .satellite_uart_0_rxd (satellite_uart_0_rxd), + .satellite_uart_0_txd (satellite_uart_0_txd), + .satellite_gpio_0 (satellite_gpio), + + `ifdef __au280__ + .hbm_temp_1_0 (7'd0), + .hbm_temp_2_0 (7'd0), + .interrupt_hbm_cattrip_0 (1'b0), + `elsif __au55n__ + .hbm_temp_1_0 (7'd0), + .hbm_temp_2_0 (7'd0), + .interrupt_hbm_cattrip_0 (1'b0), + `elsif __au55c__ + .hbm_temp_1_0 (7'd0), + .hbm_temp_2_0 (7'd0), + .interrupt_hbm_cattrip_0 (1'b0), + `elsif __au50__ + .hbm_temp_1_0 (7'd0), + .hbm_temp_2_0 (7'd0), + .interrupt_hbm_cattrip_0 (1'b0), + `elsif __au200__ + .qsfp_resetl (qsfp_resetl), + .qsfp_modprsl (qsfp_modprsl), + .qsfp_intl (qsfp_intl), + .qsfp_lpmode (qsfp_lpmode), + .qsfp_modsell (qsfp_modsell), + `elsif __au250__ + .qsfp_resetl (qsfp_resetl), + .qsfp_modprsl (qsfp_modprsl), + .qsfp_intl (qsfp_intl), + .qsfp_lpmode (qsfp_lpmode), + .qsfp_modsell (qsfp_modsell), + `elsif __au45n__ + + `endif .aclk (axil_aclk), .aresetn (powerup_rstn) ); @@ -618,7 +664,19 @@ module open_nic_shell #( .mod_rstn (qdma_rstn), .mod_rst_done (qdma_rst_done), + .axil_cfg_aclk (axil_aclk), .axil_aclk (axil_aclk), + + `ifdef __au55n__ + .ref_clk_100mhz (ref_clk_100mhz), + `elsif __au55c__ + .ref_clk_100mhz (ref_clk_100mhz), + `elsif __au50__ + .ref_clk_100mhz (ref_clk_100mhz), + `elsif __au280__ + .ref_clk_100mhz (ref_clk_100mhz), + `endif + .axis_master_aclk (axis_aclk), .axis_aclk (axis_aclk) ); diff --git a/hw/lib/xilinx/xilinx_shell_v1_0_0/xilinx_shell.tcl b/hw/lib/xilinx/xilinx_shell_v1_0_0/xilinx_shell.tcl index 1cee759..6bc6fab 100644 --- a/hw/lib/xilinx/xilinx_shell_v1_0_0/xilinx_shell.tcl +++ b/hw/lib/xilinx/xilinx_shell_v1_0_0/xilinx_shell.tcl @@ -34,6 +34,7 @@ set proj_dir ./ip_proj set ip_version 1.0 set lib_name xilinx set proj ./proj +set_param board.repoPaths $::env(BOARD_FILE_PATH) ##################################### # Project Settings ##################################### @@ -42,11 +43,23 @@ set_property BOARD_PART $board [current_project] set_property source_mgmt_mode All [current_project] set_property top ${top} [current_fileset] set_property ip_repo_paths $::env(NFPLUS_FOLDER)/hw/lib/ [current_fileset] -set_property verilog_define { {__synthesis__} } [current_fileset] +if {[string match $board_name "au280"]} { + set_property verilog_define { {__synthesis__} {__au280__}} [current_fileset] +} elseif {[string match $board_name "au250"]} { + set_property verilog_define { {__synthesis__} {__au250__}} [current_fileset] +} elseif {[string match $board_name "au200"]} { + set_property verilog_define { {__synthesis__} {__au200__}} [current_fileset] +} elseif {[string match $board_name "vcu1525"]} { + set_property verilog_define { {__synthesis__} {__au200__}} [current_fileset] +} else { + puts "Error: ${board_name} is not found." + exit -1 +} puts "Creating Xiilnx Xilinx OpenNIC Shell IP" ##################################### # Design Parameters ##################################### +set num_qdma 1 set num_phys_func 2 set num_queue 2048 set min_pkt_len 64 @@ -69,6 +82,7 @@ read_verilog -sv "open-nic-shell/src/qdma_subsystem/qdma_subsystem_hash.sv" read_verilog "open-nic-shell/src/qdma_subsystem/qdma_subsystem_qdma_wrapper.v" read_verilog -sv "open-nic-shell/src/qdma_subsystem/qdma_subsystem_register.sv" read_verilog -sv "open-nic-shell/src/qdma_subsystem/qdma_subsystem.sv" +read_verilog -sv "open-nic-shell/src/system_config/cms_subsystem.sv" read_verilog -sv "open-nic-shell/src/system_config/system_config_address_map.sv" read_verilog "open-nic-shell/src/system_config/system_config_register.v" read_verilog -sv "open-nic-shell/src/system_config/system_config.sv" @@ -127,7 +141,8 @@ generate_target {instantiation_template} [get_files ./${proj}/${axi_crossbar}/${ generate_target all [get_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci] ipx::package_project -force -import_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci -source "vivado_ip/qdma_subsystem_axi_cdc.tcl" +#source "vivado_ip/qdma_subsystem_axi_cdc.tcl" +source "open-nic-shell/src/qdma_subsystem/vivado_ip/qdma_subsystem_axi_cdc.tcl" generate_target {instantiation_template} [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] generate_target all [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] ipx::package_project -force -import_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci @@ -137,7 +152,8 @@ generate_target {instantiation_template} [get_files ./${proj}/${axi_crossbar}/${ generate_target all [get_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci] ipx::package_project -force -import_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci -source "vivado_ip/qdma_subsystem_clk_div.tcl" +#source "vivado_ip/qdma_subsystem_clk_div.tcl" +source "open-nic-shell/src/qdma_subsystem/vivado_ip/qdma_subsystem_clk_div.tcl" generate_target {instantiation_template} [get_files ./${proj}/${clk_wiz}/${clk_wiz}.xci] generate_target all [get_files ./${proj}/${clk_wiz}/${clk_wiz}.xci] ipx::package_project -force -import_files ./${proj}/${clk_wiz}/${clk_wiz}.xci @@ -165,7 +181,37 @@ generate_target {instantiation_template} [get_files ./${proj}/${axi_crossbar}/${ generate_target all [get_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci] ipx::package_project -force -import_files ./${proj}/${axi_crossbar}/${axi_crossbar}.xci -update_ip_catalog -rebuild +source "open-nic-shell/src/system_config/vivado_ip/system_management_wiz.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${system_management_wiz}/${system_management_wiz}.xci] +generate_target all [get_files ./${proj}/${system_management_wiz}/${system_management_wiz}.xci] +ipx::package_project -force -import_files ./${proj}/${system_management_wiz}/${system_management_wiz}.xci + +source "open-nic-shell/src/system_config/vivado_ip/clk_wiz_50Mhz.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${clk_wiz_50Mhz}/${clk_wiz_50Mhz}.xci] +generate_target all [get_files ./${proj}/${clk_wiz_50Mhz}/${clk_wiz_50Mhz}.xci] +ipx::package_project -force -import_files ./${proj}/${clk_wiz_50Mhz}/${clk_wiz_50Mhz}.xci + +source "open-nic-shell/src/system_config/vivado_ip/axi_quad_spi_0.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${axi_quad_spi}/${axi_quad_spi}.xci] +generate_target all [get_files ./${proj}/${axi_quad_spi}/${axi_quad_spi}.xci] +ipx::package_project -force -import_files ./${proj}/${axi_quad_spi}/${axi_quad_spi}.xci + +source "open-nic-shell/src/system_config/vivado_ip/cms_subsystem_0.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${cms_subsystem}/${cms_subsystem}.xci] +generate_target all [get_files ./${proj}/${cms_subsystem}/${cms_subsystem}.xci] +ipx::package_project -force -import_files ./${proj}/${cms_subsystem}/${cms_subsystem}.xci + +source "open-nic-shell/src/system_config/vivado_ip/system_config_axi_clock_converter.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] +generate_target all [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] +ipx::package_project -force -import_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci + +source "open-nic-shell/src/utility/vivado_ip/axi_lite_clock_converter.tcl" +generate_target {instantiation_template} [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] +generate_target all [get_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci] +ipx::package_project -force -import_files ./${proj}/${axi_clock_converter}/${axi_clock_converter}.xci + +update_ip_catalog -rebuild ipx::infer_user_parameters [ipx::current_core] set_property name ${design} [ipx::current_core] diff --git a/hw/projects/reference_nic/hw/tcl/reference_nic.tcl b/hw/projects/reference_nic/hw/tcl/reference_nic.tcl index 1f068fb..3dc9507 100644 --- a/hw/projects/reference_nic/hw/tcl/reference_nic.tcl +++ b/hw/projects/reference_nic/hw/tcl/reference_nic.tcl @@ -38,6 +38,7 @@ set project_constraints "${public_repo_dir}/common/constraints/${board_name}_gen set start_time [exec date +%s] set_param general.maxThreads 8 set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 200000" +set_param board.repoPaths $::env(BOARD_FILE_PATH) ##################################### # Design Parameters on NF_DATAPATH ##################################### @@ -51,16 +52,16 @@ set_property board_part ${board} [current_project] set_property source_mgmt_mode DisplayOnly [current_project] set_property top ${top} [current_fileset] if {[string match $board_name "au280"]} { - set_property verilog_define { {BOARD_AU280} {au280} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU280} {au280} {__au280__} {__synthesis__} } [current_fileset] set board_param "AU280" } elseif {[string match $board_name "au250"]} { - set_property verilog_define { {BOARD_AU250} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU250} {__au250__} {__synthesis__} } [current_fileset] set board_param "AU250" } elseif {[string match $board_name "au200"]} { - set_property verilog_define { {BOARD_AU200} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU200} {__au200__} {__synthesis__} } [current_fileset] set board_param "AU200" } elseif {[string match $board_name "vcu1525"]} { - set_property verilog_define { {BOARD_VCU1525} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_VCU1525} {__au200__} {__synthesis__} } [current_fileset] set board_param "VCU1525" } set_property generic "C_NF_DATA_WIDTH=${datapath_width_bit} BOARD=\"${board_param}\"" [current_fileset] @@ -222,6 +223,87 @@ set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci] reset_target all [get_ips axi_crossbar_0] generate_target all [get_ips axi_crossbar_0] +create_ip -name axi_crossbar -vendor xilinx.com -library ip -module_name axi_crossbar_1 +set_property -dict [list \ +CONFIG.NUM_MI {3} \ +CONFIG.PROTOCOL {AXI4LITE} \ +CONFIG.CONNECTIVITY_MODE {SASD} \ +CONFIG.R_REGISTER {1} \ +CONFIG.S00_WRITE_ACCEPTANCE {1} \ +CONFIG.S01_WRITE_ACCEPTANCE {1} \ +CONFIG.S02_WRITE_ACCEPTANCE {1} \ +CONFIG.S03_WRITE_ACCEPTANCE {1} \ +CONFIG.S04_WRITE_ACCEPTANCE {1} \ +CONFIG.S05_WRITE_ACCEPTANCE {1} \ +CONFIG.S06_WRITE_ACCEPTANCE {1} \ +CONFIG.S07_WRITE_ACCEPTANCE {1} \ +CONFIG.S08_WRITE_ACCEPTANCE {1} \ +CONFIG.S09_WRITE_ACCEPTANCE {1} \ +CONFIG.S10_WRITE_ACCEPTANCE {1} \ +CONFIG.S11_WRITE_ACCEPTANCE {1} \ +CONFIG.S12_WRITE_ACCEPTANCE {1} \ +CONFIG.S13_WRITE_ACCEPTANCE {1} \ +CONFIG.S14_WRITE_ACCEPTANCE {1} \ +CONFIG.S15_WRITE_ACCEPTANCE {1} \ +CONFIG.S00_READ_ACCEPTANCE {1} \ +CONFIG.S01_READ_ACCEPTANCE {1} \ +CONFIG.S02_READ_ACCEPTANCE {1} \ +CONFIG.S03_READ_ACCEPTANCE {1} \ +CONFIG.S04_READ_ACCEPTANCE {1} \ +CONFIG.S05_READ_ACCEPTANCE {1} \ +CONFIG.S06_READ_ACCEPTANCE {1} \ +CONFIG.S07_READ_ACCEPTANCE {1} \ +CONFIG.S08_READ_ACCEPTANCE {1} \ +CONFIG.S09_READ_ACCEPTANCE {1} \ +CONFIG.S10_READ_ACCEPTANCE {1} \ +CONFIG.S11_READ_ACCEPTANCE {1} \ +CONFIG.S12_READ_ACCEPTANCE {1} \ +CONFIG.S13_READ_ACCEPTANCE {1} \ +CONFIG.S14_READ_ACCEPTANCE {1} \ +CONFIG.S15_READ_ACCEPTANCE {1} \ +CONFIG.M00_WRITE_ISSUING {1} \ +CONFIG.M01_WRITE_ISSUING {1} \ +CONFIG.M02_WRITE_ISSUING {1} \ +CONFIG.M03_WRITE_ISSUING {1} \ +CONFIG.M04_WRITE_ISSUING {1} \ +CONFIG.M05_WRITE_ISSUING {1} \ +CONFIG.M06_WRITE_ISSUING {1} \ +CONFIG.M07_WRITE_ISSUING {1} \ +CONFIG.M08_WRITE_ISSUING {1} \ +CONFIG.M09_WRITE_ISSUING {1} \ +CONFIG.M10_WRITE_ISSUING {1} \ +CONFIG.M11_WRITE_ISSUING {1} \ +CONFIG.M12_WRITE_ISSUING {1} \ +CONFIG.M13_WRITE_ISSUING {1} \ +CONFIG.M14_WRITE_ISSUING {1} \ +CONFIG.M15_WRITE_ISSUING {1} \ +CONFIG.M00_READ_ISSUING {1} \ +CONFIG.M01_READ_ISSUING {1} \ +CONFIG.M02_READ_ISSUING {1} \ +CONFIG.M03_READ_ISSUING {1} \ +CONFIG.M04_READ_ISSUING {1} \ +CONFIG.M05_READ_ISSUING {1} \ +CONFIG.M06_READ_ISSUING {1} \ +CONFIG.M07_READ_ISSUING {1} \ +CONFIG.M08_READ_ISSUING {1} \ +CONFIG.M09_READ_ISSUING {1} \ +CONFIG.M10_READ_ISSUING {1} \ +CONFIG.M11_READ_ISSUING {1} \ +CONFIG.M12_READ_ISSUING {1} \ +CONFIG.M13_READ_ISSUING {1} \ +CONFIG.M14_READ_ISSUING {1} \ +CONFIG.M15_READ_ISSUING {1} \ +CONFIG.S00_SINGLE_THREAD {1} \ +CONFIG.M00_A00_ADDR_WIDTH {16} \ +CONFIG.M01_A00_ADDR_WIDTH {16} \ +CONFIG.M02_A00_ADDR_WIDTH {16} \ +CONFIG.M00_A00_BASE_ADDR {0x0000000000000000}\ +CONFIG.M01_A00_BASE_ADDR {0x0000000000010000}\ +CONFIG.M02_A00_BASE_ADDR {0x0000000000020000}] [get_ips axi_crossbar_1] +set_property generate_synth_checkpoint false [get_files axi_crossbar_1.xci] +reset_target all [get_ips axi_crossbar_1] +generate_target all [get_ips axi_crossbar_1] + create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name axi_clock_converter_0 set_property -dict { CONFIG.PROTOCOL {AXI4LITE} diff --git a/hw/projects/reference_router/hw/tcl/reference_router.tcl b/hw/projects/reference_router/hw/tcl/reference_router.tcl index d9a9d37..6b455b6 100644 --- a/hw/projects/reference_router/hw/tcl/reference_router.tcl +++ b/hw/projects/reference_router/hw/tcl/reference_router.tcl @@ -38,6 +38,7 @@ set project_constraints "${public_repo_dir}/common/constraints/${board_name}_gen set start_time [exec date +%s] set_param general.maxThreads 8 set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 200000" +set_param board.repoPaths $::env(BOARD_FILE_PATH) ##################################### # Design Parameters on NF_DATAPATH ##################################### @@ -51,16 +52,16 @@ set_property board_part ${board} [current_project] set_property source_mgmt_mode DisplayOnly [current_project] set_property top ${top} [current_fileset] if {[string match $board_name "au280"]} { - set_property verilog_define { {BOARD_AU280} {au280} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU280} {au280} {__au280__} {__synthesis__} } [current_fileset] set board_param "AU280" } elseif {[string match $board_name "au250"]} { - set_property verilog_define { {BOARD_AU250} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU250} {__au250__} {__synthesis__} } [current_fileset] set board_param "AU250" } elseif {[string match $board_name "au200"]} { - set_property verilog_define { {BOARD_AU200} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU200} {__au200__} {__synthesis__} } [current_fileset] set board_param "AU200" } elseif {[string match $board_name "vcu1525"]} { - set_property verilog_define { {BOARD_VCU1525} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_VCU1525} {__au200__} {__synthesis__} } [current_fileset] set board_param "VCU1525" } set_property generic "C_NF_DATA_WIDTH=${datapath_width_bit} BOARD=\"${board_param}\"" [current_fileset] @@ -229,6 +230,87 @@ set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci] reset_target all [get_ips axi_crossbar_0] generate_target all [get_ips axi_crossbar_0] +create_ip -name axi_crossbar -vendor xilinx.com -library ip -module_name axi_crossbar_1 +set_property -dict [list \ +CONFIG.NUM_MI {3} \ +CONFIG.PROTOCOL {AXI4LITE} \ +CONFIG.CONNECTIVITY_MODE {SASD} \ +CONFIG.R_REGISTER {1} \ +CONFIG.S00_WRITE_ACCEPTANCE {1} \ +CONFIG.S01_WRITE_ACCEPTANCE {1} \ +CONFIG.S02_WRITE_ACCEPTANCE {1} \ +CONFIG.S03_WRITE_ACCEPTANCE {1} \ +CONFIG.S04_WRITE_ACCEPTANCE {1} \ +CONFIG.S05_WRITE_ACCEPTANCE {1} \ +CONFIG.S06_WRITE_ACCEPTANCE {1} \ +CONFIG.S07_WRITE_ACCEPTANCE {1} \ +CONFIG.S08_WRITE_ACCEPTANCE {1} \ +CONFIG.S09_WRITE_ACCEPTANCE {1} \ +CONFIG.S10_WRITE_ACCEPTANCE {1} \ +CONFIG.S11_WRITE_ACCEPTANCE {1} \ +CONFIG.S12_WRITE_ACCEPTANCE {1} \ +CONFIG.S13_WRITE_ACCEPTANCE {1} \ +CONFIG.S14_WRITE_ACCEPTANCE {1} \ +CONFIG.S15_WRITE_ACCEPTANCE {1} \ +CONFIG.S00_READ_ACCEPTANCE {1} \ +CONFIG.S01_READ_ACCEPTANCE {1} \ +CONFIG.S02_READ_ACCEPTANCE {1} \ +CONFIG.S03_READ_ACCEPTANCE {1} \ +CONFIG.S04_READ_ACCEPTANCE {1} \ +CONFIG.S05_READ_ACCEPTANCE {1} \ +CONFIG.S06_READ_ACCEPTANCE {1} \ +CONFIG.S07_READ_ACCEPTANCE {1} \ +CONFIG.S08_READ_ACCEPTANCE {1} \ +CONFIG.S09_READ_ACCEPTANCE {1} \ +CONFIG.S10_READ_ACCEPTANCE {1} \ +CONFIG.S11_READ_ACCEPTANCE {1} \ +CONFIG.S12_READ_ACCEPTANCE {1} \ +CONFIG.S13_READ_ACCEPTANCE {1} \ +CONFIG.S14_READ_ACCEPTANCE {1} \ +CONFIG.S15_READ_ACCEPTANCE {1} \ +CONFIG.M00_WRITE_ISSUING {1} \ +CONFIG.M01_WRITE_ISSUING {1} \ +CONFIG.M02_WRITE_ISSUING {1} \ +CONFIG.M03_WRITE_ISSUING {1} \ +CONFIG.M04_WRITE_ISSUING {1} \ +CONFIG.M05_WRITE_ISSUING {1} \ +CONFIG.M06_WRITE_ISSUING {1} \ +CONFIG.M07_WRITE_ISSUING {1} \ +CONFIG.M08_WRITE_ISSUING {1} \ +CONFIG.M09_WRITE_ISSUING {1} \ +CONFIG.M10_WRITE_ISSUING {1} \ +CONFIG.M11_WRITE_ISSUING {1} \ +CONFIG.M12_WRITE_ISSUING {1} \ +CONFIG.M13_WRITE_ISSUING {1} \ +CONFIG.M14_WRITE_ISSUING {1} \ +CONFIG.M15_WRITE_ISSUING {1} \ +CONFIG.M00_READ_ISSUING {1} \ +CONFIG.M01_READ_ISSUING {1} \ +CONFIG.M02_READ_ISSUING {1} \ +CONFIG.M03_READ_ISSUING {1} \ +CONFIG.M04_READ_ISSUING {1} \ +CONFIG.M05_READ_ISSUING {1} \ +CONFIG.M06_READ_ISSUING {1} \ +CONFIG.M07_READ_ISSUING {1} \ +CONFIG.M08_READ_ISSUING {1} \ +CONFIG.M09_READ_ISSUING {1} \ +CONFIG.M10_READ_ISSUING {1} \ +CONFIG.M11_READ_ISSUING {1} \ +CONFIG.M12_READ_ISSUING {1} \ +CONFIG.M13_READ_ISSUING {1} \ +CONFIG.M14_READ_ISSUING {1} \ +CONFIG.M15_READ_ISSUING {1} \ +CONFIG.S00_SINGLE_THREAD {1} \ +CONFIG.M00_A00_ADDR_WIDTH {16} \ +CONFIG.M01_A00_ADDR_WIDTH {16} \ +CONFIG.M02_A00_ADDR_WIDTH {16} \ +CONFIG.M00_A00_BASE_ADDR {0x0000000000000000}\ +CONFIG.M01_A00_BASE_ADDR {0x0000000000010000}\ +CONFIG.M02_A00_BASE_ADDR {0x0000000000020000}] [get_ips axi_crossbar_1] +set_property generate_synth_checkpoint false [get_files axi_crossbar_1.xci] +reset_target all [get_ips axi_crossbar_1] +generate_target all [get_ips axi_crossbar_1] + create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name axi_clock_converter_0 set_property -dict { CONFIG.PROTOCOL {AXI4LITE} diff --git a/hw/projects/reference_switch/hw/tcl/reference_switch.tcl b/hw/projects/reference_switch/hw/tcl/reference_switch.tcl index dc5191c..29276bc 100644 --- a/hw/projects/reference_switch/hw/tcl/reference_switch.tcl +++ b/hw/projects/reference_switch/hw/tcl/reference_switch.tcl @@ -38,6 +38,7 @@ set project_constraints "${public_repo_dir}/common/constraints/${board_name}_gen set start_time [exec date +%s] set_param general.maxThreads 8 set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 200000" +set_param board.repoPaths $::env(BOARD_FILE_PATH) ##################################### # Design Parameters on NF_DATAPATH ##################################### @@ -54,16 +55,16 @@ set_property board_part ${board} [current_project] set_property source_mgmt_mode DisplayOnly [current_project] set_property top ${top} [current_fileset] if {[string match $board_name "au280"]} { - set_property verilog_define { {BOARD_AU280} {au280} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU280} {au280} {__au280__} {__synthesis__} } [current_fileset] set board_param "AU280" } elseif {[string match $board_name "au250"]} { - set_property verilog_define { {BOARD_AU250} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU250} {__au250__} {__synthesis__} } [current_fileset] set board_param "AU250" } elseif {[string match $board_name "au200"]} { - set_property verilog_define { {BOARD_AU200} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU200} {__au200__} {__synthesis__} } [current_fileset] set board_param "AU200" } elseif {[string match $board_name "vcu1525"]} { - set_property verilog_define { {BOARD_VCU1525} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_VCU1525} {__au200__} {__synthesis__} } [current_fileset] set board_param "VCU1525" } set_property generic "C_NF_DATA_WIDTH=${datapath_width_bit} BOARD=\"${board_param}\"" [current_fileset] @@ -227,6 +228,87 @@ set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci] reset_target all [get_ips axi_crossbar_0] generate_target all [get_ips axi_crossbar_0] +create_ip -name axi_crossbar -vendor xilinx.com -library ip -module_name axi_crossbar_1 +set_property -dict [list \ +CONFIG.NUM_MI {3} \ +CONFIG.PROTOCOL {AXI4LITE} \ +CONFIG.CONNECTIVITY_MODE {SASD} \ +CONFIG.R_REGISTER {1} \ +CONFIG.S00_WRITE_ACCEPTANCE {1} \ +CONFIG.S01_WRITE_ACCEPTANCE {1} \ +CONFIG.S02_WRITE_ACCEPTANCE {1} \ +CONFIG.S03_WRITE_ACCEPTANCE {1} \ +CONFIG.S04_WRITE_ACCEPTANCE {1} \ +CONFIG.S05_WRITE_ACCEPTANCE {1} \ +CONFIG.S06_WRITE_ACCEPTANCE {1} \ +CONFIG.S07_WRITE_ACCEPTANCE {1} \ +CONFIG.S08_WRITE_ACCEPTANCE {1} \ +CONFIG.S09_WRITE_ACCEPTANCE {1} \ +CONFIG.S10_WRITE_ACCEPTANCE {1} \ +CONFIG.S11_WRITE_ACCEPTANCE {1} \ +CONFIG.S12_WRITE_ACCEPTANCE {1} \ +CONFIG.S13_WRITE_ACCEPTANCE {1} \ +CONFIG.S14_WRITE_ACCEPTANCE {1} \ +CONFIG.S15_WRITE_ACCEPTANCE {1} \ +CONFIG.S00_READ_ACCEPTANCE {1} \ +CONFIG.S01_READ_ACCEPTANCE {1} \ +CONFIG.S02_READ_ACCEPTANCE {1} \ +CONFIG.S03_READ_ACCEPTANCE {1} \ +CONFIG.S04_READ_ACCEPTANCE {1} \ +CONFIG.S05_READ_ACCEPTANCE {1} \ +CONFIG.S06_READ_ACCEPTANCE {1} \ +CONFIG.S07_READ_ACCEPTANCE {1} \ +CONFIG.S08_READ_ACCEPTANCE {1} \ +CONFIG.S09_READ_ACCEPTANCE {1} \ +CONFIG.S10_READ_ACCEPTANCE {1} \ +CONFIG.S11_READ_ACCEPTANCE {1} \ +CONFIG.S12_READ_ACCEPTANCE {1} \ +CONFIG.S13_READ_ACCEPTANCE {1} \ +CONFIG.S14_READ_ACCEPTANCE {1} \ +CONFIG.S15_READ_ACCEPTANCE {1} \ +CONFIG.M00_WRITE_ISSUING {1} \ +CONFIG.M01_WRITE_ISSUING {1} \ +CONFIG.M02_WRITE_ISSUING {1} \ +CONFIG.M03_WRITE_ISSUING {1} \ +CONFIG.M04_WRITE_ISSUING {1} \ +CONFIG.M05_WRITE_ISSUING {1} \ +CONFIG.M06_WRITE_ISSUING {1} \ +CONFIG.M07_WRITE_ISSUING {1} \ +CONFIG.M08_WRITE_ISSUING {1} \ +CONFIG.M09_WRITE_ISSUING {1} \ +CONFIG.M10_WRITE_ISSUING {1} \ +CONFIG.M11_WRITE_ISSUING {1} \ +CONFIG.M12_WRITE_ISSUING {1} \ +CONFIG.M13_WRITE_ISSUING {1} \ +CONFIG.M14_WRITE_ISSUING {1} \ +CONFIG.M15_WRITE_ISSUING {1} \ +CONFIG.M00_READ_ISSUING {1} \ +CONFIG.M01_READ_ISSUING {1} \ +CONFIG.M02_READ_ISSUING {1} \ +CONFIG.M03_READ_ISSUING {1} \ +CONFIG.M04_READ_ISSUING {1} \ +CONFIG.M05_READ_ISSUING {1} \ +CONFIG.M06_READ_ISSUING {1} \ +CONFIG.M07_READ_ISSUING {1} \ +CONFIG.M08_READ_ISSUING {1} \ +CONFIG.M09_READ_ISSUING {1} \ +CONFIG.M10_READ_ISSUING {1} \ +CONFIG.M11_READ_ISSUING {1} \ +CONFIG.M12_READ_ISSUING {1} \ +CONFIG.M13_READ_ISSUING {1} \ +CONFIG.M14_READ_ISSUING {1} \ +CONFIG.M15_READ_ISSUING {1} \ +CONFIG.S00_SINGLE_THREAD {1} \ +CONFIG.M00_A00_ADDR_WIDTH {16} \ +CONFIG.M01_A00_ADDR_WIDTH {16} \ +CONFIG.M02_A00_ADDR_WIDTH {16} \ +CONFIG.M00_A00_BASE_ADDR {0x0000000000000000}\ +CONFIG.M01_A00_BASE_ADDR {0x0000000000010000}\ +CONFIG.M02_A00_BASE_ADDR {0x0000000000020000}] [get_ips axi_crossbar_1] +set_property generate_synth_checkpoint false [get_files axi_crossbar_1.xci] +reset_target all [get_ips axi_crossbar_1] +generate_target all [get_ips axi_crossbar_1] + create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name axi_clock_converter_0 set_property -dict { CONFIG.PROTOCOL {AXI4LITE} diff --git a/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl b/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl index b608e72..46bc1c8 100644 --- a/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl +++ b/hw/projects/reference_switch_lite/hw/tcl/reference_switch_lite.tcl @@ -38,6 +38,7 @@ set project_constraints "${public_repo_dir}/common/constraints/${board_name}_gen set start_time [exec date +%s] set_param general.maxThreads 8 set_param synth.elaboration.rodinMoreOptions "rt::set_parameter max_loop_limit 200000" +set_param board.repoPaths $::env(BOARD_FILE_PATH) ##################################### # Design Parameters on NF_DATAPATH ##################################### @@ -54,16 +55,16 @@ set_property board_part ${board} [current_project] set_property source_mgmt_mode DisplayOnly [current_project] set_property top ${top} [current_fileset] if {[string match $board_name "au280"]} { - set_property verilog_define { {BOARD_AU280} {au280} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU280} {au280} {__au280__} {__synthesis__} } [current_fileset] set board_param "AU280" } elseif {[string match $board_name "au250"]} { - set_property verilog_define { {BOARD_AU250} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU250} {__au250__} {__synthesis__} } [current_fileset] set board_param "AU250" } elseif {[string match $board_name "au200"]} { - set_property verilog_define { {BOARD_AU200} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_AU200} {__au200__} {__synthesis__} } [current_fileset] set board_param "AU200" } elseif {[string match $board_name "vcu1525"]} { - set_property verilog_define { {BOARD_VCU1525} {__synthesis__} } [current_fileset] + set_property verilog_define { {BOARD_VCU1525} {__au200__} {__synthesis__} } [current_fileset] set board_param "VCU1525" } set_property generic "C_NF_DATA_WIDTH=${datapath_width_bit} BOARD=\"${board_param}\"" [current_fileset] @@ -226,6 +227,87 @@ set_property generate_synth_checkpoint false [get_files axi_crossbar_0.xci] reset_target all [get_ips axi_crossbar_0] generate_target all [get_ips axi_crossbar_0] +create_ip -name axi_crossbar -vendor xilinx.com -library ip -module_name axi_crossbar_1 +set_property -dict [list \ +CONFIG.NUM_MI {3} \ +CONFIG.PROTOCOL {AXI4LITE} \ +CONFIG.CONNECTIVITY_MODE {SASD} \ +CONFIG.R_REGISTER {1} \ +CONFIG.S00_WRITE_ACCEPTANCE {1} \ +CONFIG.S01_WRITE_ACCEPTANCE {1} \ +CONFIG.S02_WRITE_ACCEPTANCE {1} \ +CONFIG.S03_WRITE_ACCEPTANCE {1} \ +CONFIG.S04_WRITE_ACCEPTANCE {1} \ +CONFIG.S05_WRITE_ACCEPTANCE {1} \ +CONFIG.S06_WRITE_ACCEPTANCE {1} \ +CONFIG.S07_WRITE_ACCEPTANCE {1} \ +CONFIG.S08_WRITE_ACCEPTANCE {1} \ +CONFIG.S09_WRITE_ACCEPTANCE {1} \ +CONFIG.S10_WRITE_ACCEPTANCE {1} \ +CONFIG.S11_WRITE_ACCEPTANCE {1} \ +CONFIG.S12_WRITE_ACCEPTANCE {1} \ +CONFIG.S13_WRITE_ACCEPTANCE {1} \ +CONFIG.S14_WRITE_ACCEPTANCE {1} \ +CONFIG.S15_WRITE_ACCEPTANCE {1} \ +CONFIG.S00_READ_ACCEPTANCE {1} \ +CONFIG.S01_READ_ACCEPTANCE {1} \ +CONFIG.S02_READ_ACCEPTANCE {1} \ +CONFIG.S03_READ_ACCEPTANCE {1} \ +CONFIG.S04_READ_ACCEPTANCE {1} \ +CONFIG.S05_READ_ACCEPTANCE {1} \ +CONFIG.S06_READ_ACCEPTANCE {1} \ +CONFIG.S07_READ_ACCEPTANCE {1} \ +CONFIG.S08_READ_ACCEPTANCE {1} \ +CONFIG.S09_READ_ACCEPTANCE {1} \ +CONFIG.S10_READ_ACCEPTANCE {1} \ +CONFIG.S11_READ_ACCEPTANCE {1} \ +CONFIG.S12_READ_ACCEPTANCE {1} \ +CONFIG.S13_READ_ACCEPTANCE {1} \ +CONFIG.S14_READ_ACCEPTANCE {1} \ +CONFIG.S15_READ_ACCEPTANCE {1} \ +CONFIG.M00_WRITE_ISSUING {1} \ +CONFIG.M01_WRITE_ISSUING {1} \ +CONFIG.M02_WRITE_ISSUING {1} \ +CONFIG.M03_WRITE_ISSUING {1} \ +CONFIG.M04_WRITE_ISSUING {1} \ +CONFIG.M05_WRITE_ISSUING {1} \ +CONFIG.M06_WRITE_ISSUING {1} \ +CONFIG.M07_WRITE_ISSUING {1} \ +CONFIG.M08_WRITE_ISSUING {1} \ +CONFIG.M09_WRITE_ISSUING {1} \ +CONFIG.M10_WRITE_ISSUING {1} \ +CONFIG.M11_WRITE_ISSUING {1} \ +CONFIG.M12_WRITE_ISSUING {1} \ +CONFIG.M13_WRITE_ISSUING {1} \ +CONFIG.M14_WRITE_ISSUING {1} \ +CONFIG.M15_WRITE_ISSUING {1} \ +CONFIG.M00_READ_ISSUING {1} \ +CONFIG.M01_READ_ISSUING {1} \ +CONFIG.M02_READ_ISSUING {1} \ +CONFIG.M03_READ_ISSUING {1} \ +CONFIG.M04_READ_ISSUING {1} \ +CONFIG.M05_READ_ISSUING {1} \ +CONFIG.M06_READ_ISSUING {1} \ +CONFIG.M07_READ_ISSUING {1} \ +CONFIG.M08_READ_ISSUING {1} \ +CONFIG.M09_READ_ISSUING {1} \ +CONFIG.M10_READ_ISSUING {1} \ +CONFIG.M11_READ_ISSUING {1} \ +CONFIG.M12_READ_ISSUING {1} \ +CONFIG.M13_READ_ISSUING {1} \ +CONFIG.M14_READ_ISSUING {1} \ +CONFIG.M15_READ_ISSUING {1} \ +CONFIG.S00_SINGLE_THREAD {1} \ +CONFIG.M00_A00_ADDR_WIDTH {16} \ +CONFIG.M01_A00_ADDR_WIDTH {16} \ +CONFIG.M02_A00_ADDR_WIDTH {16} \ +CONFIG.M00_A00_BASE_ADDR {0x0000000000000000}\ +CONFIG.M01_A00_BASE_ADDR {0x0000000000010000}\ +CONFIG.M02_A00_BASE_ADDR {0x0000000000020000}] [get_ips axi_crossbar_1] +set_property generate_synth_checkpoint false [get_files axi_crossbar_1.xci] +reset_target all [get_ips axi_crossbar_1] +generate_target all [get_ips axi_crossbar_1] + create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name axi_clock_converter_0 set_property -dict { CONFIG.PROTOCOL {AXI4LITE} diff --git a/sw/driver/opennic-driver.patch b/sw/driver/opennic-driver.patch index d86d81a..9ecf90e 100644 --- a/sw/driver/opennic-driver.patch +++ b/sw/driver/opennic-driver.patch @@ -34,26 +34,41 @@ diff -uprN ./onic_hardware.h ./onic_hardware.h struct onic_qdma_h2c_param { diff -uprN ./onic_main.c ./onic_main.c ---- ./onic_main.c 2020-10-10 22:22:57.000000000 +0900 -+++ ./onic_main.c 2021-02-02 14:52:46.000000000 +0900 -@@ -187,7 +187,9 @@ - strlcpy(netdev->name, dev_name, sizeof(netdev->name)); +--- ./onic_main.c 2023-12-07 12:27:36.237535443 +0000 ++++ ./onic_main.c 2023-12-07 12:33:38.980629056 +0000 +@@ -22,6 +22,7 @@ + #include + #include + #include ++#include - memset(&saddr, 0, sizeof(struct sockaddr)); - memcpy(saddr.sa_data, onic_default_dev_addr, 6); + #include "onic.h" + #include "onic_hardware.h" +@@ -129,6 +130,9 @@ static const struct net_device_ops onic_ + .ndo_start_xmit = onic_xmit_frame, + .ndo_set_mac_address = onic_set_mac_address, + .ndo_do_ioctl = onic_do_ioctl, ++#if LINUX_VERSION_CODE >= KERNEL_VERSION(5,6,0) ++ .ndo_siocdevprivate = onic_siocdevprivate, ++#endif + .ndo_change_mtu = onic_change_mtu, + .ndo_get_stats64 = onic_get_stats64, + }; +@@ -203,7 +207,9 @@ static int onic_probe(struct pci_dev *pd + + memset(&saddr, 0, sizeof(struct sockaddr)); + memcpy(saddr.sa_data, onic_default_dev_addr, 6); - get_random_bytes(saddr.sa_data + 3, 3); + saddr.sa_data[3] = pdev->bus->number; + saddr.sa_data[4] = PCI_SLOT(pdev->devfn); + saddr.sa_data[5] = PCI_FUNC(pdev->devfn); - onic_set_mac_address(netdev, (void *)&saddr); + onic_set_mac_address(netdev, (void *)&saddr); -diff -uprN ./onic_main.c ./onic_main.c ---- ./onic_main.c 2020-10-10 22:22:57.000000000 +0900 -+++ ./onic_main.c 2021-02-02 14:52:46.000000000 +0900 -@@ -223,6 +223,15 @@ static int onic_probe(struct pci_dev *pd + priv = netdev_priv(netdev); +@@ -241,6 +247,15 @@ static int onic_probe(struct pci_dev *pd netif_set_real_num_tx_queues(netdev, priv->num_tx_queues); netif_set_real_num_rx_queues(netdev, priv->num_rx_queues); - + +#ifdef NF_IOCTL + rv = onic_create_nfdp_dev(&priv->hw.nfdp_handle, priv->pdev); + if (rv < 0) { @@ -66,16 +81,17 @@ diff -uprN ./onic_main.c ./onic_main.c rv = register_netdev(netdev); if (rv < 0) { dev_err(&pdev->dev, "register_netdev, err = %d", rv); + diff -uprN ./onic_netdev.c ./onic_netdev.c ---- ./onic_netdev.c 2020-10-10 22:22:57.000000000 +0900 -+++ ./onic_netdev.c 2021-02-02 14:52:46.000000000 +0900 -@@ -24,6 +24,97 @@ +--- ./onic_netdev.c 2023-12-07 12:27:48.485237886 +0000 ++++ ./onic_netdev.c 2023-12-07 12:33:03.369510418 +0000 +@@ -25,6 +25,97 @@ #define ONIC_RX_DESC_STEP 256 +#ifdef NF_IOCTL +#define NFDP_OFFSET 0x0000 -+#define NFDP_END 0x70000 ++#define NFDP_END 0x400000 +#define NFDP_MAXLEN NFDP_END - NFDP_OFFSET + +#define NFDP_IOCTL_CMD_WRITE_REG (SIOCDEVPRIVATE+1) @@ -167,7 +183,7 @@ diff -uprN ./onic_netdev.c ./onic_netdev.c inline static u16 onic_ring_get_real_count(struct onic_ring *ring) { /* Valid writeback entry means one less count of descriptor entries */ -@@ -609,6 +700,34 @@ netdev_tx_t onic_xmit_frame(struct sk_bu +@@ -742,6 +833,34 @@ netdev_tx_t onic_xmit_frame(struct sk_bu return NETDEV_TX_OK; } @@ -199,13 +215,16 @@ diff -uprN ./onic_netdev.c ./onic_netdev.c +} +#endif /*NF_IOCTl*/ + - int onic_set_mac_address(struct net_device *dev, void *addr) - { - u8 *dev_addr = (u8 *)addr; -@@ -622,6 +741,50 @@ int onic_set_mac_address(struct net_devi - - int onic_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) - { + int onic_set_mac_address(struct net_device *dev, void *addr) + { + struct sockaddr *saddr = addr; +@@ -756,11 +875,61 @@ int onic_set_mac_address(struct net_devi + return 0; + } + +-int onic_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++int nf_onic_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) + { +#ifdef NF_IOCTL + struct onic_private *priv = netdev_priv(dev); + struct nfdp_dev *nfdev = onic_get_nfdp_dev(priv->hw.nfdp_handle); @@ -229,11 +248,6 @@ diff -uprN ./onic_netdev.c ./onic_netdev.c + err = -EFAULT; + break; + } -+ //err = ioctl_write_reg(nfdev, &sifr); -+ //if (err != 0) { -+ // err = -EFAULT; -+ // break; -+ //} + err = ioctl_read_reg(nfdev, &sifr); + if (err != 0) { + err = -EFAULT; @@ -250,21 +264,42 @@ diff -uprN ./onic_netdev.c ./onic_netdev.c + break; + } +#endif /*NF_IOCTL*/ - return 0; - } + return 0; + } + ++int onic_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) ++{ ++ return nf_onic_do_ioctl(dev, ifr, cmd); ++} ++ ++int onic_siocdevprivate(struct net_device *dev, struct ifreq *ifr, ++ void *data, int cmd) ++{ ++ return nf_onic_do_ioctl(dev, ifr, cmd); ++} ++ + int onic_change_mtu(struct net_device *dev, int mtu) + { + netdev_info(dev, "Requested MTU = %d", mtu); diff -uprN ./onic_netdev.h ./onic_netdev.h ---- ./onic_netdev.h 2020-10-10 22:22:57.000000000 +0900 -+++ ./onic_netdev.h 2021-02-02 14:52:46.000000000 +0900 -@@ -49,4 +49,27 @@ void onic_get_stats64(struct net_device +--- ./onic_netdev.h 2023-12-07 12:27:36.237535443 +0000 ++++ ./onic_netdev.h 2023-12-07 12:35:34.613759583 +0000 +@@ -43,10 +43,32 @@ int onic_set_mac_address(struct net_devi - int onic_poll(struct napi_struct *napi, int budget); + int onic_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); + ++int onic_siocdevprivate(struct net_device *dev, struct ifreq *ifr, void *data, int cmd); ++ + int onic_change_mtu(struct net_device *dev, int mtu); + + void onic_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats); + + int onic_poll(struct napi_struct *napi, int budget); + +#define NF_IOCTL +#ifdef NF_IOCTL -+//#ifndef __NF_IOCTL__ -+//#define __NF_IOCTL__ + +struct nfdp_dev { + struct pci_dev *pdev; @@ -280,19 +315,6 @@ diff -uprN ./onic_netdev.h ./onic_netdev.h +int onic_create_nfdp_dev(unsigned long *handle, struct pci_dev *pdev); + +void onic_destroy_nfdp_dev(unsigned long handle); -+//#endif /*__NF_IOCTL__ */ +#endif /* NF_IOCTL */ + #endif -diff -uprN ./onic_register.h ./onic_register.h ---- ./onic_register.h 2020-10-10 22:22:57.000000000 +0900 -+++ ./onic_register.h 2021-02-02 14:52:46.000000000 +0900 -@@ -30,7 +30,7 @@ static inline void onic_write_reg(struct - } - - #define SHELL_START 0x0 --#define SHELL_END 0x10000 -+#define SHELL_END 0x40000 - #define SHELL_MAXLEN (SHELL_END - SHELL_START) - - /***** system config registers *****/ diff --git a/tools/settings.sh b/tools/settings.sh index 42daf15..a852b42 100644 --- a/tools/settings.sh +++ b/tools/settings.sh @@ -29,7 +29,7 @@ export NF_PROJECT_NAME=reference_switch export PYTHON_BNRY=/usr/bin/python3 ### Don't change -export VERSION=2020.2 +export VERSION=2023.2 export PROJECTS=${NFPLUS_FOLDER}/projects export CONTRIB_PROJECTS=${NFPLUS_FOLDER}/contrib-projects export NF_DESIGN_DIR=${NFPLUS_FOLDER}/hw/projects/${NF_PROJECT_NAME} @@ -37,6 +37,7 @@ export NF_WORK_DIR=/tmp/${USER} export PYTHONPATH=.:${NFPLUS_FOLDER}/tools/scripts/:${NF_DESIGN_DIR}/lib/Python:${NFPLUS_FOLDER}/tools/scripts/NFTest export DRIVER_FOLDER=${NFPLUS_FOLDER}/lib/sw/std/driver/${DRIVER_NAME} export APPS_FOLDER=${NFPLUS_FOLDER}/lib/sw/std/apps/${DRIVER_NAME} +export BOARD_FILE_PATH=${NFPLUS_FOLDER}/hw/lib/xilinx/xilinx_shell_v1_0_0/open-nic-shell/board_files # Check sequence