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NetFPGA 10G Production Test
The Production Test validates a NetFPGA-10G board by simultaneously exercising all board level interfaces (with the exception of RLDRAM) and checking for errors. The Production Test also reports the current test status via PCIe or UART to the host computer. Due to licensing issues the project comes only with a pre-built bitstream and associated test software.
A Manual providing instructions to run the Production Test is available here. It is advised that you run both the Production Test and the separate RLDRAM test to validate your board before attempting any development. As described in the manual, if the results of either test indicate a problem with your board, you should return it to HiTech Global (HTG) immediately.
This document describes how the Production Test verifies the NetFPGA-10G on-board systems. The subsections which follow provide detailed descriptions of each of the main components of the Production Test, namely:
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QDRII memory interface test
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10G SFP+/PHY interface test
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Expansion (Samtec) Interface
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Clock & power test
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CPLD test
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Flash test
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PCIe test
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UART test
This test exercises the SRAM interface with 100% utilization @ 250MHz. The test writes and reads every memory location in bursts of 4 with data values. The data values are comprised of 9-bit counters. The test result is fed out over UART, PCIe and LED.
This test sends and receives packets at close to 100% line rate in loopback mode. Interfaces need to be wired A-B and C-D with direct attach cables as described in the Production Test Manual. The test generates packets at line rate for each XAUI transmit interface and implements a checker on each XAUI receive interface. The test design logs tx and rx counts and rx error counts, verifies PMA, PCS and XAUI link status. Only if all results are as expected does the test pass. Output is reported via UART, PCIe and LED.
To test the Samtec interfaces, we have implemented an Aurora testbench which generates packets at 6.25Gbps line rate per GTX, transmits them over the loopback cable, and receives and checks them.
This test simply checks that the clock frequencies (100MHz, 25MHz, Super clock) are within range and checks the power ok signals from the DC2DCs. Results are reported over UART, PCIe and LED.
This test shifts a ‘1’ across the wide CPLD-FPGA interface and checks its results continuously. Results are reported over UART, PCIe and LED.
The CPLD is continuously reading back device information from the platform flash devices. While these values are returned as expected, the test passes. Results are passed to the FPGA and from there reported over UART, PCIe and LED.
This test can only be conducted in server mode. The host CPU issues data transfers to and from the board over the PCIe and checks the returned values. The result of this test can only be seen on the output of the Production Test software executed on the host PC, as described in the Server Mode section of the Production Test Manual.
In Standalone Mode, the UART interface is a debug output used for the Production Test report itself. In Server Mode, the host issues a message to the board via UART and checks the returned answer is as expected.
The production test aims to test the board as thoroughly as possible. However there are certain parts of the design which cannot currently be tested:
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The operation of the 10G interfaces are verified with SFP+ direct attach cables.
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Some of the clock inputs to the GTXs cannot be verified through this production test.
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SRAM is verified up to 250MHz.
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Samtec interface is verified up to 6.25Gbps.
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Configuration from flash and programming to flash is currently not supported within the production test.