Project Tracking

Name	Description	Owner	Target Release	Status
Updated Testbenches/Unit tests	Unified and general testbenches for projects and pcores	Neels	TBD
DRAM streaming interface	AXI stream to RLDRAM II for queuing	TBD
Generic Regs and Tables in HW	demonstrates regsiter and table access using generic implementation	M.Shahbaz	31 November '12
IPv4 Router	reference implementation of IPv4 router	G. Antichi / M.Shahbaz	31 November '12
DRAM memory-mapped interface	AXI4 to RLDRAM II for data/instruction memory	M.Shahbaz	31 November '12
NetFPGA-10G patch for XAPP852	RLDRAM II regression testing	M.Shahbaz	31 November '12
Learning CAM switch	Native implementation	G. Antichi / M.Shahbaz	15 September '12	Released
Simple switch	Native 10G implementation	Michaela Blott	15 September '12	Released
SRAM Output Queues	AXI stream to SRAM for queuing	Sam D'Amico	23 July '12	Released
OpenFlow	1.0 running at 10G	Tatsuya Yabe	23 July '12	Released
Register System	EDK based automated system for generating header/code files	M.Shahbaz	23 July '12	Released
1G to 10G wrapper	Converts 1G modules to 10G AXI interface	M.Shahbaz / G. Antichi	8 May '12	Released
DMA v2.0	Small and quick DMA	Mario Flajslik	8 May '12	Released
Fast Flash IO	High speed flash read(s)/write(s) using DMA v2.0	M. Shahbaz	8 May '12	Released