From 9e74a918872c8ed8ae346a08066e6dcb24b5806f Mon Sep 17 00:00:00 2001 From: cpchiang Date: Mon, 20 May 2024 23:40:09 -0700 Subject: [PATCH] dts: arm: npcm4xx: update clock control setting update clock control setting. Signed-off-by: cpchiang --- dts/arm/nuvoton/npcm400f.dtsi | 2 +- soc/arm/npcm4xx/common/soc_clock.h | 12 ------------ 2 files changed, 1 insertion(+), 13 deletions(-) diff --git a/dts/arm/nuvoton/npcm400f.dtsi b/dts/arm/nuvoton/npcm400f.dtsi index 79221847954daf..49b08315c1b986 100644 --- a/dts/arm/nuvoton/npcm400f.dtsi +++ b/dts/arm/nuvoton/npcm400f.dtsi @@ -15,7 +15,7 @@ pcc: clock-controller@4000d000 { clock-frequency = ; /* OFMCLK runs at 96MHz */ core-prescaler = <1>; /* CORE_CLK runs at 96MHz */ - apb1-prescaler = <1>; /* APB1_CLK runs at 96MHz */ + apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */ apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */ apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */ }; diff --git a/soc/arm/npcm4xx/common/soc_clock.h b/soc/arm/npcm4xx/common/soc_clock.h index f34724926b1b39..affac5e935fd1d 100644 --- a/soc/arm/npcm4xx/common/soc_clock.h +++ b/soc/arm/npcm4xx/common/soc_clock.h @@ -58,27 +58,15 @@ struct npcm4xx_clk_cfg { #define LFCLK 32768 /* FMUL clock */ -//#if (OFMCLK > 50000000) -//#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 if OFMCLK > 50MHz */ -//#else #define FMCLK OFMCLK /* FMUL clock = OFMCLK */ -//#endif /* APBs source clock */ #define APBSRC_CLK OFMCLK /* AHB6 clock */ -//#if (CORE_CLK > 50000000) -//#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 if CORE_CLK > 50MHz */ -//#else #define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */ -//#endif /* FIU clock divider */ -#if (CORE_CLK > 50000000) -#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */ -#else #define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */ -#endif /* Get APB clock freq */ #define NPCM4XX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))