From c11b26d68a17f52075743dd0ffc1ae16d96ec5f7 Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 23 Aug 2023 19:55:40 -0700 Subject: [PATCH] drivers: spip: add npcm4xx spip driver to support spi flash access add npcm4xx spip driver to support spi flash access. only support single mode read/write spi command. increase main stack size to 4096 to match openbic reference platform. Signed-off-by: cpchiang --- boards/arm/npcm400f_evb/fun_def_list.h | 6 +- boards/arm/npcm400f_evb/npcm400f_evb.dts | 2 +- .../arm/npcm400f_evb/npcm400f_evb_defconfig | 2 +- drivers/spi/spi_npcm4xx_spip.c | 270 ++++++++++++++---- dts/arm/nuvoton/npcm400f.dtsi | 11 - dts/arm/nuvoton/npcm4xx.dtsi | 24 ++ dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi | 4 +- dts/bindings/spi/nuvoton,npcm4xx-spip.yaml | 14 + soc/arm/npcm4xx/common/reg/reg_def.h | 131 +++++---- soc/arm/npcm4xx/npcm400f/sig_def_list.h | 14 +- 10 files changed, 332 insertions(+), 146 deletions(-) diff --git a/boards/arm/npcm400f_evb/fun_def_list.h b/boards/arm/npcm400f_evb/fun_def_list.h index cfebca939e206d..4718d000d5a708 100644 --- a/boards/arm/npcm400f_evb/fun_def_list.h +++ b/boards/arm/npcm400f_evb/fun_def_list.h @@ -67,9 +67,9 @@ FUN_DEFINE(DT_NODELABEL(pinctrl_td4p_default), TD4P) FUN_DEFINE(DT_NODELABEL(pinctrl_vin3_default), VIN3) #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip), okay) && CONFIG_SPIP_NPCM4XX -FUN_DEFINE(DT_NODELABEL(pinctrl_spip_default), SPIP_CS, SPIP_SCLK, SPIP_DIO0, SPIP_DIO1) -FUN_DEFINE(DT_NODELABEL(pinctrl_spip_quad), SPIP_DIO2, SPIP_DIO3) +#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip1), okay) && CONFIG_SPIP_NPCM4XX +FUN_DEFINE(DT_NODELABEL(pinctrl_spip1_default), SPIP1_CS, SPIP1_SCLK, SPIP1_DIO0, SPIP1_DIO1) +FUN_DEFINE(DT_NODELABEL(pinctrl_spip1_quad), SPIP1_DIO2, SPIP1_DIO3) #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c0), okay) && CONFIG_I3C_NPCM4XX diff --git a/boards/arm/npcm400f_evb/npcm400f_evb.dts b/boards/arm/npcm400f_evb/npcm400f_evb.dts index 3b9fcb0faf5eb0..0fb11dfbaf01c9 100644 --- a/boards/arm/npcm400f_evb/npcm400f_evb.dts +++ b/boards/arm/npcm400f_evb/npcm400f_evb.dts @@ -170,7 +170,7 @@ &pinctrl_vin3_default>; /* VIN3 - D6 */ }; -&spip { +&spip1 { status = "okay"; }; diff --git a/boards/arm/npcm400f_evb/npcm400f_evb_defconfig b/boards/arm/npcm400f_evb/npcm400f_evb_defconfig index e350f001cb7246..8315b1adc6f5db 100644 --- a/boards/arm/npcm400f_evb/npcm400f_evb_defconfig +++ b/boards/arm/npcm400f_evb/npcm400f_evb_defconfig @@ -14,7 +14,7 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000 CONFIG_XIP=y CONFIG_STACK_SENTINEL=y # [main stack size default: 1024] -CONFIG_MAIN_STACK_SIZE=2048 +CONFIG_MAIN_STACK_SIZE=4096 CONFIG_NO_OPTIMIZATIONS=y CONFIG_HEAP_MEM_POOL_SIZE=16384 diff --git a/drivers/spi/spi_npcm4xx_spip.c b/drivers/spi/spi_npcm4xx_spip.c index 3bafa3680a97e0..effae81708e73c 100644 --- a/drivers/spi/spi_npcm4xx_spip.c +++ b/drivers/spi/spi_npcm4xx_spip.c @@ -25,34 +25,41 @@ struct npcm4xx_spip_config { struct npcm4xx_spip_data { struct spi_context ctx; uint32_t apb3; + /* read/write init flags */ + int rw_init; + /* read command data */ + struct spi_nor_op_info read_op_info; + /* write command data */ + struct spi_nor_op_info write_op_info; }; +/* Driver convenience defines */ +#define HAL_INSTANCE(dev) \ + ((struct spip_reg *)((const struct npcm4xx_spip_config *)(dev)->config)->base) + static void SPI_SET_SS0_HIGH(const struct device *dev) { - const struct npcm4xx_spip_config *cfg = dev->config; - struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + struct spip_reg *const inst = HAL_INSTANCE(dev); - spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); - spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SSACTPOL); - spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SS); + inst->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); + inst->SSCTL |= BIT(NPCM4XX_SSCTL_SSACTPOL); + inst->SSCTL |= BIT(NPCM4XX_SSCTL_SS); } static void SPI_SET_SS0_LOW(const struct device *dev) { - const struct npcm4xx_spip_config *cfg = dev->config; - struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + struct spip_reg *const inst = HAL_INSTANCE(dev); - spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); - spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_SSACTPOL); - spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SS); + inst->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); + inst->SSCTL &= ~BIT(NPCM4XX_SSCTL_SSACTPOL); + inst->SSCTL |= BIT(NPCM4XX_SSCTL_SS); } static int spip_npcm4xx_configure(const struct device *dev, const struct spi_config *config) { - const struct npcm4xx_spip_config *cfg = dev->config; struct npcm4xx_spip_data *data = dev->data; - struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + struct spip_reg *const inst = HAL_INSTANCE(dev); uint32_t u32Div = 0; int ret = 0; @@ -60,34 +67,34 @@ static int spip_npcm4xx_configure(const struct device *dev, LOG_ERR("Word sizes other than 8 bits are not supported"); ret = -ENOTSUP; } else { - spip_regs->CTL &= ~(0x1F << NPCM4XX_CTL_DWIDTH); - spip_regs->CTL |= (SPI_WORD_SIZE_GET(config->operation) << NPCM4XX_CTL_DWIDTH); + inst->CTL &= ~(0x1F << NPCM4XX_CTL_DWIDTH); + inst->CTL |= (SPI_WORD_SIZE_GET(config->operation) << NPCM4XX_CTL_DWIDTH); } if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) { - spip_regs->CTL |= BIT(NPCM4XX_CTL_CLKPOL); + inst->CTL |= BIT(NPCM4XX_CTL_CLKPOL); if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) { - spip_regs->CTL &= ~BIT(NPCM4XX_CTL_TXNEG); - spip_regs->CTL &= ~BIT(NPCM4XX_CTL_RXNEG); + inst->CTL &= ~BIT(NPCM4XX_CTL_TXNEG); + inst->CTL &= ~BIT(NPCM4XX_CTL_RXNEG); } else { - spip_regs->CTL |= BIT(NPCM4XX_CTL_TXNEG); - spip_regs->CTL |= BIT(NPCM4XX_CTL_RXNEG); + inst->CTL |= BIT(NPCM4XX_CTL_TXNEG); + inst->CTL |= BIT(NPCM4XX_CTL_RXNEG); } } else { - spip_regs->CTL &= ~BIT(NPCM4XX_CTL_CLKPOL); + inst->CTL &= ~BIT(NPCM4XX_CTL_CLKPOL); } if (config->operation & SPI_TRANSFER_LSB) { - spip_regs->CTL |= BIT(NPCM4XX_CTL_LSB); + inst->CTL |= BIT(NPCM4XX_CTL_LSB); } else { - spip_regs->CTL &= ~BIT(NPCM4XX_CTL_LSB); + inst->CTL &= ~BIT(NPCM4XX_CTL_LSB); } if (config->operation & SPI_OP_MODE_SLAVE) { LOG_ERR("Slave mode is not supported"); ret = -ENOTSUP; } else { - spip_regs->CTL &= ~BIT(NPCM4XX_CTL_SLAVE); + inst->CTL &= ~BIT(NPCM4XX_CTL_SLAVE); } /* Set Bus clock */ @@ -103,10 +110,10 @@ static int spip_npcm4xx_configure(const struct device *dev, } } - spip_regs->CLKDIV = (spip_regs->CLKDIV & ~0xFF) | u32Div; + inst->CLKDIV = (inst->CLKDIV & ~0xFF) | u32Div; /* spip enable */ - spip_regs->CTL |= BIT(NPCM4XX_CTL_SPIEN); + inst->CTL |= BIT(NPCM4XX_CTL_SPIEN); return ret; } @@ -116,65 +123,65 @@ static int spip_npcm4xx_transceive(const struct device *dev, const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs) { - const struct npcm4xx_spip_config *cfg = dev->config; + struct spip_reg *const inst = HAL_INSTANCE(dev); struct npcm4xx_spip_data *data = dev->data; - struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + struct spi_context *ctx = &data->ctx; + int ret = 0, error = 0; + uint8_t tx_done = 0; - spi_context_lock(&data->ctx, false, NULL, config); - data->ctx.config = config; + spi_context_lock(ctx, false, NULL, config); + ctx->config = config; - int ret, error = 0; - uint8_t txDone; /* Configure */ ret = spip_npcm4xx_configure(dev, config); if (ret) { - return -ENOTSUP; + ret = -ENOTSUP; + goto spip_transceive_done; } - ret = 0; - spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); + spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1); if (config->operation & SPI_OP_MODE_SLAVE) { /* Slave */ LOG_ERR("Slave mode is not supported"); ret = -ENOTSUP; + goto spip_transceive_done; } else { /* Master */ SPI_SET_SS0_LOW(dev); if (rx_bufs == NULL) { /* write data to SPI flash */ - while (spi_context_tx_buf_on(&data->ctx)) { + while (spi_context_tx_buf_on(ctx)) { /*TX*/ - if ((spip_regs->STATUS & BIT(NPCM4XX_STATUS_TXFULL)) == 0) { - spip_regs->TX = *data->ctx.tx_buf; - spi_context_update_tx(&data->ctx, 1, 1); + if ((inst->STATUS & BIT(NPCM4XX_STATUS_TXFULL)) == 0) { + inst->TX = (uint8_t)*ctx->tx_buf; + spi_context_update_tx(ctx, 1, 1); } } - } else { - txDone = 0; - spip_regs->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + } else { + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); while (1) { /*TX*/ - if (spi_context_tx_buf_on(&data->ctx)) { - if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_TXFULL))) { - spip_regs->TX = *data->ctx.tx_buf; - spi_context_update_tx(&data->ctx, 1, 1); + if (spi_context_tx_buf_on(ctx)) { + if (!(inst->STATUS & BIT(NPCM4XX_STATUS_TXFULL))) { + inst->TX = (uint8_t)*ctx->tx_buf; + spi_context_update_tx(ctx, 1, 1); } - } else if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_BUSY))) { - txDone = 1; + } else if (!(inst->STATUS & BIT(NPCM4XX_STATUS_BUSY))) { + tx_done = 1; } /*RX*/ - if (spi_context_rx_buf_on(&data->ctx)) { - if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_RXEMPTY))) { - *data->ctx.rx_buf = spip_regs->RX; - spi_context_update_rx(&data->ctx, 1, 1); - } else if (txDone == 1) { + if (spi_context_rx_buf_on(ctx)) { + if (!(inst->STATUS & BIT(NPCM4XX_STATUS_RXEMPTY))) { + *ctx->rx_buf = (uint8_t)inst->RX; + spi_context_update_rx(ctx, 1, 1); + } else if (tx_done == 1) { ret = -EOVERFLOW; break; } } else { - if (txDone == 1) { + if (tx_done == 1) { break; } } @@ -182,19 +189,21 @@ static int spip_npcm4xx_transceive(const struct device *dev, } do { - if ((spip_regs->STATUS & BIT(NPCM4XX_STATUS_BUSY)) == 0) { + if ((inst->STATUS & BIT(NPCM4XX_STATUS_BUSY)) == 0) { break; } } while (1); SPI_SET_SS0_HIGH(dev); } - spi_context_release(&data->ctx, error); - if (error != 0) { - ret = error; - } - return ret; +spip_transceive_done: + spi_context_release(ctx, error); + + if (ret) + return ret; + else + return error; } #ifdef CONFIG_SPI_ASYNC @@ -252,12 +261,155 @@ static int spip_npcm4xx_init(const struct device *dev) return 0; } +static inline void spi_npcm4xx_spip_write_data(const struct device *dev, uint32_t code) +{ + struct spip_reg *const inst = HAL_INSTANCE(dev); + + while ((inst->STATUS & BIT(NPCM4XX_STATUS_TXFULL))); + + inst->TX = code; + + while (inst->STATUS & BIT(NPCM4XX_STATUS_BUSY)); +} + +static void spi_nor_npcm4xx_spip_fifo_transceive(const struct device *dev, + const struct spi_config *spi_cfg, + struct spi_nor_op_info op_info) +{ + struct spip_reg *const inst = HAL_INSTANCE(dev); + struct spi_nor_op_info *normal_op_info = NULL; + uint32_t index = 0, dummy_write = 0; + uint8_t *buf_data = NULL; + uint8_t sub_addr = 0; + + normal_op_info = &op_info; + + /* clear tx/rx fifo buffer */ + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_TXRST); + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + + SPI_SET_SS0_LOW(dev); + + /* send command */ + spi_npcm4xx_spip_write_data(dev, (uint32_t)normal_op_info->opcode); + + /* send address */ + index = normal_op_info->addr_len; + while (index) { + index = index - 1; + sub_addr = (normal_op_info->addr >> (8 * index)) & 0xff; + spi_npcm4xx_spip_write_data(dev, (uint32_t)sub_addr); + } + + /* only support single mode dummy byte */ + if ((normal_op_info->dummy_cycle % NPCM4XX_SPIP_SINGLE_DUMMY_BYTE) != 0) { + LOG_ERR("SPIP now only support single mode"); + return; + } + + /* send dummy bytes */ + for (index = 0; index < normal_op_info->dummy_cycle; + index += NPCM4XX_SPIP_SINGLE_DUMMY_BYTE) { + spi_npcm4xx_spip_write_data(dev, dummy_write); + } + + /* clear rx fifo buffer */ + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + + buf_data = normal_op_info->buf; + + if (buf_data == NULL) { + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + goto spi_nor_normal_done; + } + + /* read data from SPI flash */ + if (normal_op_info->data_direct == SPI_NOR_DATA_DIRECT_IN) { + for (index = 0; index < normal_op_info->data_len; index++) { + /* write dummy data out*/ + spi_npcm4xx_spip_write_data(dev, dummy_write); + /* wait received data */ + while((inst->STATUS & BIT(NPCM4XX_STATUS_RXEMPTY))); + + *(buf_data + index) = (uint8_t)inst->RX; + } + } else if (normal_op_info->data_direct == SPI_NOR_DATA_DIRECT_OUT) { + for (index = 0; index < normal_op_info->data_len; index++) { + /* write data to SPI flash */ + spi_npcm4xx_spip_write_data(dev, (uint32_t)*(buf_data + index)); + } + /* clear rx fifo buffer */ + inst->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + } + +spi_nor_normal_done: + + SPI_SET_SS0_HIGH(dev); +} + +static int spi_nor_npcm4xx_spip_transceive(const struct device *dev, + const struct spi_config *spi_cfg, + struct spi_nor_op_info op_info) +{ + struct npcm4xx_spip_data *data = dev->data; + struct spi_context *ctx = &data->ctx; + int ret = 0, error = 0; + + ret = spip_npcm4xx_configure(dev, spi_cfg); + if (ret) + return ret; + + spi_context_lock(ctx, false, NULL, spi_cfg); + ctx->config = spi_cfg; + + spi_nor_npcm4xx_spip_fifo_transceive(dev, spi_cfg, op_info); + + spi_context_release(ctx, error); + + return error; +} + +static int spi_nor_npcm4xx_spip_read_init(const struct device *dev, + const struct spi_config *spi_cfg, + struct spi_nor_op_info op_info) +{ + struct npcm4xx_spip_data *data = dev->data; + + /* record read command from jesd216 */ + memcpy(&data->read_op_info, &op_info, sizeof(op_info)); + + data->rw_init |= NPCM4XX_SPIP_SPI_NOR_READ_INIT_OK; + + return 0; +} + +static int spi_nor_npcm4xx_spip_write_init(const struct device *dev, + const struct spi_config *spi_cfg, + struct spi_nor_op_info op_info) +{ + struct npcm4xx_spip_data *data = dev->data; + + /* record read command from jesd216 */ + memcpy(&data->write_op_info, &op_info, sizeof(op_info)); + + data->rw_init |= NPCM4XX_SPIP_SPI_NOR_WRITE_INIT_OK; + + return 0; +} + +static const struct spi_nor_ops npcm4xx_spip_spi_nor_ops = { + .transceive = spi_nor_npcm4xx_spip_transceive, + .read_init = spi_nor_npcm4xx_spip_read_init, + .write_init = spi_nor_npcm4xx_spip_write_init, +}; + static const struct spi_driver_api spip_npcm4xx_driver_api = { .transceive = spip_npcm4xx_transceive, #ifdef CONFIG_SPI_ASYNC .transceive_async = spip_npcm4xx_transceive_async, #endif .release = spip_npcm4xx_release, + .spi_nor_op = &npcm4xx_spip_spi_nor_ops, }; diff --git a/dts/arm/nuvoton/npcm400f.dtsi b/dts/arm/nuvoton/npcm400f.dtsi index 7ab8dd37f855fd..972b620b31a608 100644 --- a/dts/arm/nuvoton/npcm400f.dtsi +++ b/dts/arm/nuvoton/npcm400f.dtsi @@ -159,17 +159,6 @@ label = "ADC_0"; }; - spip: spi@40016000 { - compatible = "nuvoton,npcm4xx-spip"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x40016000 0x100>; - clocks = <&pcc NPCM4XX_CLOCK_BUS_APB3 NPCM4XX_PWDWN_CTL4 7>; - pinctrl-0 = <&pinctrl_spip_default &pinctrl_spip_quad>; - label = "SPIP"; - status = "disabled"; - }; - i3c0: i3c0@40004000 { compatible = "nuvoton,npcm4xx-i3c"; instance-id = <0>; diff --git a/dts/arm/nuvoton/npcm4xx.dtsi b/dts/arm/nuvoton/npcm4xx.dtsi index 02ba2fd1ece04a..ef1a6754569efa 100644 --- a/dts/arm/nuvoton/npcm4xx.dtsi +++ b/dts/arm/nuvoton/npcm4xx.dtsi @@ -473,6 +473,30 @@ label = "SPI_FIU1"; status = "disabled"; }; + + spip1: spi@40016000 { + compatible = "nuvoton,npcm4xx-spip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40016000 0x100>; + clocks = <&pcc NPCM4XX_CLOCK_BUS_APB3 NPCM4XX_PWDWN_CTL4 7>; + spi-ctrl-caps-mask = <0x000f0f0c>; + pinctrl-0 = <&pinctrl_spip1_default &pinctrl_spip1_quad>; + label = "SPIP"; + status = "disabled"; + + spi_spip1_cs0: flash@0 { + compatible ="jedec,spi-nor"; + /* slave */ + reg = <0>; + spi-max-buswidth = <1>; + spi-max-frequency = <48000000>; + jedec-id = []; + label = "spi_spip1_cs0"; + status = "disabled"; + }; + }; + }; soc-if { diff --git a/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi b/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi index bedf041810cbac..6632dda22d0bad 100644 --- a/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi +++ b/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi @@ -33,8 +33,8 @@ pinctrl_thr2_default: thr2_default {}; pinctrl_td4p_default: td4p_default {}; pinctrl_vin3_default: vin3_default {}; - pinctrl_spip_default: spip_default{}; - pinctrl_spip_quad: spip_quad{}; + pinctrl_spip1_default: spip1_default{}; + pinctrl_spip1_quad: spip1_quad{}; pinctrl_i3c0_default: i3c0_default {}; pinctrl_i3c1_default: i3c1_default {}; pinctrl_usbd_phy_iclk: usbd_phy_iclk {}; diff --git a/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml b/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml index 276921dc6e4433..7483b0d9a53945 100644 --- a/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml +++ b/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml @@ -12,3 +12,17 @@ properties: required: true clocks: required: true + spi-ctrl-caps-mask: + type: int + required: false + description: | + SPI flash controller mode/protocol capability configuration. + + bit 0 : disable 1-1-1 + bit 1 : disable 1-1-1 (fast read) + bit 8 : disable 1-1-2 + bit 9 : disable 1-2-2 + bit 10: disable 2-2-2 + bit 16: disable 1-1-4 + bit 17: disable 1-4-4 + bit 18: disable 4-4-4 diff --git a/soc/arm/npcm4xx/common/reg/reg_def.h b/soc/arm/npcm4xx/common/reg/reg_def.h index 1485d2cf22d0bc..827dadb79fd420 100644 --- a/soc/arm/npcm4xx/common/reg/reg_def.h +++ b/soc/arm/npcm4xx/common/reg/reg_def.h @@ -537,82 +537,89 @@ struct spip_reg { /* SPIP register fields */ /* 0x00: SPI_CTL fields */ -#define NPCM4XX_CTL_QUADIOEN (22) -#define NPCM4XX_CTL_DUALIOEN (21) -#define NPCM4XX_CTL_QDIODIR (20) -#define NPCM4XX_CTL_REORDER (19) -#define NPCM4XX_CTL_SLAVE (18) -#define NPCM4XX_CTL_UNITIEN (17) -#define NPCM4XX_CTL_TWOBIT (16) -#define NPCM4XX_CTL_LSB (13) -#define NPCM4XX_CTL_DWIDTH (8) -#define NPCM4XX_CTL_SUSPITV (4) -#define NPCM4XX_CTL_CLKPOL (3) -#define NPCM4XX_CTL_TXNEG (2) -#define NPCM4XX_CTL_RXNEG (1) -#define NPCM4XX_CTL_SPIEN (0) +#define NPCM4XX_CTL_QUADIOEN (22) +#define NPCM4XX_CTL_DUALIOEN (21) +#define NPCM4XX_CTL_QDIODIR (20) +#define NPCM4XX_CTL_REORDER (19) +#define NPCM4XX_CTL_SLAVE (18) +#define NPCM4XX_CTL_UNITIEN (17) +#define NPCM4XX_CTL_TWOBIT (16) +#define NPCM4XX_CTL_LSB (13) +#define NPCM4XX_CTL_DWIDTH (8) +#define NPCM4XX_CTL_SUSPITV (4) +#define NPCM4XX_CTL_CLKPOL (3) +#define NPCM4XX_CTL_TXNEG (2) +#define NPCM4XX_CTL_RXNEG (1) +#define NPCM4XX_CTL_SPIEN (0) /* 0x04: SPI_CLKDIV fields */ -#define NPCM4XX_CLKDIV_DIVIDER (0) +#define NPCM4XX_CLKDIV_DIVIDER (0) /* 0x08: SPI_SSCTL fields */ -#define NPCM4XX_SSCTL_SLVTOCNT (16) -#define NPCM4XX_SSCTL_SSINAIEN (13) -#define NPCM4XX_SSCTL_SSACTIEN (12) -#define NPCM4XX_SSCTL_SLVURIEN (9) -#define NPCM4XX_SSCTL_SLVBEIEN (8) -#define NPCM4XX_SSCTL_SLVTORST (6) -#define NPCM4XX_SSCTL_SLVTOIEN (5) -#define NPCM4XX_SSCTL_SLV3WIRE (4) -#define NPCM4XX_SSCTL_AUTOSS (3) -#define NPCM4XX_SSCTL_SSACTPOL (2) -#define NPCM4XX_SSCTL_SS (0) +#define NPCM4XX_SSCTL_SLVTOCNT (16) +#define NPCM4XX_SSCTL_SSINAIEN (13) +#define NPCM4XX_SSCTL_SSACTIEN (12) +#define NPCM4XX_SSCTL_SLVURIEN (9) +#define NPCM4XX_SSCTL_SLVBEIEN (8) +#define NPCM4XX_SSCTL_SLVTORST (6) +#define NPCM4XX_SSCTL_SLVTOIEN (5) +#define NPCM4XX_SSCTL_SLV3WIRE (4) +#define NPCM4XX_SSCTL_AUTOSS (3) +#define NPCM4XX_SSCTL_SSACTPOL (2) +#define NPCM4XX_SSCTL_SS (0) /* 0x0C: SPI_PDMACTL fields */ -#define NPCM4XX_PDMACTL_PDMARST (2) -#define NPCM4XX_PDMACTL_RXPDMAEN (1) -#define NPCM4XX_PDMACTL_TXPDMAEN (0) +#define NPCM4XX_PDMACTL_PDMARST (2) +#define NPCM4XX_PDMACTL_RXPDMAEN (1) +#define NPCM4XX_PDMACTL_TXPDMAEN (0) /* 0x10: SPI_FIFOCTL fields */ -#define NPCM4XX_FIFOCTL_TXTH (28) -#define NPCM4XX_FIFOCTL_RXTH (24) -#define NPCM4XX_FIFOCTL_TXUFIEN (7) -#define NPCM4XX_FIFOCTL_TXUFPOL (6) -#define NPCM4XX_FIFOCTL_RXOVIEN (5) -#define NPCM4XX_FIFOCTL_RXTOIEN (4) -#define NPCM4XX_FIFOCTL_TXTHIEN (3) -#define NPCM4XX_FIFOCTL_RXTHIEN (2) -#define NPCM4XX_FIFOCTL_TXRST (1) -#define NPCM4XX_FIFOCTL_RXRST (0) +#define NPCM4XX_FIFOCTL_TXTH (28) +#define NPCM4XX_FIFOCTL_RXTH (24) +#define NPCM4XX_FIFOCTL_TXUFIEN (7) +#define NPCM4XX_FIFOCTL_TXUFPOL (6) +#define NPCM4XX_FIFOCTL_RXOVIEN (5) +#define NPCM4XX_FIFOCTL_RXTOIEN (4) +#define NPCM4XX_FIFOCTL_TXTHIEN (3) +#define NPCM4XX_FIFOCTL_RXTHIEN (2) +#define NPCM4XX_FIFOCTL_TXRST (1) +#define NPCM4XX_FIFOCTL_RXRST (0) /* 0x14: SPI_STATUS fields */ -#define NPCM4XX_STATUS_TXCNT (28) -#define NPCM4XX_STATUS_RXCNT (24) -#define NPCM4XX_STATUS_TXRXRST (23) -#define NPCM4XX_STATUS_TXUFIF (19) -#define NPCM4XX_STATUS_TXTHIF (18) -#define NPCM4XX_STATUS_TXFULL (17) -#define NPCM4XX_STATUS_TXEMPTY (16) -#define NPCM4XX_STATUS_SPIENSTS (15) -#define NPCM4XX_STATUS_RXTOIF (12) -#define NPCM4XX_STATUS_RXOVIF (11) -#define NPCM4XX_STATUS_RXTHIF (10) -#define NPCM4XX_STATUS_RXFULL (9) -#define NPCM4XX_STATUS_RXEMPTY (8) -#define NPCM4XX_STATUS_SLVUDRIF (7) -#define NPCM4XX_STATUS_SLVBEIF (6) -#define NPCM4XX_STATUS_SLVTOIF (5) -#define NPCM4XX_STATUS_SSLINE (4) -#define NPCM4XX_STATUS_SSINAIF (3) -#define NPCM4XX_STATUS_SSACTIF (2) -#define NPCM4XX_STATUS_UNITIF (1) -#define NPCM4XX_STATUS_BUSY (0) +#define NPCM4XX_STATUS_TXCNT (28) +#define NPCM4XX_STATUS_RXCNT (24) +#define NPCM4XX_STATUS_TXRXRST (23) +#define NPCM4XX_STATUS_TXUFIF (19) +#define NPCM4XX_STATUS_TXTHIF (18) +#define NPCM4XX_STATUS_TXFULL (17) +#define NPCM4XX_STATUS_TXEMPTY (16) +#define NPCM4XX_STATUS_SPIENSTS (15) +#define NPCM4XX_STATUS_RXTOIF (12) +#define NPCM4XX_STATUS_RXOVIF (11) +#define NPCM4XX_STATUS_RXTHIF (10) +#define NPCM4XX_STATUS_RXFULL (9) +#define NPCM4XX_STATUS_RXEMPTY (8) +#define NPCM4XX_STATUS_SLVUDRIF (7) +#define NPCM4XX_STATUS_SLVBEIF (6) +#define NPCM4XX_STATUS_SLVTOIF (5) +#define NPCM4XX_STATUS_SSLINE (4) +#define NPCM4XX_STATUS_SSINAIF (3) +#define NPCM4XX_STATUS_SSACTIF (2) +#define NPCM4XX_STATUS_UNITIF (1) +#define NPCM4XX_STATUS_BUSY (0) /* 0x20: SPI_TX fields */ -#define NPCM4XX_TX_TX (0) +#define NPCM4XX_TX_TX (0) /* 0x30: SPI_RX fields */ -#define NPCM4XX_RX_RX (0) +#define NPCM4XX_RX_RX (0) + +#define NPCM4XX_SPIP_SINGLE_DUMMY_BYTE 0x8 + +#define NPCM4XX_SPIP_SPI_NOR_READ_INIT 0 +#define NPCM4XX_SPIP_SPI_NOR_WRITE_INIT 1 +#define NPCM4XX_SPIP_SPI_NOR_READ_INIT_OK BIT(NPCM4XX_SPIP_SPI_NOR_READ_INIT) +#define NPCM4XX_SPIP_SPI_NOR_WRITE_INIT_OK BIT(NPCM4XX_SPIP_SPI_NOR_WRITE_INIT) /* * SPI Synchronous serial Interface Controller (SPIM) device registers diff --git a/soc/arm/npcm4xx/npcm400f/sig_def_list.h b/soc/arm/npcm4xx/npcm400f/sig_def_list.h index 9708865ae6e552..64a51799a386a4 100644 --- a/soc/arm/npcm4xx/npcm400f/sig_def_list.h +++ b/soc/arm/npcm4xx/npcm400f/sig_def_list.h @@ -141,14 +141,14 @@ SIG_DEFINE(TD4P, C6, SIG_DESC_SET(0x11, 2)) SIG_DEFINE(VIN3, D6, SIG_DESC_CLEAR(0x11, 4), SIG_DESC_SET(0x11, 3)) #endif -#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip), okay) && CONFIG_SPIP_NPCM4XX +#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip1), okay) && CONFIG_SPIP_NPCM4XX /* DEVALTC, DEV_CTL3 */ -SIG_DEFINE(SPIP_CS, A12, SIG_DESC_SET(0x1c, 1)) -SIG_DEFINE(SPIP_SCLK, D12, SIG_DESC_SET(0x1c, 1)) -SIG_DEFINE(SPIP_DIO0, C12, SIG_DESC_SET(0x1c, 1)) -SIG_DEFINE(SPIP_DIO1, B12, SIG_DESC_SET(0x1c, 1)) -SIG_DEFINE(SPIP_DIO2, A11, SIG_DESC_SET(0x1c, 1), SIG_DESC_CLEAR(0x04, 2)) -SIG_DEFINE(SPIP_DIO3, A10, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP1_CS, A12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP1_SCLK, D12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP1_DIO0, C12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP1_DIO1, B12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP1_DIO2, A11, SIG_DESC_SET(0x1c, 1), SIG_DESC_CLEAR(0x04, 2)) +SIG_DEFINE(SPIP1_DIO3, A10, SIG_DESC_SET(0x1c, 1)) #endif #if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c0), okay) && CONFIG_I3C_NPCM4XX