From f02873428ec2dd771227bba2f76c99bb8e038be0 Mon Sep 17 00:00:00 2001 From: TY Su Date: Wed, 9 Aug 2023 10:43:14 +0800 Subject: [PATCH] drivers: spip: add SPIP driver support for NPCM4XX Add SPIP driver support for NPCM4XX. (not support slave mode) Signed-off-by: TY Su --- boards/arm/npcm400f_evb/fun_def_list.h | 5 + boards/arm/npcm400f_evb/npcm400f_evb.dts | 3 + .../arm/npcm400f_evb/npcm400f_evb_defconfig | 6 +- drivers/spi/CMakeLists.txt | 1 + drivers/spi/Kconfig | 2 + drivers/spi/Kconfig.npcm4xx_spip | 11 + drivers/spi/spi_npcm4xx_spip.c | 277 ++++++++++++++++++ dts/arm/nuvoton/npcm400f.dtsi | 11 + dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi | 2 + dts/bindings/spi/nuvoton,npcm4xx-spip.yaml | 14 + soc/arm/npcm4xx/common/reg/reg_def.h | 123 +++++++- soc/arm/npcm4xx/npcm400f/sig_def_list.h | 10 + 12 files changed, 454 insertions(+), 11 deletions(-) create mode 100644 drivers/spi/Kconfig.npcm4xx_spip create mode 100644 drivers/spi/spi_npcm4xx_spip.c create mode 100644 dts/bindings/spi/nuvoton,npcm4xx-spip.yaml diff --git a/boards/arm/npcm400f_evb/fun_def_list.h b/boards/arm/npcm400f_evb/fun_def_list.h index 2b7abd0f8ac371..f3b2ca7dafdfd3 100644 --- a/boards/arm/npcm400f_evb/fun_def_list.h +++ b/boards/arm/npcm400f_evb/fun_def_list.h @@ -66,3 +66,8 @@ FUN_DEFINE(DT_NODELABEL(pinctrl_thr2_default), THR2) FUN_DEFINE(DT_NODELABEL(pinctrl_td4p_default), TD4P) FUN_DEFINE(DT_NODELABEL(pinctrl_vin3_default), VIN3) #endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip), okay) && CONFIG_SPIP_NPCM4XX +FUN_DEFINE(DT_NODELABEL(pinctrl_spip_default), SPIP_CS, SPIP_SCLK, SPIP_DIO0, SPIP_DIO1) +FUN_DEFINE(DT_NODELABEL(pinctrl_spip_quad), SPIP_DIO2, SPIP_DIO3) +#endif diff --git a/boards/arm/npcm400f_evb/npcm400f_evb.dts b/boards/arm/npcm400f_evb/npcm400f_evb.dts index 7cb8b6abea0980..3dcb13accb3653 100644 --- a/boards/arm/npcm400f_evb/npcm400f_evb.dts +++ b/boards/arm/npcm400f_evb/npcm400f_evb.dts @@ -161,3 +161,6 @@ /* &pinctrl_td4p_default */ /* TD4P - C6 */ &pinctrl_vin3_default>; /* VIN3 - D6 */ }; +&spip { + status = "okay"; +}; diff --git a/boards/arm/npcm400f_evb/npcm400f_evb_defconfig b/boards/arm/npcm400f_evb/npcm400f_evb_defconfig index 8cf604b3290a3c..52a3af6dc99c01 100644 --- a/boards/arm/npcm400f_evb/npcm400f_evb_defconfig +++ b/boards/arm/npcm400f_evb/npcm400f_evb_defconfig @@ -73,4 +73,8 @@ CONFIG_I2C=y #ADC Driver CONFIG_ADC=y -CONFIG_ADC_NPCM4XX=y \ No newline at end of file +CONFIG_ADC_NPCM4XX=y + +#SPIP Driver +CONFIG_SPI=y +CONFIG_SPIP_NPCM4XX=y \ No newline at end of file diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt index a0dabdf0c16479..7cdb43b1529a53 100644 --- a/drivers/spi/CMakeLists.txt +++ b/drivers/spi/CMakeLists.txt @@ -26,5 +26,6 @@ zephyr_library_sources_ifdef(CONFIG_ESP32_SPIM spi_esp32_spim.c) zephyr_library_sources_ifdef(CONFIG_SPI_TEST spi_test.c) zephyr_library_sources_ifdef(CONFIG_SPI_PSOC6 spi_psoc6.c) zephyr_library_sources_ifdef(CONFIG_SPI_NPCM4XX_FIU spi_npcm4xx_fiu.c) +zephyr_library_sources_ifdef(CONFIG_SPIP_NPCM4XX spi_npcm4xx_spip.c) zephyr_library_sources_ifdef(CONFIG_USERSPACE spi_handlers.c) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 880766248e84c0..b3876132b68756 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -77,4 +77,6 @@ source "drivers/spi/Kconfig.psoc6" source "drivers/spi/Kconfig.npcm4xx_fiu" +source "drivers/spi/Kconfig.npcm4xx_spip" + endif # SPI diff --git a/drivers/spi/Kconfig.npcm4xx_spip b/drivers/spi/Kconfig.npcm4xx_spip new file mode 100644 index 00000000000000..90b3be1aa4f556 --- /dev/null +++ b/drivers/spi/Kconfig.npcm4xx_spip @@ -0,0 +1,11 @@ +# NPCM4XX SPI Driver configuration options + +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +config SPIP_NPCM4XX + bool "Nuvoton NPCM4XX SPI driver SPIP" + default y + depends on SOC_FAMILY_NPCM4XX + help + Enable the SPI driver for NPCM4XX family of processors. \ No newline at end of file diff --git a/drivers/spi/spi_npcm4xx_spip.c b/drivers/spi/spi_npcm4xx_spip.c new file mode 100644 index 00000000000000..927d84b6aa4b32 --- /dev/null +++ b/drivers/spi/spi_npcm4xx_spip.c @@ -0,0 +1,277 @@ +/* + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nuvoton_npcm4xx_spip + +#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL +#include +LOG_MODULE_REGISTER(spip_npcm4xx); + +#include +#include +#include +#include "spi_context.h" + +/* Device constant configuration parameters */ +struct npcm4xx_spip_config { + /* SPIP reg base address */ + uintptr_t base; + /* clock configuration */ + struct npcm4xx_clk_cfg clk_cfg; +}; + +/* Device run time data */ +struct npcm4xx_spip_data { + struct spi_context ctx; + uint32_t apb3; +}; + +static void SPI_SET_SS0_HIGH(const struct device *dev) +{ + const struct npcm4xx_spip_config *cfg = dev->config; + struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + + spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); + spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SSACTPOL); + spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SS); +} + +static void SPI_SET_SS0_LOW(const struct device *dev) +{ + const struct npcm4xx_spip_config *cfg = dev->config; + struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + + spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_AUTOSS); + spip_regs->SSCTL &= ~BIT(NPCM4XX_SSCTL_SSACTPOL); + spip_regs->SSCTL |= BIT(NPCM4XX_SSCTL_SS); +} + +static int spip_npcm4xx_configure(const struct device *dev, + const struct spi_config *config) +{ + const struct npcm4xx_spip_config *cfg = dev->config; + struct npcm4xx_spip_data *data = dev->data; + struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + uint32_t u32Div; + int ret; + + if (SPI_WORD_SIZE_GET(config->operation) != 8) { + LOG_ERR("Word sizes other than 8 bits are not supported"); + ret = -ENOTSUP; + } else { + spip_regs->CTL &= ~(0x1F << NPCM4XX_CTL_DWIDTH); + spip_regs->CTL |= (SPI_WORD_SIZE_GET(config->operation) << NPCM4XX_CTL_DWIDTH); + } + + if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) { + spip_regs->CTL |= BIT(NPCM4XX_CTL_CLKPOL); + if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) { + spip_regs->CTL &= ~BIT(NPCM4XX_CTL_TXNEG); + spip_regs->CTL &= ~BIT(NPCM4XX_CTL_RXNEG); + } else { + spip_regs->CTL |= BIT(NPCM4XX_CTL_TXNEG); + spip_regs->CTL |= BIT(NPCM4XX_CTL_RXNEG); + } + } else { + spip_regs->CTL &= ~BIT(NPCM4XX_CTL_CLKPOL); + } + + if (config->operation & SPI_TRANSFER_LSB) { + spip_regs->CTL |= BIT(NPCM4XX_CTL_LSB); + } else { + spip_regs->CTL &= ~BIT(NPCM4XX_CTL_LSB); + } + + if (config->operation & SPI_OP_MODE_SLAVE) { + LOG_ERR("Slave mode is not supported"); + ret = -ENOTSUP; + } else { + spip_regs->CTL &= ~BIT(NPCM4XX_CTL_SLAVE); + } + + /* Set Bus clock */ + if (config->frequency != 0) { + if (config->frequency <= data->apb3) { + u32Div = (data->apb3 / config->frequency) - 1; + if (data->apb3 % config->frequency) { + u32Div += 1; + } + if (u32Div > 0xFF) { + u32Div = 0xFF; + } + } + } + + spip_regs->CLKDIV = (spip_regs->CLKDIV & ~0xFF) | u32Div; + + /* spip enable */ + spip_regs->CTL |= BIT(NPCM4XX_CTL_SPIEN); + + return ret; +} + +static int spip_npcm4xx_transceive(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + const struct npcm4xx_spip_config *cfg = dev->config; + struct npcm4xx_spip_data *data = dev->data; + struct spip_reg *const spip_regs = (struct spip_reg *) cfg->base; + + spi_context_lock(&data->ctx, false, NULL, config); + data->ctx.config = config; + + int ret, error = 0; + uint8_t txDone; + /* Configure */ + ret = spip_npcm4xx_configure(dev, config); + if (ret) { + return -ENOTSUP; + } + ret = 0; + spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1); + + + if (config->operation & SPI_OP_MODE_SLAVE) { + /* Slave */ + LOG_ERR("Slave mode is not supported"); + ret = -ENOTSUP; + } else { + /* Master */ + SPI_SET_SS0_LOW(dev); + if (rx_bufs == NULL) { + /* write data to SPI flash */ + while (spi_context_tx_buf_on(&data->ctx)) { + /*TX*/ + if ((spip_regs->STATUS & BIT(NPCM4XX_STATUS_TXFULL)) == 0) { + spip_regs->TX = *data->ctx.tx_buf; + spi_context_update_tx(&data->ctx, 1, 1); + } + } + } else { + txDone = 0; + spip_regs->FIFOCTL |= BIT(NPCM4XX_FIFOCTL_RXRST); + while (1) { + /*TX*/ + if (spi_context_tx_buf_on(&data->ctx)) { + if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_TXFULL))) { + spip_regs->TX = *data->ctx.tx_buf; + spi_context_update_tx(&data->ctx, 1, 1); + } + } else if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_BUSY))) { + txDone = 1; + } + + /*RX*/ + if (spi_context_rx_buf_on(&data->ctx)) { + if (!(spip_regs->STATUS & BIT(NPCM4XX_STATUS_RXEMPTY))) { + *data->ctx.rx_buf = spip_regs->RX; + spi_context_update_rx(&data->ctx, 1, 1); + } else if (txDone == 1) { + ret = -EOVERFLOW; + break; + } + } else { + if (txDone == 1) { + break; + } + } + } + } + + do { + if ((spip_regs->STATUS & BIT(NPCM4XX_STATUS_BUSY)) == 0) { + break; + } + } while (1); + + SPI_SET_SS0_HIGH(dev); + } + spi_context_release(&data->ctx, error); + if (error != 0) { + ret = error; + } + + return ret; +} + +#ifdef CONFIG_SPI_ASYNC +static int spip_npcm4xx_transceive_async(const struct device *dev, + const struct spi_config *config, + const struct spi_buf_set *tx_bufs, + const struct spi_buf_set *rx_bufs) +{ + return spip_npcm4xx_transceive(dev, config, tx_bufs, rx_bufs); +} +#endif /* CONFIG_SPI_ASYNC */ + +static int spip_npcm4xx_release(const struct device *dev, + const struct spi_config *config) +{ + struct npcm4xx_spip_data *data = dev->data; + + spi_context_unlock_unconditionally(&data->ctx); + + return 0; +} + +static int spip_npcm4xx_init(const struct device *dev) +{ + const struct npcm4xx_spip_config *cfg = dev->config; + struct npcm4xx_spip_data *data = dev->data; + const struct device *const clk_dev = + device_get_binding(NPCM4XX_CLK_CTRL_NAME); + uint32_t spip_apb3; + int ret; + + if (!device_is_ready(clk_dev)) { + LOG_ERR("%s device not ready", clk_dev->name); + return -ENODEV; + } + /* Turn on device clock first and get source clock freq. */ + ret = clock_control_on(clk_dev, + (clock_control_subsys_t)&cfg->clk_cfg); + if (ret < 0) { + LOG_ERR("Turn on SPIP clock fail %d", ret); + return ret; + } + + ret = clock_control_get_rate(clk_dev, (clock_control_subsys_t *) + &cfg->clk_cfg, &spip_apb3); + + if (ret < 0) { + LOG_ERR("Get ITIM clock rate error %d", ret); + return ret; + } + + data->apb3 = spip_apb3; + + spi_context_unlock_unconditionally(&data->ctx); + return 0; +} + +static const struct spi_driver_api spip_npcm4xx_driver_api = { + .transceive = spip_npcm4xx_transceive, +#ifdef CONFIG_SPI_ASYNC + .transceive_async = spip_npcm4xx_transceive_async, +#endif + .release = spip_npcm4xx_release, +}; + + +static const struct npcm4xx_spip_config spip_npcm4xx_config = { + .base = DT_INST_REG_ADDR(0), + .clk_cfg = NPCM4XX_DT_CLK_CFG_ITEM(0), +}; + +static struct npcm4xx_spip_data spip_npcm4xx_dev_data = { + SPI_CONTEXT_INIT_LOCK(spip_npcm4xx_dev_data, ctx), +}; + + +DEVICE_DT_INST_DEFINE(0, &spip_npcm4xx_init, NULL, + &spip_npcm4xx_dev_data, + &spip_npcm4xx_config, POST_KERNEL, + CONFIG_SPI_INIT_PRIORITY, &spip_npcm4xx_driver_api); diff --git a/dts/arm/nuvoton/npcm400f.dtsi b/dts/arm/nuvoton/npcm400f.dtsi index e8bdf57497c358..7559800d7ed0ca 100644 --- a/dts/arm/nuvoton/npcm400f.dtsi +++ b/dts/arm/nuvoton/npcm400f.dtsi @@ -158,6 +158,17 @@ status = "disabled"; label = "ADC_0"; }; + + spip: spi@40016000 { + compatible = "nuvoton,npcm4xx-spip"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40016000 0x100>; + clocks = <&pcc NPCM4XX_CLOCK_BUS_APB3 NPCM4XX_PWDWN_CTL4 7>; + pinctrl-0 = <&pinctrl_spip_default &pinctrl_spip_quad>; + label = "SPIP"; + status = "disabled"; + }; }; soc-id { diff --git a/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi b/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi index 39483fb467a63c..c5a363fdadecc4 100644 --- a/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi +++ b/dts/arm/nuvoton/npcm4xx/npcm4xx-pinctrl.dtsi @@ -33,4 +33,6 @@ pinctrl_thr2_default: thr2_default {}; pinctrl_td4p_default: td4p_default {}; pinctrl_vin3_default: vin3_default {}; + pinctrl_spip_default: spip_default{}; + pinctrl_spip_quad: spip_quad{}; }; diff --git a/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml b/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml new file mode 100644 index 00000000000000..276921dc6e4433 --- /dev/null +++ b/dts/bindings/spi/nuvoton,npcm4xx-spip.yaml @@ -0,0 +1,14 @@ +# Copyright (c) 2023 Nuvoton Technology Corporation. +# SPDX-License-Identifier: Apache-2.0 + +description: Nuvoton, NPCM4XX-SPIP controller node + +compatible: "nuvoton,npcm4xx-spip" + +include: ["spi-controller.yaml", "nuvoton-pinctrl.yaml"] + +properties: + reg: + required: true + clocks: + required: true diff --git a/soc/arm/npcm4xx/common/reg/reg_def.h b/soc/arm/npcm4xx/common/reg/reg_def.h index f67eb20fce83da..5dc9a40e8ab1f1 100644 --- a/soc/arm/npcm4xx/common/reg/reg_def.h +++ b/soc/arm/npcm4xx/common/reg/reg_def.h @@ -388,33 +388,33 @@ struct adc_reg { /* 0x0E: Operation Mode select */ volatile uint16_t ADCTM; volatile uint16_t RESERVED2; - /* 0x12: Offset setting for tdp */ + /* 0x12: Offset setting for tdp */ volatile uint16_t ADCTDPO[3]; volatile uint16_t RESERVED3[4]; - /* 0x20: DSADC Analog Control register 1 */ + /* 0x20: DSADC Analog Control register 1 */ volatile uint8_t ADCACTRL1; volatile uint8_t RESERVED4; - /* 0x22: DSADC Analog Power Down Control */ + /* 0x22: DSADC Analog Power Down Control */ volatile uint16_t ADCACTRL2; volatile uint8_t RESERVED5[2]; - /* 0x26: Voltage / Thermister mode select */ + /* 0x26: Voltage / Thermister mode select */ volatile uint8_t DSADCCTRL6; volatile uint8_t RESERVED6; - /* 0x28: Voltage / Thermister mode select */ + /* 0x28: Voltage / Thermister mode select */ volatile uint8_t DSADCCTRL7; volatile uint8_t RESERVED7[3]; - /* 0x2C: Voltage / Thermister mode select */ + /* 0x2C: Voltage / Thermister mode select */ volatile uint16_t DSADCCTRL8; volatile uint8_t RESERVED8[74]; - /* 0x78: DSADC Configuration */ + /* 0x78: DSADC Configuration */ volatile uint16_t DSADCCFG; - /* 0x7A: DSADC Channel select */ + /* 0x7A: DSADC Channel select */ volatile uint8_t DSADCCS; volatile uint8_t RESERVED9; - /* 0x7C: DSADC global status */ + /* 0x7C: DSADC global status */ volatile uint16_t DSADCSTS; volatile uint16_t RESERVED10; - /* 0x80: Temperature Channel Data */ + /* 0x80: Temperature Channel Data */ volatile uint16_t TCHNDAT; }; @@ -503,6 +503,109 @@ struct twd_reg { #define NPCM4XX_T0CSR_TESDIS (7) #define NPCM4XX_WDCP_WDIV (0) +/* + * SPI PERIPHERAL INTERFACE (SPIP) device registers + */ +struct spip_reg { + /* 0x00: SPI Control Register */ + volatile uint32_t CTL; + /* 0x04: SPI Clock Divider Register */ + volatile uint32_t CLKDIV; + /* 0x08: SPI Slave Select Control Register */ + volatile uint32_t SSCTL; + /* 0x0C: SPI PDMA Control Register */ + volatile uint32_t PDMACTL; + /* 0x10: SPI FIFO Control Register */ + volatile uint32_t FIFOCTL; + /* 0x14: SPI Status Register */ + volatile uint32_t STATUS; + volatile uint32_t RESERVE0[2]; + /* 0x20: SPI Data Transmit Register */ + volatile uint32_t TX; + volatile uint32_t RESERVE1[3]; + /* 0x30: SPI Data Receive Register */ + volatile uint32_t RX; +}; + +/* SPIP register fields */ +/* 0x00: SPI_CTL fields */ +#define NPCM4XX_CTL_QUADIOEN (22) +#define NPCM4XX_CTL_DUALIOEN (21) +#define NPCM4XX_CTL_QDIODIR (20) +#define NPCM4XX_CTL_REORDER (19) +#define NPCM4XX_CTL_SLAVE (18) +#define NPCM4XX_CTL_UNITIEN (17) +#define NPCM4XX_CTL_TWOBIT (16) +#define NPCM4XX_CTL_LSB (13) +#define NPCM4XX_CTL_DWIDTH (8) +#define NPCM4XX_CTL_SUSPITV (4) +#define NPCM4XX_CTL_CLKPOL (3) +#define NPCM4XX_CTL_TXNEG (2) +#define NPCM4XX_CTL_RXNEG (1) +#define NPCM4XX_CTL_SPIEN (0) + +/* 0x04: SPI_CLKDIV fields */ +#define NPCM4XX_CLKDIV_DIVIDER (0) + +/* 0x08: SPI_SSCTL fields */ +#define NPCM4XX_SSCTL_SLVTOCNT (16) +#define NPCM4XX_SSCTL_SSINAIEN (13) +#define NPCM4XX_SSCTL_SSACTIEN (12) +#define NPCM4XX_SSCTL_SLVURIEN (9) +#define NPCM4XX_SSCTL_SLVBEIEN (8) +#define NPCM4XX_SSCTL_SLVTORST (6) +#define NPCM4XX_SSCTL_SLVTOIEN (5) +#define NPCM4XX_SSCTL_SLV3WIRE (4) +#define NPCM4XX_SSCTL_AUTOSS (3) +#define NPCM4XX_SSCTL_SSACTPOL (2) +#define NPCM4XX_SSCTL_SS (0) + +/* 0x0C: SPI_PDMACTL fields */ +#define NPCM4XX_PDMACTL_PDMARST (2) +#define NPCM4XX_PDMACTL_RXPDMAEN (1) +#define NPCM4XX_PDMACTL_TXPDMAEN (0) + +/* 0x10: SPI_FIFOCTL fields */ +#define NPCM4XX_FIFOCTL_TXTH (28) +#define NPCM4XX_FIFOCTL_RXTH (24) +#define NPCM4XX_FIFOCTL_TXUFIEN (7) +#define NPCM4XX_FIFOCTL_TXUFPOL (6) +#define NPCM4XX_FIFOCTL_RXOVIEN (5) +#define NPCM4XX_FIFOCTL_RXTOIEN (4) +#define NPCM4XX_FIFOCTL_TXTHIEN (3) +#define NPCM4XX_FIFOCTL_RXTHIEN (2) +#define NPCM4XX_FIFOCTL_TXRST (1) +#define NPCM4XX_FIFOCTL_RXRST (0) + +/* 0x14: SPI_STATUS fields */ +#define NPCM4XX_STATUS_TXCNT (28) +#define NPCM4XX_STATUS_RXCNT (24) +#define NPCM4XX_STATUS_TXRXRST (23) +#define NPCM4XX_STATUS_TXUFIF (19) +#define NPCM4XX_STATUS_TXTHIF (18) +#define NPCM4XX_STATUS_TXFULL (17) +#define NPCM4XX_STATUS_TXEMPTY (16) +#define NPCM4XX_STATUS_SPIENSTS (15) +#define NPCM4XX_STATUS_RXTOIF (12) +#define NPCM4XX_STATUS_RXOVIF (11) +#define NPCM4XX_STATUS_RXTHIF (10) +#define NPCM4XX_STATUS_RXFULL (9) +#define NPCM4XX_STATUS_RXEMPTY (8) +#define NPCM4XX_STATUS_SLVUDRIF (7) +#define NPCM4XX_STATUS_SLVBEIF (6) +#define NPCM4XX_STATUS_SLVTOIF (5) +#define NPCM4XX_STATUS_SSLINE (4) +#define NPCM4XX_STATUS_SSINAIF (3) +#define NPCM4XX_STATUS_SSACTIF (2) +#define NPCM4XX_STATUS_UNITIF (1) +#define NPCM4XX_STATUS_BUSY (0) + +/* 0x20: SPI_TX fields */ +#define NPCM4XX_TX_TX (0) + +/* 0x30: SPI_RX fields */ +#define NPCM4XX_RX_RX (0) + /* Flash Interface Unit (FIU) device registers */ struct fiu_reg { volatile uint8_t reserved1; diff --git a/soc/arm/npcm4xx/npcm400f/sig_def_list.h b/soc/arm/npcm4xx/npcm400f/sig_def_list.h index ff46656a8ab879..c2694482ec6fac 100644 --- a/soc/arm/npcm4xx/npcm400f/sig_def_list.h +++ b/soc/arm/npcm4xx/npcm400f/sig_def_list.h @@ -140,3 +140,13 @@ SIG_DEFINE(TD4P, C6, SIG_DESC_SET(0x11, 2)) /* DEVALT1 */ SIG_DEFINE(VIN3, D6, SIG_DESC_CLEAR(0x11, 4), SIG_DESC_SET(0x11, 3)) #endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(spip), okay) && CONFIG_SPIP_NPCM4XX +/* DEVALTC, DEV_CTL3 */ +SIG_DEFINE(SPIP_CS, A12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP_SCLK, D12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP_DIO0, C12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP_DIO1, B12, SIG_DESC_SET(0x1c, 1)) +SIG_DEFINE(SPIP_DIO2, A11, SIG_DESC_SET(0x1c, 1), SIG_DESC_CLEAR(0x04, 2)) +SIG_DEFINE(SPIP_DIO3, A10, SIG_DESC_SET(0x1c, 1)) +#endif