diff --git a/soc/arm/npcm4xx/common/reg/reg_def.h b/soc/arm/npcm4xx/common/reg/reg_def.h
index bc7c44766b002a..fe95d5cda7bd97 100644
--- a/soc/arm/npcm4xx/common/reg/reg_def.h
+++ b/soc/arm/npcm4xx/common/reg/reg_def.h
@@ -156,18 +156,22 @@ struct scfg_reg {
 	volatile uint8_t reserved1[3];
 	/* 0x006: Device Control 4 */
 	volatile uint8_t DEV_CTL4;
-	volatile uint8_t reserved2[9];
+        volatile uint8_t reserved2[4];
+	volatile uint8_t DEVALT10;
+	volatile uint8_t DEVALT11;
+	volatile uint8_t DEVALT12;
+	volatile uint8_t reserved3[2];
 	/* 0x010 - 1F: Device Alternate Function 0 - F */
 	volatile uint8_t DEVALT0[16];
-	volatile uint8_t reserved3[4];
+	volatile uint8_t reserved4[4];
 	/* 0x024: DEVALTCX */
 	volatile uint8_t DEVALTCX;
-	volatile uint8_t reserved4[3];
+	volatile uint8_t reserved5[3];
 	/* 0x028: Device Pull-Up Enable 0 */
 	volatile uint8_t DEVPU0;
 	/* 0x029: Device Pull-Down Enable 1 */
 	volatile uint8_t DEVPD1;
-	volatile uint8_t reserved5;
+	volatile uint8_t reserved6;
 	/* 0x02B: Low-Voltage Pins Control 1 */
 	volatile uint8_t LV_CTL1;
 };
@@ -202,6 +206,8 @@ struct scfg_reg {
 #define NPCM4XX_DEVPU0_I2C2_0_PUE                4
 #define NPCM4XX_DEVPU0_I2C3_0_PUE                6
 #define NPCM4XX_DEVPU1_F_SPI_PUD_EN              7
+#define NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE   0
+#define NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER  1
 #define NPCM4XX_DEVALTCX_GPIO_PULL_EN            7
 
 #define SCFG_BASE_ADDR (0x400C3000)
diff --git a/soc/arm/npcm4xx/npcm400f/Kconfig.defconfig.series b/soc/arm/npcm4xx/npcm400f/Kconfig.defconfig.series
index d6f0fddbb2db99..56b7d91756a95b 100644
--- a/soc/arm/npcm4xx/npcm400f/Kconfig.defconfig.series
+++ b/soc/arm/npcm4xx/npcm400f/Kconfig.defconfig.series
@@ -23,6 +23,21 @@ config ESPI_NPCM4XX
 	  https://www.intel.com/content/www/us/en/support/articles/000020952/
 	  software/chipset-software.html for more detail.
 
+choice GPIO_NPCM4XX_RESET_SL
+	prompt "Selects the GPIO reset to the corresponding reset source"
+	default GPIO_NPCM4XX_RESET_SL_CORE_DOMAIN
+
+config GPIO_NPCM4XX_RESET_SL_CORE_DOMAIN
+	bool "GPIO Reset by Core domain reset"
+	help
+	  GPIO port 0-9, A-F is reset by Core domain reset.
+
+config GPIO_NPCM4XX_RESET_SL_POWER_UP
+	bool "GPIO Reset by VSB Power-Up reset"
+	help
+	GPIO port 0-9, A-F is reset by VSB Power-Up reset.
+endchoice
+
 DT_CHOSEN_Z_FLASH := zephyr,flash
 
 config FLASH_SIZE
diff --git a/soc/arm/npcm4xx/npcm400f/soc.c b/soc/arm/npcm4xx/npcm400f/soc.c
index e5f9c73301daa4..87d63adad298c9 100644
--- a/soc/arm/npcm4xx/npcm400f/soc.c
+++ b/soc/arm/npcm4xx/npcm400f/soc.c
@@ -12,8 +12,19 @@
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
+uintptr_t scfg_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(scfg), 0);
+
 void z_platform_init(void)
 {
+	struct scfg_reg *inst_scfg = (struct scfg_reg *)scfg_base;
+
+	if (scfg_base) {
+#if CONFIG_GPIO_NPCM4XX_RESET_SL_POWER_UP
+		inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER;
+#else
+		inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE;
+#endif
+	}
 }
 
 static int soc_init(const struct device *dev)