From 6dcf3b5cd74baca6752bbd9caee7a0a1bcab2ed9 Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 15 May 2024 20:56:48 -0700 Subject: [PATCH 1/2] drivers: i3c: npcm4xx: add new API for OpenBIC add below API for OpenBIC: 1. i3c_slave_set_static_addr 2. i3c_set_pid_extra_info Signed-off-by: cpchiang --- drivers/i3c/i3c_npcm4xx.c | 39 +++ include/drivers/i3c/i3c.h | 18 ++ soc/arm/npcm4xx/common/reg/reg_def.h | 362 ++++++++++++++------------- 3 files changed, 239 insertions(+), 180 deletions(-) diff --git a/drivers/i3c/i3c_npcm4xx.c b/drivers/i3c/i3c_npcm4xx.c index 2f7a8f76320d62..25efc3cd91b615 100644 --- a/drivers/i3c/i3c_npcm4xx.c +++ b/drivers/i3c/i3c_npcm4xx.c @@ -2381,6 +2381,23 @@ int i3c_npcm4xx_slave_register(const struct device *dev, struct i3c_slave_setup return 0; } +int i3c_npcm4xx_slave_set_static_addr(const struct device *dev, uint8_t static_addr) +{ + struct i3c_npcm4xx_config *config = DEV_CFG(dev); + I3C_PORT_Enum port = config->inst_id; + I3C_DEVICE_INFO_t *pDevice; + uint32_t sconfig; + + pDevice = &gI3c_dev_node_internal[port]; + pDevice->staticAddr = static_addr; + + sconfig = I3C_GET_REG_CONFIG(port); + SET_FIELD(sconfig, NPCM4XX_I3C_CONFIG_SADDR, static_addr); + I3C_SET_REG_CONFIG(port, sconfig); + + return 0; +} + /* * slave send mdb */ @@ -2537,6 +2554,28 @@ int i3c_npcm4xx_slave_get_event_enabling(const struct device *dev, uint32_t *eve return 0; } +int i3c_npcm4xx_set_pid_extra_info(const struct device *dev, uint16_t extra_info) +{ + struct i3c_npcm4xx_config *config = DEV_CFG(dev); + I3C_PORT_Enum port = config->inst_id; + I3C_DEVICE_INFO_t *pDevice; + uint32_t partno; + + partno = I3C_GET_REG_PARTNO(port); + + SET_FIELD(partno, NPCM4XX_I3C_PARTNO_VENDOR_DEF, extra_info); + I3C_SET_REG_PARTNO(port, partno); + + pDevice = &gI3c_dev_node_internal[port]; + pDevice->partNumber = partno; + + pDevice->pid[4] = ((port & 0x0F) << 4) | + ((uint8_t)(extra_info >> 8) & 0x0F); + pDevice->pid[5] = (uint8_t)extra_info; + + return 0; +} + static void i3c_npcm4xx_master_rx_ibi(struct i3c_npcm4xx_obj *obj) { struct i3c_dev_desc *i3cdev; diff --git a/include/drivers/i3c/i3c.h b/include/drivers/i3c/i3c.h index a7da7c159a517a..f9c53df8755335 100644 --- a/include/drivers/i3c/i3c.h +++ b/include/drivers/i3c/i3c.h @@ -194,6 +194,14 @@ int i3c_npcm4xx_slave_get_event_enabling(const struct device *dev, uint32_t *eve */ int i3c_npcm4xx_slave_send_sir(const struct device *dev, struct i3c_ibi_payload *payload); +/** + * @brief set the static address of the i3c controller in slave mode + * @param dev the I3C controller in slave mode + * @param static_addr the new static address + * @return 0 if the static address is set + */ +int i3c_npcm4xx_slave_set_static_addr(const struct device *dev, uint8_t static_addr); + /** * @brief slave device prepares the data for master private read transfer * @@ -212,6 +220,14 @@ int i3c_npcm4xx_slave_send_sir(const struct device *dev, struct i3c_ibi_payload int i3c_npcm4xx_slave_put_read_data(const struct device *dev, struct i3c_slave_payload *data, struct i3c_ibi_payload *ibi_notify); +/** + * @brief set the pid extra info of the i3c controller + * @param dev the I3C controller + * @param extra_info the extra info of the pid bits[11:0] + * @return int 0 = success + */ +int i3c_npcm4xx_set_pid_extra_info(const struct device *dev, uint16_t extra_info); + /* common API */ int i3c_master_send_enec(const struct device *master, uint8_t addr, uint8_t evt); int i3c_master_send_disec(const struct device *master, uint8_t addr, uint8_t evt); @@ -231,10 +247,12 @@ int i3c_master_send_getbcr(const struct device *master, uint8_t addr, uint8_t *b #define i3c_master_enable_ibi i3c_npcm4xx_master_enable_ibi #define i3c_master_send_entdaa i3c_npcm4xx_master_send_entdaa #define i3c_slave_register i3c_npcm4xx_slave_register +#define i3c_slave_set_static_addr i3c_npcm4xx_slave_set_static_addr #define i3c_slave_send_sir i3c_npcm4xx_slave_send_sir #define i3c_slave_put_read_data i3c_npcm4xx_slave_put_read_data #define i3c_slave_get_dynamic_addr i3c_npcm4xx_slave_get_dynamic_addr #define i3c_slave_get_event_enabling i3c_npcm4xx_slave_get_event_enabling +#define i3c_set_pid_extra_info i3c_npcm4xx_set_pid_extra_info int i3c_jesd403_read(struct i3c_dev_desc *slave, uint8_t *addr, int addr_size, uint8_t *data, int data_size); diff --git a/soc/arm/npcm4xx/common/reg/reg_def.h b/soc/arm/npcm4xx/common/reg/reg_def.h index 90e775a3776259..4e448136b53e11 100644 --- a/soc/arm/npcm4xx/common/reg/reg_def.h +++ b/soc/arm/npcm4xx/common/reg/reg_def.h @@ -1961,19 +1961,19 @@ struct i3c_reg { volatile uint32_t ID; }; -#define I3C_BASE_ADDR(mdl) (0x40004000 + ((mdl) * 0x0200L)) +#define I3C_BASE_ADDR(mdl) (0x40004000 + ((mdl) * 0x0200L)) /* I3C register fields */ -#define NPCM4XX_I3C_MCONFIG_I2CBAUD FIELD(28, 31) -#define NPCM4XX_I3C_MCONFIG_ODHPP 24 -#define NPCM4XX_I3C_MCONFIG_ODBAUD FIELD(16, 23) -#define NPCM4XX_I3C_MCONFIG_PPLOW FIELD(12, 15) -#define NPCM4XX_I3C_MCONFIG_PPBAUD FIELD(8, 11) -#define NPCM4XX_I3C_MCONFIG_ODSTOP 6 -#define NPCM4XX_I3C_MCONFIG_DISTO 3 -#define NPCM4XX_I3C_MCONFIG_MSTENA FIELD(0, 1) -#define NPCM4XX_I3C_CONFIG_SADDR FIELD(25, 31) -#define NPCM4XX_I3C_CONFIG_BAMATCH FIELD(16, 22) +#define NPCM4XX_I3C_MCONFIG_I2CBAUD FIELD(28, 4) +#define NPCM4XX_I3C_MCONFIG_ODHPP 24 +#define NPCM4XX_I3C_MCONFIG_ODBAUD FIELD(16, 8) +#define NPCM4XX_I3C_MCONFIG_PPLOW FIELD(12, 4) +#define NPCM4XX_I3C_MCONFIG_PPBAUD FIELD(8, 4) +#define NPCM4XX_I3C_MCONFIG_ODSTOP 6 +#define NPCM4XX_I3C_MCONFIG_DISTO 3 +#define NPCM4XX_I3C_MCONFIG_MSTENA FIELD(0, 2) +#define NPCM4XX_I3C_CONFIG_SADDR FIELD(25, 7) +#define NPCM4XX_I3C_CONFIG_BAMATCH FIELD(16, 6) #define NPCM4XX_I3C_CONFIG_HDRCMD 10 #define NPCM4XX_I3C_CONFIG_OFFLINE 9 #define NPCM4XX_I3C_CONFIG_IDRAND 8 @@ -1982,240 +1982,242 @@ struct i3c_reg { #define NPCM4XX_I3C_CONFIG_MATCHSS 2 #define NPCM4XX_I3C_CONFIG_NACK 1 #define NPCM4XX_I3C_CONFIG_SLVENA 0 -#define NPCM4XX_I3C_STATUS_TIMECTRL FIELD(30, 31) -#define NPCM4XX_I3C_STATUS_ACTSTATE FIELD(28, 29) -#define NPCM4XX_I3C_STATUS_HJDIS 27 -#define NPCM4XX_I3C_STATUS_MRDIS 25 -#define NPCM4XX_I3C_STATUS_IBIDIS 24 -#define NPCM4XX_I3C_STATUS_EVDET FIELD(20, 21) -#define NPCM4XX_I3C_STATUS_EVENT 18 -#define NPCM4XX_I3C_STATUS_CHANDLED 17 -#define NPCM4XX_I3C_STATUS_DDRMATCH 16 -#define NPCM4XX_I3C_STATUS_ERRWARN 15 -#define NPCM4XX_I3C_STATUS_CCC 14 -#define NPCM4XX_I3C_STATUS_DACHG 13 +#define NPCM4XX_I3C_STATUS_TIMECTRL FIELD(30, 2) +#define NPCM4XX_I3C_STATUS_ACTSTATE FIELD(28, 2) +#define NPCM4XX_I3C_STATUS_HJDIS 27 +#define NPCM4XX_I3C_STATUS_MRDIS 25 +#define NPCM4XX_I3C_STATUS_IBIDIS 24 +#define NPCM4XX_I3C_STATUS_EVDET FIELD(20, 2) +#define NPCM4XX_I3C_STATUS_EVENT 18 +#define NPCM4XX_I3C_STATUS_CHANDLED 17 +#define NPCM4XX_I3C_STATUS_DDRMATCH 16 +#define NPCM4XX_I3C_STATUS_ERRWARN 15 +#define NPCM4XX_I3C_STATUS_CCC 14 +#define NPCM4XX_I3C_STATUS_DACHG 13 #define NPCM4XX_I3C_STATUS_TXNOTFULL 12 -#define NPCM4XX_I3C_STATUS_RXPEND 11 -#define NPCM4XX_I3C_STATUS_STOP 10 -#define NPCM4XX_I3C_STATUS_MATCHED 9 -#define NPCM4XX_I3C_STATUS_START 8 -#define NPCM4XX_I3C_STATUS_STHDR 6 -#define NPCM4XX_I3C_STATUS_STDAA 5 -#define NPCM4XX_I3C_STATUS_STREQWR 4 -#define NPCM4XX_I3C_STATUS_STREQRD 3 -#define NPCM4XX_I3C_STATUS_STCCCH 2 -#define NPCM4XX_I3C_STATUS_STMSG 1 +#define NPCM4XX_I3C_STATUS_RXPEND 11 +#define NPCM4XX_I3C_STATUS_STOP 10 +#define NPCM4XX_I3C_STATUS_MATCHED 9 +#define NPCM4XX_I3C_STATUS_START 8 +#define NPCM4XX_I3C_STATUS_STHDR 6 +#define NPCM4XX_I3C_STATUS_STDAA 5 +#define NPCM4XX_I3C_STATUS_STREQWR 4 +#define NPCM4XX_I3C_STATUS_STREQRD 3 +#define NPCM4XX_I3C_STATUS_STCCCH 2 +#define NPCM4XX_I3C_STATUS_STMSG 1 #define NPCM4XX_I3C_STATUS_STNOTSTOP 0 -#define NPCM4XX_I3C_CTRL_VENDINFO FIELD(24, 31) -#define NPCM4XX_I3C_CTRL_ACTSTATE FIELD(20, 21) -#define NPCM4XX_I3C_CTRL_PENDINT FIELD(16, 19) -#define NPCM4XX_I3C_CTRL_IBIDATA FIELD(8, 15) +#define NPCM4XX_I3C_CTRL_VENDINFO FIELD(24, 8) +#define NPCM4XX_I3C_CTRL_ACTSTATE FIELD(20, 2) +#define NPCM4XX_I3C_CTRL_PENDINT FIELD(16, 4) +#define NPCM4XX_I3C_CTRL_IBIDATA FIELD(8, 8) #define NPCM4XX_I3C_CTRL_EXTDATA 3 -#define NPCM4XX_I3C_CTRL_EVENT FIELD(0, 1) -#define NPCM4XX_I3C_INTSET_EVENT 18 -#define NPCM4XX_I3C_INTSET_CHANDLED 17 +#define NPCM4XX_I3C_CTRL_EVENT FIELD(0, 2) +#define NPCM4XX_I3C_INTSET_EVENT 18 +#define NPCM4XX_I3C_INTSET_CHANDLED 17 #define NPCM4XX_I3C_INTSET_DDRMATCHED 16 -#define NPCM4XX_I3C_INTSET_ERRWARN 15 -#define NPCM4XX_I3C_INTSET_CCC 14 -#define NPCM4XX_I3C_INTSET_DACHG 13 +#define NPCM4XX_I3C_INTSET_ERRWARN 15 +#define NPCM4XX_I3C_INTSET_CCC 14 +#define NPCM4XX_I3C_INTSET_DACHG 13 #define NPCM4XX_I3C_INTSET_TXNOTFULL 12 -#define NPCM4XX_I3C_INTSET_RXPEND 11 -#define NPCM4XX_I3C_INTSET_STOP 10 -#define NPCM4XX_I3C_INTSET_MATCHED 9 -#define NPCM4XX_I3C_INTSET_START 8 +#define NPCM4XX_I3C_INTSET_RXPEND 11 +#define NPCM4XX_I3C_INTSET_STOP 10 +#define NPCM4XX_I3C_INTSET_MATCHED 9 +#define NPCM4XX_I3C_INTSET_START 8 #define NPCM4XX_I3C_INTCLR_EVENT 18 #define NPCM4XX_I3C_INTCLR_CHANDLED 17 -#define NPCM4XX_I3C_INTCLR_DDRMATCHED 16 +#define NPCM4XX_I3C_INTCLR_DDRMATCHED 16 #define NPCM4XX_I3C_INTCLR_ERRWARN 15 #define NPCM4XX_I3C_INTCLR_CCC 14 #define NPCM4XX_I3C_INTCLR_DACHG 13 -#define NPCM4XX_I3C_INTCLR_TXNOTFULL 12 +#define NPCM4XX_I3C_INTCLR_TXNOTFULL 12 #define NPCM4XX_I3C_INTCLR_RXPEND 11 #define NPCM4XX_I3C_INTCLR_STOP 10 #define NPCM4XX_I3C_INTCLR_MATCHED 9 #define NPCM4XX_I3C_INTCLR_START 8 -#define NPCM4XX_I3C_INTMASKED_EVENT 18 +#define NPCM4XX_I3C_INTMASKED_EVENT 18 #define NPCM4XX_I3C_INTMASKED_CHANDLED 17 #define NPCM4XX_I3C_INTMASKED_DDRMATCHED 16 #define NPCM4XX_I3C_INTMASKED_ERRWARN 15 -#define NPCM4XX_I3C_INTMASKED_CCC 14 -#define NPCM4XX_I3C_INTMASKED_DACHG 13 +#define NPCM4XX_I3C_INTMASKED_CCC 14 +#define NPCM4XX_I3C_INTMASKED_DACHG 13 #define NPCM4XX_I3C_INTMASKED_TXNOTFULL 12 #define NPCM4XX_I3C_INTMASKED_RXPEND 11 -#define NPCM4XX_I3C_INTMASKED_STOP 10 +#define NPCM4XX_I3C_INTMASKED_STOP 10 #define NPCM4XX_I3C_INTMASKED_MATCHED 9 -#define NPCM4XX_I3C_INTMASKED_START 8 +#define NPCM4XX_I3C_INTMASKED_START 8 #define NPCM4XX_I3C_ERRWARN_OWRITE 17 #define NPCM4XX_I3C_ERRWARN_OREAD 16 #define NPCM4XX_I3C_ERRWARN_S0S1 11 #define NPCM4XX_I3C_ERRWARN_HCRC 10 #define NPCM4XX_I3C_ERRWARN_HPAR 9 #define NPCM4XX_I3C_ERRWARN_SPAR 8 -#define NPCM4XX_I3C_ERRWARN_INVSTART 4 +#define NPCM4XX_I3C_ERRWARN_INVSTART 4 #define NPCM4XX_I3C_ERRWARN_TERM 3 -#define NPCM4XX_I3C_ERRWARN_URUNNACK 2 +#define NPCM4XX_I3C_ERRWARN_URUNNACK 2 #define NPCM4XX_I3C_ERRWARN_URUN 1 #define NPCM4XX_I3C_ERRWARN_ORUN 0 -#define NPCM4XX_I3C_DMACTRL_DMAWIDTH FIELD(4, 5) -#define NPCM4XX_I3C_DMACTRL_DMATB FIELD(2, 3) -#define NPCM4XX_I3C_DMACTRL_DMAFB FIELD(0, 1) -#define NPCM4XX_I3C_DATACTRL_RXEMPTY 31 +#define NPCM4XX_I3C_DMACTRL_DMAWIDTH FIELD(4, 2) +#define NPCM4XX_I3C_DMACTRL_DMATB FIELD(2, 2) +#define NPCM4XX_I3C_DMACTRL_DMAFB FIELD(0, 2) +#define NPCM4XX_I3C_DATACTRL_RXEMPTY 31 #define NPCM4XX_I3C_DATACTRL_TXFULL 30 -#define NPCM4XX_I3C_DATACTRL_RXCOUNT FIELD(24, 28) -#define NPCM4XX_I3C_DATACTRL_TXCOUNT FIELD(16, 20) -#define NPCM4XX_I3C_DATACTRL_RXTRIG FIELD(6, 7) -#define NPCM4XX_I3C_DATACTRL_TXTRIG FIELD(4, 5) +#define NPCM4XX_I3C_DATACTRL_RXCOUNT FIELD(24, 5) +#define NPCM4XX_I3C_DATACTRL_TXCOUNT FIELD(16, 5) +#define NPCM4XX_I3C_DATACTRL_RXTRIG FIELD(6, 2) +#define NPCM4XX_I3C_DATACTRL_TXTRIG FIELD(4, 2) #define NPCM4XX_I3C_DATACTRL_UNLOCK 3 -#define NPCM4XX_I3C_DATACTRL_FLUSHFB 1 -#define NPCM4XX_I3C_DATACTRL_FLUSHTB 0 -#define NPCM4XX_I3C_WDATAB_END_A 16 -#define NPCM4XX_I3C_WDATAB_END_B 8 -#define NPCM4XX_I3C_WDATAB_DATA FIELD(0, 7) -#define NPCM4XX_I3C_WDATABE_DATA FIELD(0, 7) -#define NPCM4XX_I3C_WDATAH_END 16 -#define NPCM4XX_I3C_WDATAH_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_WDATAH_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_WDATAHE_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_WDATAHE_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_RDATAB_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_RDATAH_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_RDATAH_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_WDATAB1_DATA FIELD(0, 7) +#define NPCM4XX_I3C_DATACTRL_FLUSHFB 1 +#define NPCM4XX_I3C_DATACTRL_FLUSHTB 0 +#define NPCM4XX_I3C_WDATAB_END_A 16 +#define NPCM4XX_I3C_WDATAB_END_B 8 +#define NPCM4XX_I3C_WDATAB_DATA FIELD(0, 8) +#define NPCM4XX_I3C_WDATABE_DATA FIELD(0, 8) +#define NPCM4XX_I3C_WDATAH_END 16 +#define NPCM4XX_I3C_WDATAH_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_WDATAH_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_WDATAHE_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_WDATAHE_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_RDATAB_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_RDATAH_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_RDATAH_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_WDATAB1_DATA FIELD(0, 8) #define NPCM4XX_I3C_CAPABILITIES_DMA 31 #define NPCM4XX_I3C_CAPABILITIES_INT 30 -#define NPCM4XX_I3C_CAPABILITIES_FIFORX FIELD(28, 29) -#define NPCM4XX_I3C_CAPABILITIES_FIFOTX FIELD(26, 27) +#define NPCM4XX_I3C_CAPABILITIES_FIFORX FIELD(28, 2) +#define NPCM4XX_I3C_CAPABILITIES_FIFOTX FIELD(26, 2) #define NPCM4XX_I3C_CAPABILITIES_TIMECTRL 21 -#define NPCM4XX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 20) -#define NPCM4XX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 15) -#define NPCM4XX_I3C_CAPABILITIES_SADDR FIELD(10, 11) +#define NPCM4XX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 5) +#define NPCM4XX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 4) +#define NPCM4XX_I3C_CAPABILITIES_SADDR FIELD(10, 2) #define NPCM4XX_I3C_CAPABILITIES_HDRSUPP 6 -#define NPCM4XX_I3C_CAPABILITIES_IDREG FIELD(2, 5) -#define NPCM4XX_I3C_CAPABILITIES_IDENA FIELD(0, 1) +#define NPCM4XX_I3C_CAPABILITIES_IDREG FIELD(2, 4) +#define NPCM4XX_I3C_CAPABILITIES_IDENA FIELD(0, 2) #define NPCM4XX_I3C_DYNADDR_DADDR FIELD(1, 7) #define NPCM4XX_I3C_DYNADDR_DAVALID 0 -#define NPCM4XX_I3C_MAXLIMITS_MAXWR FIELD(16, 27) -#define NPCM4XX_I3C_MAXLIMITS_MAXRD FIELD(0, 11) -#define NPCM4XX_I3C_PARTNO_PARTNO FIELD(0, 31) -#define NPCM4XX_I3C_IDEXT_BCR FIELD(16, 23) -#define NPCM4XX_I3C_IDEXT_DCR FIELD(8, 15) -#define NPCM4XX_I3C_VENDORID_VID FIELD(0, 14) -#define NPCM4XX_I3C_TCCLOCK_FREQ FIELD(8, 15) -#define NPCM4XX_I3C_TCCLOCK_ACCURACY FIELD(0, 7) -#define NPCM4XX_I3C_MCTRL_RDTERM FIELD(16, 23) -#define NPCM4XX_I3C_MCTRL_ADDR FIELD(9, 15) -#define NPCM4XX_I3C_MCTRL_DIR 8 -#define NPCM4XX_I3C_MCTRL_IBIRESP FIELD(6, 7) -#define NPCM4XX_I3C_MCTRL_TYPE FIELD(4, 5) -#define NPCM4XX_I3C_MCTRL_REQUEST FIELD(0, 2) -#define NPCM4XX_I3C_MSTATUS_IBIADDR FIELD(24, 30) -#define NPCM4XX_I3C_MSTATUS_NOWMASTER 19 +#define NPCM4XX_I3C_MAXLIMITS_MAXWR FIELD(16, 12) +#define NPCM4XX_I3C_MAXLIMITS_MAXRD FIELD(0, 12) +#define NPCM4XX_I3C_PARTNO_PART_ID FIELD(16, 16) +#define NPCM4XX_I3C_PARTNO_INSTANCE_ID FIELD(12, 4) +#define NPCM4XX_I3C_PARTNO_VENDOR_DEF FIELD(0, 12) +#define NPCM4XX_I3C_IDEXT_BCR FIELD(16, 8) +#define NPCM4XX_I3C_IDEXT_DCR FIELD(8, 8) +#define NPCM4XX_I3C_VENDORID_VID FIELD(0, 15) +#define NPCM4XX_I3C_TCCLOCK_FREQ FIELD(8, 8) +#define NPCM4XX_I3C_TCCLOCK_ACCURACY FIELD(0, 8) +#define NPCM4XX_I3C_MCTRL_RDTERM FIELD(16, 8) +#define NPCM4XX_I3C_MCTRL_ADDR FIELD(9, 7) +#define NPCM4XX_I3C_MCTRL_DIR 8 +#define NPCM4XX_I3C_MCTRL_IBIRESP FIELD(6, 2) +#define NPCM4XX_I3C_MCTRL_TYPE FIELD(4, 2) +#define NPCM4XX_I3C_MCTRL_REQUEST FIELD(0, 3) +#define NPCM4XX_I3C_MSTATUS_IBIADDR FIELD(24, 7) +#define NPCM4XX_I3C_MSTATUS_NOWMASTER 19 #define NPCM4XX_I3C_MSTATUS_ERRWARN 15 #define NPCM4XX_I3C_MSTATUS_IBIWON 13 -#define NPCM4XX_I3C_MSTATUS_TXNOTFULL 12 +#define NPCM4XX_I3C_MSTATUS_TXNOTFULL 12 #define NPCM4XX_I3C_MSTATUS_RXPEND 11 -#define NPCM4XX_I3C_MSTATUS_COMPLETE 10 -#define NPCM4XX_I3C_MSTATUS_MCTRLDONE 9 -#define NPCM4XX_I3C_MSTATUS_SLVSTART 8 -#define NPCM4XX_I3C_MSTATUS_IBITYPE FIELD(6, 7) +#define NPCM4XX_I3C_MSTATUS_COMPLETE 10 +#define NPCM4XX_I3C_MSTATUS_MCTRLDONE 9 +#define NPCM4XX_I3C_MSTATUS_SLVSTART 8 +#define NPCM4XX_I3C_MSTATUS_IBITYPE FIELD(6, 2) #define NPCM4XX_I3C_MSTATUS_NACKED 5 #define NPCM4XX_I3C_MSTATUS_BETWEEN 4 -#define NPCM4XX_I3C_MSTATUS_STATE FIELD(0, 2) -#define NPCM4XX_I3C_IBIRULES_NOBYTE 31 -#define NPCM4XX_I3C_IBIRULES_MSB0 30 -#define NPCM4XX_I3C_IBIRULES_ADDR4 FIELD(24, 29) -#define NPCM4XX_I3C_IBIRULES_ADDR3 FIELD(18, 23) -#define NPCM4XX_I3C_IBIRULES_ADDR2 FIELD(12, 17) -#define NPCM4XX_I3C_IBIRULES_ADDR1 FIELD(6, 11) -#define NPCM4XX_I3C_IBIRULES_ADDR0 FIELD(0, 5) -#define NPCM4XX_I3C_MINTSET_NOWMASTER 19 +#define NPCM4XX_I3C_MSTATUS_STATE FIELD(0, 3) +#define NPCM4XX_I3C_IBIRULES_NOBYTE 31 +#define NPCM4XX_I3C_IBIRULES_MSB0 30 +#define NPCM4XX_I3C_IBIRULES_ADDR4 FIELD(24, 6) +#define NPCM4XX_I3C_IBIRULES_ADDR3 FIELD(18, 6) +#define NPCM4XX_I3C_IBIRULES_ADDR2 FIELD(12, 6) +#define NPCM4XX_I3C_IBIRULES_ADDR1 FIELD(6, 6) +#define NPCM4XX_I3C_IBIRULES_ADDR0 FIELD(0, 6) +#define NPCM4XX_I3C_MINTSET_NOWMASTER 19 #define NPCM4XX_I3C_MINTSET_ERRWARN 15 #define NPCM4XX_I3C_MINTSET_IBIWON 13 -#define NPCM4XX_I3C_MINTSET_TXNOTFULL 12 +#define NPCM4XX_I3C_MINTSET_TXNOTFULL 12 #define NPCM4XX_I3C_MINTSET_RXPEND 11 -#define NPCM4XX_I3C_MINTSET_COMPLETE 10 -#define NPCM4XX_I3C_MINTSET_MCTRLDONE 9 -#define NPCM4XX_I3C_MINTSET_SLVSTART 8 +#define NPCM4XX_I3C_MINTSET_COMPLETE 10 +#define NPCM4XX_I3C_MINTSET_MCTRLDONE 9 +#define NPCM4XX_I3C_MINTSET_SLVSTART 8 #define NPCM4XX_I3C_MINTCLR_NOWMASTER 19 -#define NPCM4XX_I3C_MINTCLR_ERRWARN 15 -#define NPCM4XX_I3C_MINTCLR_IBIWON 13 +#define NPCM4XX_I3C_MINTCLR_ERRWARN 15 +#define NPCM4XX_I3C_MINTCLR_IBIWON 13 #define NPCM4XX_I3C_MINTCLR_TXNOTFULL 12 -#define NPCM4XX_I3C_MINTCLR_RXPEND 11 +#define NPCM4XX_I3C_MINTCLR_RXPEND 11 #define NPCM4XX_I3C_MINTCLR_COMPLETE 10 #define NPCM4XX_I3C_MINTCLR_MCTRLDONE 9 #define NPCM4XX_I3C_MINTCLR_SLVSTART 8 -#define NPCM4XX_I3C_MINTMASKED_NOWMASTER 19 -#define NPCM4XX_I3C_MINTMASKED_ERRWARN 15 -#define NPCM4XX_I3C_MINTMASKED_IBIWON 13 -#define NPCM4XX_I3C_MINTMASKED_TXNOTFULL 12 -#define NPCM4XX_I3C_MINTMASKED_RXPEND 11 -#define NPCM4XX_I3C_MINTMASKED_COMPLETE 10 -#define NPCM4XX_I3C_MINTMASKED_MCTRLDONE 9 -#define NPCM4XX_I3C_MINTMASKED_SLVSTART 8 +#define NPCM4XX_I3C_MINTMASKED_NOWMASTER 19 +#define NPCM4XX_I3C_MINTMASKED_ERRWARN 15 +#define NPCM4XX_I3C_MINTMASKED_IBIWON 13 +#define NPCM4XX_I3C_MINTMASKED_TXNOTFULL 12 +#define NPCM4XX_I3C_MINTMASKED_RXPEND 11 +#define NPCM4XX_I3C_MINTMASKED_COMPLETE 10 +#define NPCM4XX_I3C_MINTMASKED_MCTRLDONE 9 +#define NPCM4XX_I3C_MINTMASKED_SLVSTART 8 #define NPCM4XX_I3C_MERRWARN_TIMEOUT 20 -#define NPCM4XX_I3C_MERRWARN_INVREQ 19 -#define NPCM4XX_I3C_MERRWARN_MSGERR 18 -#define NPCM4XX_I3C_MERRWARN_OWRITE 17 -#define NPCM4XX_I3C_MERRWARN_OREAD 16 -#define NPCM4XX_I3C_MERRWARN_HCRC 10 -#define NPCM4XX_I3C_MERRWARN_HPAR 9 -#define NPCM4XX_I3C_MERRWARN_TERM 4 -#define NPCM4XX_I3C_MERRWARN_WRABT 3 -#define NPCM4XX_I3C_MERRWARN_NACK 2 -#define NPCM4XX_I3C_MDMACTRL_DMAWIDTH FIELD(4, 5) -#define NPCM4XX_I3C_MDMACTRL_DMATB FIELD(2, 3) -#define NPCM4XX_I3C_MDMACTRL_DMAFB FIELD(0, 1) +#define NPCM4XX_I3C_MERRWARN_INVREQ 19 +#define NPCM4XX_I3C_MERRWARN_MSGERR 18 +#define NPCM4XX_I3C_MERRWARN_OWRITE 17 +#define NPCM4XX_I3C_MERRWARN_OREAD 16 +#define NPCM4XX_I3C_MERRWARN_HCRC 10 +#define NPCM4XX_I3C_MERRWARN_HPAR 9 +#define NPCM4XX_I3C_MERRWARN_TERM 4 +#define NPCM4XX_I3C_MERRWARN_WRABT 3 +#define NPCM4XX_I3C_MERRWARN_NACK 2 +#define NPCM4XX_I3C_MDMACTRL_DMAWIDTH FIELD(4, 2) +#define NPCM4XX_I3C_MDMACTRL_DMATB FIELD(2, 2) +#define NPCM4XX_I3C_MDMACTRL_DMAFB FIELD(0, 2) #define NPCM4XX_I3C_MDATACTRL_RXEMPTY 31 #define NPCM4XX_I3C_MDATACTRL_TXFULL 30 -#define NPCM4XX_I3C_MDATACTRL_RXCOUNT FIELD(24, 28) -#define NPCM4XX_I3C_MDATACTRL_TXCOUNT FIELD(16, 20) -#define NPCM4XX_I3C_MDATACTRL_RXTRIG FIELD(6, 7) -#define NPCM4XX_I3C_MDATACTRL_TXTRIG FIELD(4, 5) +#define NPCM4XX_I3C_MDATACTRL_RXCOUNT FIELD(24, 5) +#define NPCM4XX_I3C_MDATACTRL_TXCOUNT FIELD(16, 5) +#define NPCM4XX_I3C_MDATACTRL_RXTRIG FIELD(6, 2) +#define NPCM4XX_I3C_MDATACTRL_TXTRIG FIELD(4, 2) #define NPCM4XX_I3C_MDATACTRL_UNLOCK 3 #define NPCM4XX_I3C_MDATACTRL_FLUSHFB 1 #define NPCM4XX_I3C_MDATACTRL_FLUSHTB 0 #define NPCM4XX_I3C_MWDATAB_END_A 16 #define NPCM4XX_I3C_MWDATAB_END_B 8 -#define NPCM4XX_I3C_MWDATAB_DATA FIELD(0, 7) -#define NPCM4XX_I3C_MWDATABE_DATA FIELD(0, 7) +#define NPCM4XX_I3C_MWDATAB_DATA FIELD(0, 8) +#define NPCM4XX_I3C_MWDATABE_DATA FIELD(0, 8) #define NPCM4XX_I3C_MWDATAH_END 16 -#define NPCM4XX_I3C_MWDATAH_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_MWDATAH_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_MWDATAHE_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_MWDATAHE_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_MRDATAB_DATA FIELD(0, 7) -#define NPCM4XX_I3C_MRDATAH_DATA1 FIELD(8, 15) -#define NPCM4XX_I3C_MRDATAH_DATA0 FIELD(0, 7) -#define NPCM4XX_I3C_MWDATAB1_DATA FIELD(0, 7) -#define NPCM4XX_I3C_MWMSG_SDR_CONTROL_LEN FIELD(11, 15) +#define NPCM4XX_I3C_MWDATAH_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_MWDATAH_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_MWDATAHE_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_MWDATAHE_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_MRDATAB_DATA FIELD(0, 8) +#define NPCM4XX_I3C_MRDATAH_DATA1 FIELD(8, 8) +#define NPCM4XX_I3C_MRDATAH_DATA0 FIELD(0, 8) +#define NPCM4XX_I3C_MWDATAB1_DATA FIELD(0, 8) +#define NPCM4XX_I3C_MWMSG_SDR_CONTROL_LEN FIELD(11, 5) #define NPCM4XX_I3C_MWMSG_SDR_CONTROL_I2C 10 #define NPCM4XX_I3C_MWMSG_SDR_CONTROL_END 8 #define NPCM4XX_I3C_MWMSG_SDR_CONTROL_ADDR FIELD(1, 7) #define NPCM4XX_I3C_MWMSG_SDR_CONTROL_DIR 0 -#define NPCM4XX_I3C_MWMSG_SDR_DATA_DATA16B FIELD(0, 15) -#define NPCM4XX_I3C_MRMSG_SDR_DATA FIELD(0, 15) -#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_END 14 -#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_LEN FIELD(0, 9) -#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_ADDR FIELD(9, 15) +#define NPCM4XX_I3C_MWMSG_SDR_DATA_DATA16B FIELD(0, 16) +#define NPCM4XX_I3C_MRMSG_SDR_DATA FIELD(0, 16) +#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_END 14 +#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_LEN FIELD(0, 10) +#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_ADDR FIELD(9, 7) #define NPCM4XX_I3C_MWMSG_DDR_CONTROL_DIR 7 -#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_CMD FIELD(0, 6) -#define NPCM4XX_I3C_MWMSG_DDR_DATA_DATA16B FIELD(0, 15) -#define NPCM4XX_I3C_MRMSG_DDR_DATA FIELD(0, 15) +#define NPCM4XX_I3C_MWMSG_DDR_CONTROL_CMD FIELD(0, 7) +#define NPCM4XX_I3C_MWMSG_DDR_DATA_DATA16B FIELD(0, 16) +#define NPCM4XX_I3C_MRMSG_DDR_DATA FIELD(0, 16) #define NPCM4XX_I3C_MDYNADDR_DADDR FIELD(1, 7) -#define NPCM4XX_I3C_MDYNADDR_DAVALID 0 -#define NPCM4XX_I3C_HDRCMD_NEWCMD 31 -#define NPCM4XX_I3C_HDRCMD_OVFLW 30 -#define NPCM4XX_I3C_HDRCMD_CMD0 FIELD(0, 7) -#define NPCM4XX_I3C_IBIEXT1_EXT3 FIELD(24, 31) -#define NPCM4XX_I3C_IBIEXT1_EXT2 FIELD(16, 23) -#define NPCM4XX_I3C_IBIEXT1_EXT1 FIELD(8, 15) -#define NPCM4XX_I3C_IBIEXT1_MAX FIELD(4, 6) -#define NPCM4XX_I3C_IBIEXT1_CNT FIELD(0, 2) -#define NPCM4XX_I3C_IBIEXT2_EXT7 FIELD(24, 31) -#define NPCM4XX_I3C_IBIEXT2_EXT6 FIELD(16, 23) -#define NPCM4XX_I3C_IBIEXT2_EXT5 FIELD(8, 15) -#define NPCM4XX_I3C_IBIEXT2_EXT4 FIELD(0, 7) -#define NPCM4XX_I3C_SID_ID FIELD(0, 31) +#define NPCM4XX_I3C_MDYNADDR_DAVALID 0 +#define NPCM4XX_I3C_HDRCMD_NEWCMD 31 +#define NPCM4XX_I3C_HDRCMD_OVFLW 30 +#define NPCM4XX_I3C_HDRCMD_CMD0 FIELD(0, 8) +#define NPCM4XX_I3C_IBIEXT1_EXT3 FIELD(24, 8) +#define NPCM4XX_I3C_IBIEXT1_EXT2 FIELD(16, 8) +#define NPCM4XX_I3C_IBIEXT1_EXT1 FIELD(8, 8) +#define NPCM4XX_I3C_IBIEXT1_MAX FIELD(4, 3) +#define NPCM4XX_I3C_IBIEXT1_CNT FIELD(0, 3) +#define NPCM4XX_I3C_IBIEXT2_EXT7 FIELD(24, 8) +#define NPCM4XX_I3C_IBIEXT2_EXT6 FIELD(16, 8) +#define NPCM4XX_I3C_IBIEXT2_EXT5 FIELD(8, 8) +#define NPCM4XX_I3C_IBIEXT2_EXT4 FIELD(0, 8) +#define NPCM4XX_I3C_SID_ID FIELD(0, 32) struct dsct_reg { __IO uint32_t CTL; From 3cecac996a7163408cfa6c050dd03b7e12956a1b Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 15 May 2024 22:15:55 -0700 Subject: [PATCH 2/2] drivers: i3c: npcm4xx: fix master mode xfer fail issues fix master mode xfer fail issues. 1. depend on MCLK frequency(96/48) to configure OD/PP setting. 2. check dev_descs instead of pDevList when xfer. dev_descs added when call i3c_master_attach_device() 3. return actual read length after xfer done. Signed-off-by: cpchiang --- drivers/i3c/i3c_npcm4xx.c | 205 +++++++++++++++++++++---------- drivers/i3c/npcm4xx/i3c_drv.h | 1 + drivers/i3c/npcm4xx/i3c_master.c | 1 + 3 files changed, 143 insertions(+), 64 deletions(-) diff --git a/drivers/i3c/i3c_npcm4xx.c b/drivers/i3c/i3c_npcm4xx.c index 25efc3cd91b615..8f9ddb29dbfcef 100644 --- a/drivers/i3c/i3c_npcm4xx.c +++ b/drivers/i3c/i3c_npcm4xx.c @@ -873,8 +873,6 @@ int8_t LoadBaudrateSetting(I3C_TRANSFER_TYPE_Enum type, uint32_t baudrate, uint3 */ void I3C_SetXferRate(I3C_TASK_INFO_t *pTaskInfo) { - bool bBroadcast = FALSE; - bool bSlaveFound = FALSE; uint32_t PPBAUD; uint32_t PPLOW; uint32_t ODBAUD; @@ -884,14 +882,18 @@ void I3C_SetXferRate(I3C_TASK_INFO_t *pTaskInfo) uint32_t mconfig; I3C_TRANSFER_TASK_t *pTask; - I3C_TRANSFER_PROTOCOL_Enum protocol; I3C_TRANSFER_FRAME_t *pFrame; - I3C_DEVICE_INFO_SHORT_t *pSlaveDevInfo = NULL; if (pTaskInfo == NULL) return; mconfig = I3C_GET_REG_MCONFIG(pTaskInfo->Port); + + PPBAUD = (mconfig & I3C_MCONFIG_PPBAUD_MASK) >> I3C_MCONFIG_PPBAUD_SHIFT; + PPLOW = (mconfig & I3C_MCONFIG_PPLOW_MASK) >> I3C_MCONFIG_PPLOW_SHIFT; + ODBAUD = (mconfig & I3C_MCONFIG_ODBAUD_MASK) >> I3C_MCONFIG_ODBAUD_SHIFT; + I2CBAUD = (mconfig & I3C_MCONFIG_I2CBAUD_MASK) >> I3C_MCONFIG_I2CBAUD_SHIFT; + mconfig &= ~(I3C_MCONFIG_I2CBAUD_MASK | I3C_MCONFIG_ODHPP_MASK | I3C_MCONFIG_ODBAUD_MASK | I3C_MCONFIG_PPLOW_MASK | I3C_MCONFIG_PPBAUD_MASK); @@ -901,49 +903,131 @@ void I3C_SetXferRate(I3C_TASK_INFO_t *pTaskInfo) if (pTask->frame_idx != 0) return; - protocol = pTask->protocol; pFrame = &(pTask->pFrameList[pTask->frame_idx]); - bBroadcast = (pTask->address == I3C_BROADCAST_ADDR) - || (protocol == I3C_TRANSFER_PROTOCOL_CCCb) - || (protocol == I3C_TRANSFER_PROTOCOL_CCCw) - || (protocol == I3C_TRANSFER_PROTOCOL_CCCr) - || (protocol == I3C_TRANSFER_PROTOCOL_ENTDAA) - || (protocol == I3C_TRANSFER_PROTOCOL_EVENT); - - if (bBroadcast && (pFrame->type != I3C_TRANSFER_TYPE_I2C) - && ((pFrame->flag & I3C_TRANSFER_REPEAT_START) == 0)) { + // update by frame setting + if ((pTask->frame_idx == 0) && ((pFrame->flag & I3C_TRANSFER_REPEAT_START) == 0) && + (pFrame->type != I3C_TRANSFER_TYPE_I2C) && (pFrame->address == 0x7E)) { ODHPP = 0; } - if (!bBroadcast) { - pSlaveDevInfo = pMasterDevice->pOwner->pDevList; - while (pSlaveDevInfo != NULL) { - if (pSlaveDevInfo->attr.b.runI3C) { - if (pSlaveDevInfo->dynamicAddr == pTask->address) - break; - } else { - if (pSlaveDevInfo->staticAddr == pTask->address) - break; - } - - pSlaveDevInfo = pSlaveDevInfo->pNextDev; + if (pFrame->type == I3C_TRANSFER_TYPE_I2C) { + switch(pFrame->baudrate) { + case I3C_TRANSFER_SPEED_I2C_1MHZ: + if (APB3_CLK == 96000000) { // 926 - 922 KHz + PPBAUD = 3; + PPLOW = 0; + ODBAUD = 12; + I2CBAUD = 0; + } else if (APB3_CLK == 48000000) { // 878 - 880 KHz + PPBAUD = 2; + PPLOW = 0; + ODBAUD = 8; + I2CBAUD = 0; + } + break; + case I3C_TRANSFER_SPEED_I2C_400KHZ: + if (APB3_CLK == 96000000) { // 371 - 369 KHz + PPBAUD = 9; + PPLOW = 0; + ODBAUD = 12; + I2CBAUD = 0; + } else if (APB3_CLK == 48000000) { // 340 - 338 KHz + PPBAUD = 9; + PPLOW = 0; + ODBAUD = 6; + I2CBAUD = 0; + } + break; + default: + if (APB3_CLK == 96000000) { // 98 - 96 KHz + PPBAUD = 15; + PPLOW = 0; + ODBAUD = 30; + I2CBAUD = 0; + } else if (APB3_CLK == 48000000) { // 98 - 97 KHz + PPBAUD = 2; + PPLOW = 0; + ODBAUD = 80; + I2CBAUD = 0; + } + break; } - - bSlaveFound = (pSlaveDevInfo != NULL); } - - if (bBroadcast) { - /* Can't make sure all slave device run in i3c mode ?*/ - /* PP=4MHz, OD Freq = 1MHz for I3C device before get dynamic address */ - PPBAUD = 5; - PPLOW = 0; - ODBAUD = 3; - I2CBAUD = 8; - } else if (bSlaveFound) { - if ((pSlaveDevInfo->attr.b.runI3C) == (pFrame->type != I3C_TRANSFER_TYPE_I2C)) { - LoadBaudrateSetting(pFrame->type, pFrame->baudrate, &PPBAUD, &PPLOW, - &ODBAUD, &I2CBAUD); + else + { + switch(pFrame->baudrate) { + case I3C_TRANSFER_SPEED_SDR_12p5MHZ: + // I3C PP=12.5MHz, OD Freq = 1MHz if ODHPP = 0 + if (APB3_CLK == 96000000) { + PPBAUD = 2; + PPLOW = 2; + ODBAUD = 15; + } else if (APB3_CLK == 48000000) { + PPBAUD = 0; + PPLOW = 2; + ODBAUD = 23; + } + break; + case I3C_TRANSFER_SPEED_SDR_8MHZ: + // I3C PP=8MHz, OD Freq = 1MHz if ODHPP = 0 + if (APB3_CLK == 96000000) { + PPBAUD = 2; + PPLOW = 6; + ODBAUD = 15; + } else if (APB3_CLK == 48000000) { + PPBAUD = 0; + PPLOW = 4; + ODBAUD = 23; + } + break; + case I3C_TRANSFER_SPEED_SDR_6MHZ: + // I3C PP=6MHz, OD Freq = 1MHz if ODHPP = 0 + if (APB3_CLK == 96000000) { + PPBAUD = 2; + PPLOW = 10; + ODBAUD = 15; + } else if (APB3_CLK == 48000000) { + PPBAUD = 1; + PPLOW = 4; + ODBAUD = 11; + } + break; + case I3C_TRANSFER_SPEED_SDR_4MHZ: + // I3C PP=4MHz, OD Freq = 1MHz if ODHPP = 0 + if (APB3_CLK == 96000000) { + PPBAUD = 5; + PPLOW = 12; + ODBAUD = 7; + } else if (APB3_CLK == 48000000) { + PPBAUD = 0; + PPLOW = 10; + ODBAUD = 23; + } + break; + case I3C_TRANSFER_SPEED_SDR_2MHZ: + // I3C PP=2MHz, OD Freq = 1MHz if ODHPP = 0 + if (APB3_CLK == 96000000) { + PPBAUD = 15; + PPLOW = 15; + ODBAUD = 2; + } else if (APB3_CLK == 48000000) { + PPBAUD = 4; + PPLOW = 14; + ODBAUD = 4; + } + break; + default: + if (APB3_CLK == 96000000) { + PPBAUD = 15; + PPLOW = 15; + ODBAUD = 5; + } else if (APB3_CLK == 48000000) { + PPBAUD = 15; + PPLOW = 15; + ODBAUD = 1; + } + break; } } @@ -2940,7 +3024,7 @@ int i3c_npcm4xx_master_priv_xfer(struct i3c_dev_desc *i3cdev, struct i3c_priv_xf I3C_BUS_INFO_t *pBus; I3C_DEVICE_INFO_t *pMaster; - I3C_DEVICE_INFO_SHORT_t *pSlaveDev; + struct i3c_dev_desc *pSlaveDev; if (!nxfers) { return 0; @@ -2962,20 +3046,10 @@ int i3c_npcm4xx_master_priv_xfer(struct i3c_dev_desc *i3cdev, struct i3c_priv_xf } Addr = obj->dev_addr_tbl[pos]; + pSlaveDev = obj->dev_descs[pos]; - /* find device node */ - pSlaveDev = pBus->pDevList; - while (pSlaveDev != NULL) { - if ((pSlaveDev->dynamicAddr == Addr) && (pSlaveDev->attr.b.runI3C == TRUE)) - break; - if ((pSlaveDev->staticAddr == Addr) && (pSlaveDev->attr.b.runI3C == FALSE)) - break; - pSlaveDev = pSlaveDev->pNextDev; - } - - if (pSlaveDev == NULL) { + if (pSlaveDev == NULL) return DEVICE_COUNT_MAX; - } cmds = (struct i3c_npcm4xx_cmd *)k_calloc(sizeof(struct i3c_npcm4xx_cmd), nxfers); __ASSERT(cmds, "failed to allocat cmd\n"); @@ -3015,8 +3089,8 @@ int i3c_npcm4xx_master_priv_xfer(struct i3c_dev_desc *i3cdev, struct i3c_priv_xf for (i = 0; i < nxfers; i++) { bWnR = (((i + 1) < nxfers) && (xfers[i].rnw == 0) && (xfers[i + 1].rnw == 1)); - Baudrate = (pSlaveDev->attr.b.runI3C) ? I3C_TRANSFER_SPEED_SDR_12p5MHZ : - I3C_TRANSFER_SPEED_I2C_100KHZ; + Baudrate = (pSlaveDev->info.i2c_mode) ? I3C_TRANSFER_SPEED_I2C_100KHZ : + I3C_TRANSFER_SPEED_SDR_12p5MHZ; /* Try to slow down for the fly line */ /* Baudrate = (pSlaveDev->attr.b.runI3C) ? I3C_TRANSFER_SPEED_SDR_6MHZ : */ @@ -3024,22 +3098,22 @@ int i3c_npcm4xx_master_priv_xfer(struct i3c_dev_desc *i3cdev, struct i3c_priv_xf if (!bWnR) { if (xfers[i].rnw) { - Protocol = (pSlaveDev->attr.b.runI3C) ? - I3C_TRANSFER_PROTOCOL_I3C_READ : - I3C_TRANSFER_PROTOCOL_I2C_READ; + Protocol = (pSlaveDev->info.i2c_mode) ? + I3C_TRANSFER_PROTOCOL_I2C_READ : + I3C_TRANSFER_PROTOCOL_I3C_READ; RxBuf = xfers[i].data.in; RxLen = xfers[i].len; } else { - Protocol = (pSlaveDev->attr.b.runI3C) ? - I3C_TRANSFER_PROTOCOL_I3C_WRITE : - I3C_TRANSFER_PROTOCOL_I2C_WRITE; + Protocol = (pSlaveDev->info.i2c_mode) ? + I3C_TRANSFER_PROTOCOL_I2C_WRITE : + I3C_TRANSFER_PROTOCOL_I3C_WRITE; TxBuf = xfers[i].data.out; TxLen = xfers[i].len; } } else { - Protocol = (pSlaveDev->attr.b.runI3C) ? - I3C_TRANSFER_PROTOCOL_I3C_WRITEnREAD : - I3C_TRANSFER_PROTOCOL_I2C_WRITEnREAD; + Protocol = (pSlaveDev->info.i2c_mode) ? + I3C_TRANSFER_PROTOCOL_I2C_WRITEnREAD : + I3C_TRANSFER_PROTOCOL_I3C_WRITEnREAD; TxBuf = xfers[i].data.out; TxLen = xfers[i].len; RxBuf = xfers[i + 1].data.in; @@ -3062,6 +3136,9 @@ int i3c_npcm4xx_master_priv_xfer(struct i3c_dev_desc *i3cdev, struct i3c_priv_xf if (bWnR) { i++; } + + if (xfers[i].rnw == 1) + xfers[i].len = xfer.rx_len; } } diff --git a/drivers/i3c/npcm4xx/i3c_drv.h b/drivers/i3c/npcm4xx/i3c_drv.h index a0a509f9cc0103..263b58b43b7606 100644 --- a/drivers/i3c/npcm4xx/i3c_drv.h +++ b/drivers/i3c/npcm4xx/i3c_drv.h @@ -69,6 +69,7 @@ struct i3c_npcm4xx_cmd { }; struct i3c_npcm4xx_xfer { int ret; + int rx_len; int ncmds; struct i3c_npcm4xx_cmd *cmds; struct k_sem sem; diff --git a/drivers/i3c/npcm4xx/i3c_master.c b/drivers/i3c/npcm4xx/i3c_master.c index 52a32c870e658d..540da74a4d7b80 100644 --- a/drivers/i3c/npcm4xx/i3c_master.c +++ b/drivers/i3c/npcm4xx/i3c_master.c @@ -233,6 +233,7 @@ __u32 I3C_Master_Callback(__u32 TaskInfo, __u32 ErrDetail) } ret = pTaskInfo->result; + xfer->rx_len = *pTask->pRdLen; I3C_Complete_Task(pTaskInfo); pBus->pCurrentTask = NULL; pBus->busState = I3C_BUS_STATE_IDLE;