From 1c77ac083d21e8f830977e5e5042587a3fee9d06 Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 10 Apr 2024 20:17:55 -0700 Subject: [PATCH 1/4] soc: arm: npcm4xx: change to use static definition to config crgpio when enable CONFIG_XIP, global variables copy from rom to ram after z_data_copy() be called. change to use static definition to config crgpio. Signed-off-by: cpchiang --- soc/arm/npcm4xx/npcm400f/soc.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/soc/arm/npcm4xx/npcm400f/soc.c b/soc/arm/npcm4xx/npcm400f/soc.c index 87d63adad298c9..a7f690215b7d7b 100644 --- a/soc/arm/npcm4xx/npcm400f/soc.c +++ b/soc/arm/npcm4xx/npcm400f/soc.c @@ -12,19 +12,16 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL); -uintptr_t scfg_base = DT_REG_ADDR_BY_IDX(DT_NODELABEL(scfg), 0); - void z_platform_init(void) { + uintptr_t scfg_base = SCFG_BASE_ADDR; struct scfg_reg *inst_scfg = (struct scfg_reg *)scfg_base; - if (scfg_base) { -#if CONFIG_GPIO_NPCM4XX_RESET_SL_POWER_UP - inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER; +#ifdef CONFIG_GPIO_NPCM4XX_RESET_SL_POWER_UP + inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_POWER; #else - inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE; + inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE; #endif - } } static int soc_init(const struct device *dev) From 107d35866053de1b062889012193ab76aa564bdf Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 10 Apr 2024 22:18:23 -0700 Subject: [PATCH 2/4] soc: arm: npcm4xx: script: remove invalid environment setting remove invalid environment setting. color command only available in windows environment. Signed-off-by: cpchiang --- soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py b/soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py index b08f064d23e984..370e3ace26ed8a 100644 --- a/soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py +++ b/soc/arm/npcm4xx/common/ImageGenerator/ImageGenerator.py @@ -2016,7 +2016,8 @@ def RemoveOTP(): # 0 NOTEST, 10 DEBUG, 20 INFO, 30 WARNING, 40 ERROR, 50 CRITICAL logging.basicConfig(level=20, format='%(asctime)s - %(levelname)s : %(message)s', filemode='w', filename='Log.txt') -os.system('color') +if sys.platform == "win32": + os.system('color') argv = sys.argv logging.info('User input : %s' % argv) From b2d075a6e7a105c34aa6a683c85e7873d9b9644a Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 10 Apr 2024 20:27:54 -0700 Subject: [PATCH 3/4] arch: arm: mpu: Make XN bit conditional on CONFIG_XIP for RAM region Make the execute never (XN) bit conditonal on CONFIG_XIP for the RAM MPU region attribute. This is required because when CONFIG_XIP is not set, the entire image will be linked into SRAM. In this case, SRAM must be executable. Signed-off-by: Daniel DeGrasse --- include/arch/arm/aarch32/mpu/arm_mpu_v7m.h | 8 +++++++- include/arch/arm/aarch32/mpu/arm_mpu_v8m.h | 9 ++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h b/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h index 50cacb8f95f17f..bd49959f3d9569 100644 --- a/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h +++ b/include/arch/arm/aarch32/mpu/arm_mpu_v7m.h @@ -109,11 +109,17 @@ #define REGION_2G REGION_SIZE(2GB) #define REGION_4G REGION_SIZE(4GB) + +/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When + * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep + * the SRAM region XN bit clear or the application code will not be executable. + */ + /* Some helper defines for common regions */ #define REGION_RAM_ATTR(size) \ { \ (NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \ - MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \ + IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \ } #define REGION_RAM_NOCACHE_ATTR(size) \ { \ diff --git a/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h b/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h index c4535699f0f6c7..b1b9ea84efbcc4 100644 --- a/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h +++ b/include/arch/arm/aarch32/mpu/arm_mpu_v8m.h @@ -118,9 +118,16 @@ * expected to be re-programmed or re-adjusted at run-time so * that they do not overlap with other MPU regions). */ + + +/* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When + * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep + * the SRAM region XN bit clear or the application code will not be executable. + */ + #define REGION_RAM_ATTR(base, size) \ {\ - .rbar = NOT_EXEC | \ + .rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) \ P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \ /* Cache-ability */ \ .mair_idx = MPU_MAIR_INDEX_SRAM, \ From 25294ceb3c561991c3fb40a9815c3712ed6574d1 Mon Sep 17 00:00:00 2001 From: cpchiang Date: Wed, 10 Apr 2024 23:25:02 -0700 Subject: [PATCH 4/4] soc: arm: npcm4xx: support MPU feature support MPU feature. 1. move copy sram vector table before config MPU. 2. place sram vector table to SECTIONS link. 3. add MPU range for sram vector table that used when program spim flash. Signed-off-by: cpchiang --- soc/arm/npcm4xx/common/CMakeLists.txt | 2 +- .../common/npcm4xx_sram_vector_table.ld | 7 ++- soc/arm/npcm4xx/npcm400f/CMakeLists.txt | 6 +++ soc/arm/npcm4xx/npcm400f/Kconfig.series | 2 + soc/arm/npcm4xx/npcm400f/mpu_regions.c | 51 +++++++++++++++++++ soc/arm/npcm4xx/npcm400f/soc.c | 4 +- 6 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 soc/arm/npcm4xx/npcm400f/mpu_regions.c diff --git a/soc/arm/npcm4xx/common/CMakeLists.txt b/soc/arm/npcm4xx/common/CMakeLists.txt index 903fc29fb0f573..bb83274a774896 100644 --- a/soc/arm/npcm4xx/common/CMakeLists.txt +++ b/soc/arm/npcm4xx/common/CMakeLists.txt @@ -12,7 +12,7 @@ zephyr_sources_ifdef(CONFIG_XIP ) zephyr_linker_sources_ifdef(CONFIG_XIP - RAM_SECTIONS + SECTIONS SORT_KEY 0 npcm4xx_sram_vector_table.ld ) diff --git a/soc/arm/npcm4xx/common/npcm4xx_sram_vector_table.ld b/soc/arm/npcm4xx/common/npcm4xx_sram_vector_table.ld index 60a33dc2794a75..795ef57b6eb237 100644 --- a/soc/arm/npcm4xx/common/npcm4xx_sram_vector_table.ld +++ b/soc/arm/npcm4xx/common/npcm4xx_sram_vector_table.ld @@ -3,8 +3,9 @@ * * SPDX-License-Identifier: Apache-2.0 */ -SECTION_PROLOGUE(.npcm4xx_sram_vector_table,,) +SECTION_DATA_PROLOGUE(.npcm4xx_sram_vector_table,,) { +_npcm4xx_sram_vector_begin = .; #if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR) /* * In an MCU with VTOR, the VTOR.TBLOFF is set to the start address of the @@ -29,6 +30,7 @@ SECTION_PROLOGUE(.npcm4xx_sram_vector_table,,) . = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) ); #endif +MPU_ALIGN(_npcm4xx_sram_vector_table_size); /* vector table from initial SP(0x00) to systick(0x3C) */ _npcm4xx_sram_vector_start = .; KEEP(*(.npcm4xx_exc_sram_vector_table)) @@ -44,6 +46,7 @@ _npcm4xx_sram_irq_vector_end = .; _npcm4xx_sram_vector_func_start = .; KEEP(*(.npcm4xx_sram_vector_func)) KEEP(*(".npcm4xx_sram_vector_func.*")) +MPU_ALIGN(_npcm4xx_sram_vector_table_size); _npcm4xx_sram_vector_func_end = .; } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION) @@ -54,4 +57,4 @@ _npcm4xx_sram_vector_func_end = .; _npcm4xx_sram_vector_table_size = _npcm4xx_sram_vector_func_end - _npcm4xx_sram_vector_start; /* use for load code from rom to sram */ -_npcm4xx_rom_vector_table_start = LOADADDR(.npcm4xx_sram_vector_table); +_npcm4xx_rom_vector_table_start = LOADADDR(.npcm4xx_sram_vector_table) + (_npcm4xx_sram_vector_start - _npcm4xx_sram_vector_begin); diff --git a/soc/arm/npcm4xx/npcm400f/CMakeLists.txt b/soc/arm/npcm4xx/npcm400f/CMakeLists.txt index ef311a1be7c1c3..733a499deaebb1 100644 --- a/soc/arm/npcm4xx/npcm400f/CMakeLists.txt +++ b/soc/arm/npcm4xx/npcm400f/CMakeLists.txt @@ -1,8 +1,14 @@ # SPDX-License-Identifier: Apache-2.0 zephyr_include_directories(${ZEPHYR_BASE}/drivers) +zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m) zephyr_sources( soc.c gdma.c ) + +zephyr_sources_ifdef( + CONFIG_ARM_MPU + mpu_regions.c +) diff --git a/soc/arm/npcm4xx/npcm400f/Kconfig.series b/soc/arm/npcm4xx/npcm400f/Kconfig.series index 7443ecaef48f9a..c722af933e55d8 100644 --- a/soc/arm/npcm4xx/npcm400f/Kconfig.series +++ b/soc/arm/npcm4xx/npcm400f/Kconfig.series @@ -10,5 +10,7 @@ config SOC_SERIES_NPCM400F select CPU_CORTEX_M_HAS_DWT select SOC_FAMILY_NPCM4XX select CORTEX_M_SYSTICK + select CPU_HAS_ARM_MPU + select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS help Enable support for Nuvoton NPCM400F series diff --git a/soc/arm/npcm4xx/npcm400f/mpu_regions.c b/soc/arm/npcm4xx/npcm400f/mpu_regions.c new file mode 100644 index 00000000000000..89a40f8c97b934 --- /dev/null +++ b/soc/arm/npcm4xx/npcm400f/mpu_regions.c @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2024 Nuvoton Technology Corporation. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#include "arm_mpu_mem_cfg.h" + +extern char _npcm4xx_sram_vector_start[]; + +/* Some helper defines for nuvton regions, the same attr with ramfunc */ +#define NUVOTON_REGION_RAM_RX_ATTR(size) \ + { \ + (NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \ + size | P_RO_U_RO_Msk) \ + } + +static const struct arm_mpu_region mpu_regions[] = { + /* Region 0 */ + MPU_REGION_ENTRY("FLASH_0", + CONFIG_FLASH_BASE_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, \ + CONFIG_FLASH_SIZE * 1024)), +#else + REGION_FLASH_ATTR(REGION_FLASH_SIZE)), +#endif + /* Region 1 */ + MPU_REGION_ENTRY("SRAM_0", + CONFIG_SRAM_BASE_ADDRESS, +#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE) + REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, \ + CONFIG_SRAM_SIZE * 1024)), +#else + REGION_RAM_ATTR(REGION_SRAM_SIZE)), +#endif + /* Region 2 ,use for sram vector table, size 512 bytes */ +#if defined(CONFIG_XIP) + MPU_REGION_ENTRY("SRAM_VECTOR_0", + (uint32_t)_npcm4xx_sram_vector_start, + NUVOTON_REGION_RAM_RX_ATTR(REGION_512B)), +#endif +}; + +const struct arm_mpu_config mpu_config = { + .num_regions = ARRAY_SIZE(mpu_regions), + .mpu_regions = mpu_regions, +}; diff --git a/soc/arm/npcm4xx/npcm400f/soc.c b/soc/arm/npcm4xx/npcm400f/soc.c index a7f690215b7d7b..501db5f92a13bb 100644 --- a/soc/arm/npcm4xx/npcm400f/soc.c +++ b/soc/arm/npcm4xx/npcm400f/soc.c @@ -22,14 +22,14 @@ void z_platform_init(void) #else inst_scfg->DEVALT10 = NPCM4XX_DEVALT10_CRGPIO_SELECT_SL_CORE; #endif + + npcm4xx_sram_vector_table_copy(); } static int soc_init(const struct device *dev) { ARG_UNUSED(dev); - npcm4xx_sram_vector_table_copy(); - return 0; }