From 55d37dcffa17aaa00e9c267a5e7984ff456c430c Mon Sep 17 00:00:00 2001
From: Thorsten de Buhr <thorstendb-ARM@users.noreply.github.com>
Date: Tue, 25 Jun 2024 12:34:37 +0200
Subject: [PATCH] Fixed: Message on check against sau num regions = 0 (#1582)

Fixed.
Checking sauNumRegions against sauRegion config:
- if set > 0 and regions are present: compare number against number of
regions. If there are moire regions than set, warning:
```
*** WARNING M391: /Users/thode01/work/github/devtools/build/tools/svdconv/SVDConv/darwin-arm64/Debug/ARMCM23.svd (Line 56)
  CPU: configured num of SAU regions '4' greater than <sauNumRegions> value: 1
```
- if set to 0 and regions are present, error:
```
*** ERROR M387: /Users/thode01/work/github/devtools/build/tools/svdconv/SVDConv/darwin-arm64/Debug/ARMCM23.svd (Line 56)
  CPU: <sauNumRegions> set to null but regions are configured.
```

Testfile:
```
<?xml version="1.0" encoding="utf-8"?>

<device schemaVersion="1.3" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd" >
  <vendor>ARM Ltd.</vendor>                                       <!-- device vendor name -->
  <vendorID>ARM</vendorID>                                        <!-- device vendor short name -->
  <name>ARMCM23</name>                                            <!-- name of part-->
  <series>ARMv8-M Baseline</series>                               <!-- device series the device belongs to -->
  <version>1.0</version>                                          <!-- version of this description, adding CMSIS-SVD 1.1 tags -->
  <description>ARM 32-bit Cortex-M23 based device.</description>
  <licenseText>                                                   <!-- this license text will appear in header file. \n force line breaks -->
    ARM Limited (ARM) is supplying this software for use with Cortex-M\n
    processor based microcontroller, but can be equally used for other\n
    suitable  processor architectures. This file can be freely distributed.\n
    Modifications to this file shall be clearly marked.\n
    \n
    THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED\n
    OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF\n
    MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.\n
    ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR\n
    CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  </licenseText>

  <cpu>                                                           <!-- details about the cpu embedded in the device -->
    <name>CM23</name>
    <revision>r0p0</revision>
    <endian>little</endian>
    <mpuPresent>true</mpuPresent>
    <fpuPresent>false</fpuPresent>
    <vtorPresent>true</vtorPresent>
    <nvicPrioBits>3</nvicPrioBits>
    <vendorSystickConfig>false</vendorSystickConfig>
    <sauNumRegions>0</sauNumRegions>
    <sauRegionsConfig enabled="true" protectionWhenDisabled="s">
      <region enabled="true" name="SauRegion0">
        <base>0x00000000</base>
        <limit>0x001FFFE0</limit>
        <!-- secure / non-secure callable -->
        <access>c</access>
      </region>
      <region enabled="true" name="SauRegion1">
        <base>0x00200000</base>
        <limit>0x003FFFE0</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
      <region enabled="true" name="SauRegion2">
        <base>0x20200000</base>
        <limit>0x203FFFE0</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
      <region enabled="true" name="SauRegion3">
        <base>0x40000000</base>
        <limit>0x40040000</limit>
        <!-- non-secure -->
        <access>n</access>
      </region>
    </sauRegionsConfig>
  </cpu>

  <addressUnitBits>8</addressUnitBits>                            <!-- byte addressable memory -->
  <width>32</width>                                               <!-- bus width is 32 bits -->
  <!-- default settings implicitly inherited by subsequent sections -->
  <size>32</size>                                                 <!-- this is the default size (number of bits) of all peripherals
                                                                       and register that do not define "size" themselves -->
  <access>read-write</access>                                     <!-- default access permission for all subsequent registers -->
  <resetValue>0x00000000</resetValue>                             <!-- by default all bits of the registers are initialized to 0 on reset -->
  <resetMask>0xFFFFFFFF</resetMask>                               <!-- by default all 32Bits of the registers are used -->

</device>
```
---
 tools/svdconv/SVDConv/src/SVDConv_Msgs.cpp | 3 ++-
 tools/svdconv/SVDModel/src/SvdCpu.cpp      | 9 ++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/tools/svdconv/SVDConv/src/SVDConv_Msgs.cpp b/tools/svdconv/SVDConv/src/SVDConv_Msgs.cpp
index 59336673f..e44c775b6 100644
--- a/tools/svdconv/SVDConv/src/SVDConv_Msgs.cpp
+++ b/tools/svdconv/SVDConv/src/SVDConv_Msgs.cpp
@@ -204,10 +204,11 @@ const MsgTable SvdConv::msgTable = {
   { "M384", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "Number of PMU Event Counters (found val: '%NUM%') not set or outside range [2..31]. Ignoring PMU entry."} },   // 14.02.2020
   { "M385", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "PMU not supported for CPU '%NAME%'"                                         } },   // 14.02.2020
   { "M386", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "Name not C compliant: '%NAME%' : Brackets [] found"                         } },
-  { "M387", { MsgLevel::LEVEL_ERROR,    CRLF_B,   ""                                                                           } },
+  { "M387", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "CPU: <sauNumRegions> set to 0 but regions are configured."               } },
   { "M388", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "MVE Floating-Point support is set but MVE is not set"                       } },
   { "M389", { MsgLevel::LEVEL_ERROR,    CRLF_B,   "Specified <deviceNumInterrupts>: '%NUM%' greater or equal '%NAME%': '%NUM2%'."} },   // 05.05.2020
   { "M390", { MsgLevel::LEVEL_WARNING3, CRLF_B,   "Checking IRQ '%NAME%': CPU unknown (see <cpu>). Assuming a maximum of %NUM% external Interrupts."} },    // 13.05.2020
+  { "M391", { MsgLevel::LEVEL_WARNING,  CRLF_B,   "CPU: configured number of SAU regions '%NUM%' greater than <sauNumRegions> value: '%NUM2%'"        } },
 
   // 500... SfrCC2 related Data modification Errors
   { "M500", { MsgLevel::LEVEL_ERROR,    CRLF_B,   ""                                                                            } },
diff --git a/tools/svdconv/SVDModel/src/SvdCpu.cpp b/tools/svdconv/SVDModel/src/SvdCpu.cpp
index 35493c5a1..ba5351185 100644
--- a/tools/svdconv/SVDModel/src/SvdCpu.cpp
+++ b/tools/svdconv/SVDModel/src/SvdCpu.cpp
@@ -336,16 +336,23 @@ bool SvdCpu::CheckItem()
       LogMsg("M363", lineNo);
       m_sauRegionsConfig->Invalidate();
     }
+    else if(m_sauNumRegions == 0) {
+      LogMsg("M387", lineNo);
+      m_sauRegionsConfig->Invalidate();
+    }
   }
 
   if(m_sauNumRegions != SvdItem::VALUE32_NOT_INIT) {
-    if(m_sauNumRegions == 0 || m_sauNumRegions > MAXNUM_SAU_REGIONS) {
+    if(m_sauNumRegions > MAXNUM_SAU_REGIONS) {
       LogMsg("M364", NUM(m_sauNumRegions), NUM2(MAXNUM_SAU_REGIONS), lineNo);
       m_sauNumRegions = SvdItem::VALUE32_NOT_INIT;
       if(m_sauRegionsConfig) {
         m_sauRegionsConfig->Invalidate();
       }
     }
+    else if(m_sauRegionsConfig && m_sauNumRegions < m_sauRegionsConfig->GetChildCount()) {
+      LogMsg("M391", NUM(m_sauRegionsConfig->GetChildCount()), NUM2(m_sauNumRegions),lineNo);
+    }
   }
 
   if(m_pmuPresent) {