You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
Is there a plan to develop a suite of RVV-optimized code that can be applied to various vector lengths (VLENs), rather than developing RVV-optimized code specific to certain VLENs for each processor with built-in vectors, , such as C910, X280, etc., shown as below in the Makefile.riscv64 file?
The text was updated successfully, but these errors were encountered:
Is there a plan to develop a suite of RVV-optimized code that can be applied to various vector lengths (VLENs), rather than developing RVV-optimized code specific to certain VLENs for each processor with built-in vectors, , such as C910, X280, etc., shown as below in the Makefile.riscv64 file?
The text was updated successfully, but these errors were encountered: