New uArch in RISC-V tree: required changes

[fleclairTT]

Currently writing up patches to enable support for the Tenstorrent Ascalon processor in its 8 wide configuration.

Outside of changes to Makefile.riscv64, param.h and cpuid_riscv64.c, what other changes are required within the RISC-V tree for basic target support?

I'm looking at doing a patch series for optimized kernels later on, but want to enable basic targetting first. Currently unsure what the workflow is for RISC-V.

[martin-frbg]

please see https://github.com/OpenMathLib/OpenBLAS/blob/develop/docs/developers.md#adding-dedicated-support-for-a-new-cpu-model - you need to add your new cpu name to TargetList.txt and clone the KERNEL configuration of an existing model, also put the hardware characteristics as another FORCE_cpuname block in getarch.c (and/or cmake/prebuild.cmake if you prefer CMake) so that make TARGET=yourcpu works in the absence of autodetection

[martin-frbg]

(I assume there are some fundamental differences between the Ascalon and what the more generic RISCV64-ZVL256B target was hoping to provide - but perhaps that could be the basis to include in your KERNEL.ASCALON)