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  (text "Place a 100nF cap close\nto each VDDIO pin.\n\nAll VDDIO pins must be\nconnected to the same\ntrace, connected to 3v3\nrail in a single point \nand bypassed with 10μ."
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  (label "DAC{SDA SCL}" (at 41.275 184.15 0)
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  (label "I^{2}C.SCL" (at 66.04 154.94 180)
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  (label "I^{2}C.SDA" (at 66.04 152.4 180)
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  (label "I^{2}S{MCK FS SCK SDI SDO}" (at 27.94 134.62 0)
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