From 032466f11d9151dd295287bca56be2e0087ac75c Mon Sep 17 00:00:00 2001
From: chengguanghui <wissycgh@gmail.com>
Date: Tue, 14 Jan 2025 11:37:47 +0800
Subject: [PATCH 1/2] fix(DM): standalonedm support apb

---
 .../scala/device/RocketDebugWrapper.scala     | 24 +++++++++++++++++++
 .../device/standalone/StandAloneDevice.scala  |  7 +++++-
 .../device/standalone/standalone_device.mk    |  4 ++++
 3 files changed, 34 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/device/RocketDebugWrapper.scala b/src/main/scala/device/RocketDebugWrapper.scala
index b2513e56ab..77b975cf00 100644
--- a/src/main/scala/device/RocketDebugWrapper.scala
+++ b/src/main/scala/device/RocketDebugWrapper.scala
@@ -45,6 +45,10 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
 //  debug.node := TLFragmenter() := peripheralXbar
   val debugCustomXbarOpt = p(DebugModuleKey).map(params => LazyModule( new DebugCustomXbar(outputRequiresInput = false)))
   debug.dmInner.dmInner.customNode := debugCustomXbarOpt.get.node
+  val apbDebugNodeOpt = p(ExportDebug).apb.option(APBMasterNode(Seq(APBMasterPortParameters(Seq(APBMasterParameters("debugAPB"))))))
+  (apbDebugNodeOpt zip debug.apbNodeOpt) foreach { case (master, slave) =>
+    slave := master
+  }
 
 //  debug.dmInner.dmInner.sb2tlOpt.foreach { sb2tl  =>
 //    l2xbar := TLBuffer() := TLWidthWidget(1) := sb2tl.node
@@ -74,6 +78,26 @@ class DebugModule(numCores: Int)(implicit p: Parameters) extends LazyModule {
     io.debugIO.extTrigger.foreach { x => debug.module.io.extTrigger.foreach {y => x <> y}}
     debug.module.io.ctrl.debugUnavail.foreach { _ := false.B }
 
+    io.debugIO.apb.zip(apbDebugNodeOpt).map{case(io, apbNodeOpt) =>
+      val apb =  apbNodeOpt.out(0)._1
+      apb.psel := io.psel
+      apb.penable := io.penable
+
+      apb.pwrite := io.pwrite
+      apb.paddr := io.paddr
+      apb.pprot := io.pprot
+      apb.pwdata := io.pwdata
+      apb.pstrb := io.pstrb
+      apb.pauser := io.pauser
+
+      io.pready := apb.pready
+      io.pslverr := apb.pslverr
+      io.prdata := apb.prdata
+      io.pduser := apb.pduser
+    }
+    debug.module.io.apb_clock.foreach(_ := io.debugIO.apb.get.clock)
+    debug.module.io.apb_reset.foreach(_ := io.debugIO.apb.get.reset)
+
     val dtm = io.debugIO.systemjtag.map(instantiateJtagDTM(_))
 
     def instantiateJtagDTM(sj: SystemJTAGIO): DebugTransportModuleJTAG = {
diff --git a/src/main/scala/device/standalone/StandAloneDevice.scala b/src/main/scala/device/standalone/StandAloneDevice.scala
index 03983c60a9..8485c93fca 100644
--- a/src/main/scala/device/standalone/StandAloneDevice.scala
+++ b/src/main/scala/device/standalone/StandAloneDevice.scala
@@ -22,7 +22,7 @@ import chisel3.experimental.{annotate, ChiselAnnotation}
 import chisel3.experimental.dataview._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.Parameters
-import freechips.rocketchip.devices.debug.DebugModuleKey
+import freechips.rocketchip.devices.debug._
 import freechips.rocketchip.devices.tilelink._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.tilelink._
@@ -169,6 +169,7 @@ object ArgParser {
     var firrtlOpts = Array[String]()
     var module: String = ""
     var useTL: Boolean = false
+    var useAPB: Boolean = false
     var baseAddress: BigInt = -1
     var addrWidth: Int = -1
     var dataWidth: Int = 64
@@ -185,6 +186,9 @@ object ArgParser {
         case "--use-axi4" :: tail =>
           useTL = false
           nextOption(tail)
+        case "--use-apb" :: tail =>
+          useAPB = true
+          nextOption(tail)
         case "--device-base-addr" :: value :: tail =>
           baseAddress = value match {
             case s"0x$hex" => BigInt(hex, 16)
@@ -222,6 +226,7 @@ object ArgParser {
           useTL, baseAddress, addrWidth, dataWidth, p(XSTileKey).size
         )(p)))(p.alter((site, here, up) => {
           case DebugModuleKey => up(DebugModuleKey).map(_.copy(baseAddress = baseAddress))
+          case ExportDebug    => up(ExportDebug).copy(protocols = (if(useAPB) Set(APB) else Set(JTAG)))
         }))
       case _: String => throw new IllegalArgumentException(s"$module not found")
     }
diff --git a/src/main/scala/device/standalone/standalone_device.mk b/src/main/scala/device/standalone/standalone_device.mk
index 070ecdca4a..6845a049a2 100644
--- a/src/main/scala/device/standalone/standalone_device.mk
+++ b/src/main/scala/device/standalone/standalone_device.mk
@@ -14,6 +14,10 @@ ifeq ($(DEVICE_AXI4),1)
 DEVICE_ARGS += --use-axi4
 endif
 
+ifeq ($(DEVICE_APB),1)
+DEVICE_ARGS += --use-apb
+endif
+
 ifneq ($(DEVICE_HART_NUM),)
 NUM_CORES = $(DEVICE_HART_NUM)
 endif

From b5de476322c93a5944f26811a95e7ea655288735 Mon Sep 17 00:00:00 2001
From: chengguanghui <wissycgh@gmail.com>
Date: Tue, 14 Jan 2025 11:38:45 +0800
Subject: [PATCH 2/2] submodule(rocket-chip): bump rocket-chip to support apb

---
 rocket-chip | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/rocket-chip b/rocket-chip
index 61a5be2607..aefa602ebf 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit 61a5be26075b1c4dad74250b20edd3a8d260a8de
+Subproject commit aefa602ebfad757f552223a7141d743e28792ef3