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Subtype Constraint in Entity Port Causes Error #9
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@bpadalino thanks for asked what can be done at pyVHDLParser. The repository is still in an alpha state (v0.4.x) and contains some known errors:
I think your example code is related to #6 . Currently the parser has problems when the subtype indication isn't followed by Lately I added a lot of documentation (see https://pyvhdlparser.readthedocs.io/en/latest/). have you started to dig into some details? I wanted to add more details soon, so interested contributors can easily understand how it works and how to debug. With regards to debugging I'm right now writing a functionality to export the internal data structures (linked lists / stream) to graphviz, so the parsed input can be displayed as SVG/PNG diagrams. Exporting tokens works fine, but exporting groups and tokens isn't done yet. If you like, this could be a first task, to get more familiar with the internal data structures before fixing bugs in the parser itself. I also started to upload testcases written with Pythons unittest. These are done for entities and architectures as well as tokens. The list of testcases could be expanded to:
Tests based on unittest are written in Python itself, the aforementioned test had been started as *.vhdl files, which should be translated to unittests. In general, I would like to get some help :) |
That looks great! Where in the code is that at? I can try to take a look at adding this type of output for groups and tokens as you suggested. As a note, I tried adding an initializer to my entity list, and it didn't seem to help the error. I didn't notice much in the documentation on how the parser worked. For example, The issue with the parsing is probably because I am passing in |
@bpadalino uploading an improved version, where you can study how I created the token stream diagram is currently blocked by Paebbels/pyAttributes#7. This fix is needed to slice the I also wrote down some notes on a paper, so I can explain to you how the parser and the states are working. |
@bpadalino so Paebbels/pyAttributes#7 is now closed and I pushed a version of pyVHDLParser, where next I'll write the docs how the |
As I pushed my updates, I found out, that ReadTheDocs isn't compiling my latest help pages, due to missing Python 3.8 support. I request an upgrade of my documentation repositories. I hope they do it soon. See readthedocs/readthedocs.org#6324 (comment) Nonetheless, I'll write more documentation. I was requested to also document the planned CodeDOM. |
I am running into the same issue, has anyone found a work-around? |
I'd like to help contribute to this project because I find there aren't enough VHDL parsers that are complete and open source, available for use in other projects.
This seems to be as good a place to start as any, so I cloned the repository and quickly found out the subtype constraint on an entity port doesn't pass the blockstreaming with the error
ERROR: Expected ';', ':=' or whitespace after subtype indication.
To be clear, this happens whenever the port has a constraint, like a range constraint:
s_axis_tdata : in std_logic_vector(31 downto 0);
.There are a lot of constraints which can apply to the subtype. I'm not necessarily worried about capturing them all, but I am interested in parsing out mostly entities and instantiations in code.
If you have a recommendation on where to look in the code to help add the capabilities, and a list of capabilities in order of precedence you want others to handle, I'd like to try to help out.
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