From 9960df4e68a0988008ea8c772f006e2c4ede2c7e Mon Sep 17 00:00:00 2001
From: "Rodrigo A. Melo" <rodrigomelo9@gmail.com>
Date: Mon, 13 Jan 2025 23:13:59 -0300
Subject: [PATCH] Workaround to ensure Docker can find files only under HOME or
 PWD

---
 README.md                      | 2 ++
 hdlconv/templates/docker.jinja | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 93964bb..e31a08b 100644
--- a/README.md
+++ b/README.md
@@ -3,6 +3,8 @@
 HDL converter (between VHDL, SystemVerilog and/or Verilog), based on [GHDL](https://github.com/ghdl/ghdl), [Yosys](https://github.com/YosysHQ/yosys), [Synlig](https://github.com/chipsalliance/synlig) and the plugins [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin) and [yosys-slang](https://github.com/povik/yosys-slang).
 It relies on [Docker](https://docs.docker.com/get-docker) and [PyFPGA containers](https://github.com/PyFPGA/containers).
 
+> Known limitation: the files must be located either under the `$HOME` directory or under the current working directory (`$PWD`) for Docker to be able to find and access them.
+
 * `vhdl2vhdl`: converts from a newer VHDL to VHDL'93 (using `ghdl`).
 * `vhdl2vlog`: converts from VHDL to Verilog (backends: `ghdl` or `yosys`).
 * `slog2vlog`: converts from SystemVerilog to Verilog (frontends: `slang`, `synlig` or `yosys`).
diff --git a/hdlconv/templates/docker.jinja b/hdlconv/templates/docker.jinja
index eac25fa..fbfcd27 100644
--- a/hdlconv/templates/docker.jinja
+++ b/hdlconv/templates/docker.jinja
@@ -1,2 +1,2 @@
 CONTAINER="ghcr.io/pyfpga/synthesis"
-DOCKER="docker run --rm -v $HOME:$HOME -w $PWD --user $(id -u):$(id -g) $CONTAINER"
+DOCKER="docker run --rm -v $HOME:$HOME -v $PWD:$PWD -w $PWD --user $(id -u):$(id -g) $CONTAINER"