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inPyHDI/Pyverilog (press backspace or delete to remove)

There are two types of coding style in module s ports declaration. FIRST: module module_name ( input in1, input in2, output out1); In ast output this is what i get: Description ModuleDef (name: module_name) ...
  • rahultanwar10
  • Opened 
    on Jan 30
  • #135

It would be great if there was API documentation for this library, and if it was mentioned in the README. The documentation can largely be auto-generated from the existing code.
  • parker-research
  • Opened 
    on Nov 28, 2024
  • #134

python3 Pyverilog/examples/example_graphgen.py -t top -s top.led test.v Generating LALR tables WARNING: 183 shift/reduce conflicts Traceback (most recent call last): File ./examples/example_graphgen.py ...
  • zhangshuaiAA9
  • 2
  • Opened 
    on Jul 13, 2024
  • #131

When a localparam is encountered in the ANSI style parameter declaration, a parsing error is reported. Example source verilog module a_module #( localparam A = 2 )( input [A-1:0] sig ); endmodule ...
  • mclark-iontra
  • Opened 
    on Jun 15, 2024
  • #129

Hello, Can the code generator handle arrays of the form wire [N:0] w_array [0:M] ?? Thanks in advance Capucine
  • CapucinedeBoissac
  • Opened 
    on Oct 30, 2023
  • #128

I had the same problem as issue #116 However, I was able to fix the problem by adding a new type of number with the provided structure. Already made a comment on said issue, but making a new one for visibility. ...
  • YSJL
  • Opened 
    on Oct 30, 2023
  • #127

when exculd: ast, directives = parse(file, preprocess_include= , preprocess_define= ) Got the following error: File C:\Users\Administrator\AppData\Roaming\Python\Python37\site-packages\pyverilog\vparser\parser.py ...
  • 1353369570
  • Opened 
    on Oct 20, 2023
  • #126

Hello, the following file could not be parsed: https://github.com/KatCe/pyverilog_issue_125/blob/main/picorv32_sv2v_out.v Got the following error: Pyverilog/pyverilog/vparser/parser.py , line 1589, ...
  • KatCe
  • Opened 
    on Oct 15, 2023
  • #125

Hello, the following module can not be parsed: module minimized_in ( clk_i, rst_ni, use_sign_i, sign_i, result_o ); input wire clk_i; input wire rst_ni; input wire use_sign_i; input wire sign_i; ...
  • KatCe
  • 1
  • Opened 
    on Oct 15, 2023
  • #124
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