diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f0/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f1/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f2/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f3/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h index b947b5eeb642..d95c78d92f6f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f4/i2c_hard_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -7,6 +7,7 @@ * Date Author Notes * 2024-02-06 Dyyt587 first version * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing */ #ifndef __I2C_HARD_CONFIG_H__ #define __I2C_HARD_CONFIG_H__ @@ -22,8 +23,7 @@ extern "C" { #define I2C1_BUS_CONFIG \ { \ .Instance = I2C1, \ - .timing=0x10707DBC, \ - .timeout=0x1000, \ + .timeout = 1000, \ .name = "hwi2c1", \ .evirq_type = I2C1_EV_IRQn, \ .erirq_type = I2C1_ER_IRQn, \ @@ -80,8 +80,7 @@ extern "C" { #define I2C2_BUS_CONFIG \ { \ .Instance = I2C2, \ - .timing=0x10707DBC, \ - .timeout=0x1000, \ + .timeout = 1000, \ .name = "hwi2c2", \ .evirq_type = I2C2_EV_IRQn, \ .erirq_type = I2C2_ER_IRQn, \ @@ -138,8 +137,7 @@ extern "C" { #define I2C3_BUS_CONFIG \ { \ .Instance = I2C3, \ - .timing=0x10707DBC, \ - .timeout=0x1000, \ + .timeout = 1000, \ .name = "hwi2c3", \ .evirq_type = I2C3_EV_IRQn, \ .erirq_type = I2C3_ER_IRQn, \ @@ -191,6 +189,64 @@ extern "C" { #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_RX_USING_DMA */ +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + #ifdef __cplusplus } #endif diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/f7/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g0/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/g4/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h5/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/dma_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/dma_config.h index 922bd0aa5a7f..13bdec081b42 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/dma_config.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/dma_config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -27,6 +27,13 @@ extern "C" { #define UART2_RX_DMA_REQUEST DMA_REQUEST_USART2_RX #define UART2_RX_DMA_IRQ DMA1_Stream0_IRQn #endif +#if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) +#define UART4_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler +#define UART4_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_RX_DMA_INSTANCE DMA1_Stream0 +#define UART4_RX_DMA_REQUEST DMA_REQUEST_UART4_RX +#define UART4_RX_DMA_IRQ DMA1_Stream0_IRQn +#endif /* DMA1 stream1 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) @@ -36,6 +43,13 @@ extern "C" { #define UART2_TX_DMA_REQUEST DMA_REQUEST_USART2_TX #define UART2_TX_DMA_IRQ DMA1_Stream1_IRQn #endif +#if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) +#define UART4_DMA_TX_IRQHandler DMA1_Stream1_IRQHandler +#define UART4_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART4_TX_DMA_INSTANCE DMA1_Stream1 +#define UART4_TX_DMA_REQUEST DMA_REQUEST_USART4_TX +#define UART4_TX_DMA_IRQ DMA1_Stream1_IRQn +#endif /* DMA1 stream2 */ #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) @@ -60,7 +74,13 @@ extern "C" { #define SPI2_TX_DMA_INSTANCE DMA1_Stream4 #define SPI2_TX_DMA_IRQ DMA1_Stream4_IRQn #endif - +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_DMA_RX_IRQHandler DMA1_Stream4_IRQHandler +#define UART1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART1_RX_DMA_INSTANCE DMA1_Stream4 +#define UART1_RX_DMA_REQUEST DMA_REQUEST_USART1_RX +#define UART1_RX_DMA_IRQ DMA1_Stream4_IRQn +#endif /* DMA1 stream5 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) @@ -69,8 +89,22 @@ extern "C" { #define SPI3_TX_DMA_INSTANCE DMA1_Stream5 #define SPI3_TX_DMA_IRQ DMA1_Stream5_IRQn #endif +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_DMA_TX_IRQHandler DMA1_Stream5_IRQHandler +#define UART1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define UART1_TX_DMA_INSTANCE DMA1_Stream5 +#define UART1_TX_DMA_REQUEST DMA_REQUEST_USART1_TX +#define UART1_TX_DMA_IRQ DMA1_Stream5_IRQn +#endif /* DMA1 stream6 */ +#if defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C_RX_DMA_INSTANCE) +#define I2C1_DMA_RX_IRQHandler DMA1_Stream6_IRQHandler +#define I2C1_RX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_RX_DMA_INSTANCE DMA1_Stream6 +#define I2C1_RX_DMA_REQUEST DMA_REQUEST_I2C1_RX +#define I2C1_RX_DMA_IRQ DMA1_Stream6_IRQn +#endif /* DMA1 stream7 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) @@ -79,6 +113,13 @@ extern "C" { #define SPI3_TX_DMA_INSTANCE DMA1_Stream7 #define SPI3_TX_DMA_IRQ DMA1_Stream7_IRQn #endif +#if defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler +#define I2C1_TX_DMA_RCC RCC_AHB1ENR_DMA1EN +#define I2C1_TX_DMA_INSTANCE DMA1_Stream7 +#define I2C1_TX_DMA_REQUEST DMA_REQUEST_I2C1_TX +#define I2C1_TX_DMA_IRQ DMA1_Stream7_IRQn +#endif /* DMA2 stream0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/h7/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l0/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l1/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l4/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/l5/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/u5/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wb/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/i2c_hard_config.h b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/i2c_hard_config.h new file mode 100644 index 000000000000..d95c78d92f6f --- /dev/null +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/config/wl/i2c_hard_config.h @@ -0,0 +1,254 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-02-06 Dyyt587 first version + * 2024-04-23 Zeidan Add I2Cx_xx_DMA_CONFIG + * 2024-06-23 wdfk-prog Removes timing + */ +#ifndef __I2C_HARD_CONFIG_H__ +#define __I2C_HARD_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_HARD_I2C1 +#ifndef I2C1_BUS_CONFIG +#define I2C1_BUS_CONFIG \ + { \ + .Instance = I2C1, \ + .timeout = 1000, \ + .name = "hwi2c1", \ + .evirq_type = I2C1_EV_IRQn, \ + .erirq_type = I2C1_ER_IRQn, \ + } +#endif /* I2C1_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C1 */ + +#ifdef BSP_I2C1_TX_USING_DMA +#ifndef I2C1_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .channel = I2C1_TX_DMA_CHANNEL \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_TX_DMA_RCC, \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .dma_irq = I2C1_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_TX_DMA_CONFIG */ +#endif /* BSP_I2C1_TX_USING_DMA */ + +#ifdef BSP_I2C1_RX_USING_DMA +#ifndef I2C1_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C1_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C1_RX_DMA_RCC, \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .dma_irq = I2C1_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C1_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C2 +#ifndef I2C2_BUS_CONFIG +#define I2C2_BUS_CONFIG \ + { \ + .Instance = I2C2, \ + .timeout = 1000, \ + .name = "hwi2c2", \ + .evirq_type = I2C2_EV_IRQn, \ + .erirq_type = I2C2_ER_IRQn, \ + } +#endif /* I2C2_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C2 */ + +#ifdef BSP_I2C2_TX_USING_DMA +#ifndef I2C2_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_TX_DMA_RCC, \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .dma_irq = I2C2_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_TX_DMA_CONFIG */ +#endif /* BSP_I2C2_TX_USING_DMA */ + +#ifdef BSP_I2C2_RX_USING_DMA +#ifndef I2C2_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C2_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C2_RX_DMA_RCC, \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .dma_irq = I2C2_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C2_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C3 +#ifndef I2C3_BUS_CONFIG +#define I2C3_BUS_CONFIG \ + { \ + .Instance = I2C3, \ + .timeout = 1000, \ + .name = "hwi2c3", \ + .evirq_type = I2C3_EV_IRQn, \ + .erirq_type = I2C3_ER_IRQn, \ + } +#endif /* I2C3_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C3 */ + +#ifdef BSP_I2C3_TX_USING_DMA +#ifndef I2C3_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_TX_DMA_RCC, \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .dma_irq = I2C3_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_TX_DMA_CONFIG */ +#endif /* BSP_I2C3_TX_USING_DMA */ + +#ifdef BSP_I2C3_RX_USING_DMA +#ifndef I2C3_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C3_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C3_RX_DMA_RCC, \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .dma_irq = I2C3_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C3_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_RX_USING_DMA */ + +#ifdef BSP_USING_HARD_I2C4 +#ifndef I2C4_BUS_CONFIG +#define I2C4_BUS_CONFIG \ + { \ + .Instance = I2C4, \ + .timeout = 1000, \ + .name = "hwi2c4", \ + .evirq_type = I2C4_EV_IRQn, \ + .erirq_type = I2C4_ER_IRQn, \ + } +#endif /* I2C4_BUS_CONFIG */ +#endif /* BSP_USING_HARD_I2C4 */ + +#ifdef BSP_I2C4_TX_USING_DMA +#ifndef I2C4_TX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_TX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_TX_DMA_RCC, \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .dma_irq = I2C4_TX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_TX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_TX_DMA_CONFIG */ +#endif /* BSP_I2C4_TX_USING_DMA */ + +#ifdef BSP_I2C4_RX_USING_DMA +#ifndef I2C4_RX_DMA_CONFIG +#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + } +#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) +#define I2C4_RX_DMA_CONFIG \ + { \ + .dma_rcc = I2C4_RX_DMA_RCC, \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .dma_irq = I2C4_RX_DMA_IRQ, \ + .request = DMA_REQUEST_I2C4_RX \ + } +#endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) */ +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__I2C_CONFIG_H__ */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c index 405644a36ddd..975b15a78e9f 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.c @@ -1,12 +1,13 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2024-02-17 Dyyt587 first version - * 2024-04-23 Zeidan fix bugs, test on STM32F429IGTx + * Date Author Notes + * 2024-02-17 Dyyt587 first version + * 2024-04-23 Zeidan fix bugs, test on STM32F429IGTx + * 2024-06-23 wdfk-prog Add blocking modes and distinguish POLL,INT,DMA modes */ #include @@ -16,14 +17,16 @@ #include "drv_config.h" #include -/* not fully support for I2C4 */ -#if defined(BSP_USING_HARD_I2C1) || defined(BSP_USING_HARD_I2C2) || defined(BSP_USING_HARD_I2C3) +#if defined(BSP_HARDWARE_I2C) -//#define DRV_DEBUG +// #define DRV_DEBUG #define LOG_TAG "drv.i2c.hw" #include -enum +//! The STM32 I2C is complex to calculate manually, and the default user uses a 100kHz configuration. +#define DEFAULT_BAUD_RATE (100*1000) //HZ + +typedef enum { #ifdef BSP_USING_HARD_I2C1 I2C1_INDEX, @@ -34,7 +37,10 @@ enum #ifdef BSP_USING_HARD_I2C3 I2C3_INDEX, #endif /* BSP_USING_HARD_I2C3 */ -}; +#ifdef BSP_USING_HARD_I2C4 + I2C4_INDEX, +#endif /* BSP_USING_HARD_I2C4 */ +}i2c_index_t; static struct stm32_i2c_config i2c_config[] = { @@ -47,6 +53,9 @@ static struct stm32_i2c_config i2c_config[] = #ifdef BSP_USING_HARD_I2C3 I2C3_BUS_CONFIG, #endif /* BSP_USING_HARD_I2C3 */ +#ifdef BSP_USING_HARD_I2C4 + I2C4_BUS_CONFIG, +#endif /* BSP_USING_HARD_I2C4 */ }; static struct stm32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; @@ -59,6 +68,11 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) I2C_HandleTypeDef *i2c_handle = &i2c_drv->handle; rt_memset(i2c_handle, 0, sizeof(I2C_HandleTypeDef)); struct stm32_i2c_config *cfg = i2c_drv->config; + if(cfg->timing == 0) + { + //! Please write the timing value, the default driver uses 100kHz + return -RT_EFAULT; + } i2c_handle->Instance = cfg->Instance; #if defined(SOC_SERIES_STM32H7) i2c_handle->Init.Timing = cfg->timing; @@ -72,13 +86,10 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) #if defined(SOC_SERIES_STM32H7) i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; #endif /* defined(SOC_SERIES_STM32H7) */ - i2c_handle->Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; + i2c_handle->Init.OwnAddress2 = 0; + i2c_handle->Init.OwnAddress2Masks = I2C_OA2_NOMASK; i2c_handle->Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; i2c_handle->Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - if (HAL_I2C_DeInit(i2c_handle) != HAL_OK) - { - return -RT_EFAULT; - } if (HAL_I2C_Init(i2c_handle) != HAL_OK) { @@ -97,8 +108,9 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) return -RT_EFAULT; } #endif /* defined(SOC_SERIES_STM32H7) */ +#if defined(RT_I2C_USING_DMA) /* I2C2 DMA Init */ - if (i2c_drv->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) + if (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) { HAL_DMA_Init(&i2c_drv->dma.handle_rx); @@ -109,7 +121,7 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) HAL_NVIC_EnableIRQ(i2c_drv->config->dma_rx->dma_irq); } - if (i2c_drv->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) + if (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) { HAL_DMA_Init(&i2c_drv->dma.handle_tx); @@ -119,12 +131,15 @@ static rt_err_t stm32_i2c_init(struct stm32_i2c *i2c_drv) HAL_NVIC_SetPriority(i2c_drv->config->dma_tx->dma_irq, 1, 0); HAL_NVIC_EnableIRQ(i2c_drv->config->dma_tx->dma_irq); } - - if (i2c_drv->i2c_dma_flag & I2C_USING_TX_DMA_FLAG || i2c_drv->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) +#endif /* defined(RT_I2C_USING_DMA) */ +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) + if ((i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX || i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) + || (i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_INT_TX || i2c_drv->i2c_dma_flag & RT_DEVICE_FLAG_INT_RX)) { HAL_NVIC_SetPriority(i2c_drv->config->evirq_type, 2, 0); HAL_NVIC_EnableIRQ(i2c_drv->config->evirq_type); } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ return RT_EOK; } @@ -150,7 +165,6 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, { /* for stm32 dma may more stability */ #define DMA_TRANS_MIN_LEN 2 /* only buffer length >= DMA_TRANS_MIN_LEN will use DMA mode */ -#define TRANS_TIMEOUT_PERSEC 8 /* per ms will trans nums bytes */ rt_int32_t i, ret; struct rt_i2c_msg *msg = msgs; @@ -158,16 +172,21 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, struct stm32_i2c *i2c_obj; uint32_t mode = 0; uint8_t next_flag = 0; - struct rt_completion *completion; rt_uint32_t timeout; if (num == 0) { return 0; } + +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) + struct rt_completion *completion; + completion = &i2c_obj->completion; +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ RT_ASSERT((msgs != RT_NULL) && (bus != RT_NULL)); i2c_obj = rt_container_of(bus, struct stm32_i2c, i2c_bus); - completion = &i2c_obj->completion; + RT_ASSERT(i2c_obj != RT_NULL); I2C_HandleTypeDef *handle = &i2c_obj->handle; + RT_ASSERT(handle != RT_NULL); LOG_D("xfer start %d mags", num); for (i = 0; i < (num - 1); i++) @@ -177,7 +196,7 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, LOG_D("xfer msgs[%d] addr=0x%2x buf=0x%x len= 0x%x flags= 0x%x", i, msg->addr, msg->buf, msg->len, msg->flags); next_msg = &msgs[i + 1]; next_flag = next_msg->flags; - timeout = msg->len/TRANS_TIMEOUT_PERSEC + 5; + timeout = msg->len / (bus->config.usage_freq / 1000) + 1 + 5; if (next_flag & RT_I2C_NO_START) { if ((next_flag & RT_I2C_RD) == (msg->flags & RT_I2C_RD)) @@ -201,56 +220,83 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, LOG_D("xfer rec msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" : "nuknown mode"); - if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) +#if defined(RT_I2C_USING_DMA) + if ((i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode); } else +#endif /* defined(RT_I2C_USING_DMA) */ +#if defined(RT_I2C_USING_INT) + if(i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_INT_RX) { ret = HAL_I2C_Master_Seq_Receive_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode); } + else +#endif /* defined(RT_I2C_USING_INT) */ +#if defined(RT_I2C_USING_POLL) + { + ret = HAL_I2C_Master_Receive(handle, (msg->addr<<1), msg->buf, msg->len, timeout); + } +#endif /* defined(RT_I2C_USING_POLL) */ if (ret != RT_EOK) { LOG_E("[%s:%d]I2C Read error(%d)!\n", __func__, __LINE__, ret); goto out; } +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) if (rt_completion_wait(completion, timeout) != RT_EOK) { LOG_D("receive time out"); goto out; } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ } else { LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" : "nuknown mode"); - if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) +#if defined(RT_I2C_USING_DMA) + if ((i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode); } else +#endif /* defined(RT_I2C_USING_DMA) */ +#if defined(RT_I2C_USING_INT) + if(i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_INT_TX) { ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode); } + else +#endif /* defined(RT_I2C_USING_INT) */ +#if defined(RT_I2C_USING_POLL) + { + ret = HAL_I2C_Master_Transmit(handle, (msg->addr<<1), msg->buf, msg->len, timeout); + } +#endif /* defined(RT_I2C_USING_POLL) */ if (ret != RT_EOK) { LOG_D("[%s:%d]I2C Write error(%d)!\n", __func__, __LINE__, ret); goto out; } +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) if (rt_completion_wait(completion, timeout) != RT_EOK) { LOG_D("transmit time out"); goto out; } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ } LOG_D("xfer next msgs[%d] addr=0x%2x buf= 0x%x len= 0x%x flags = 0x%x\r\n", i + 1, next_msg->addr, next_msg->buf, next_msg->len, next_msg->flags); } /* last msg */ msg = &msgs[i]; - timeout = msg->len/TRANS_TIMEOUT_PERSEC + 5; + // timeout= data_time + dev_addr_time + reserve_time + timeout = msg->len / (bus->config.usage_freq / 1000) + 1 + 5; if (msg->flags & RT_I2C_NO_STOP) mode = I2C_LAST_FRAME_NO_STOP; else @@ -261,49 +307,76 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, LOG_D("xfer rec msgs[%d] hal mode=%s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" : "nuknown mode"); - if ((i2c_obj->i2c_dma_flag & I2C_USING_RX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) +#if defined(RT_I2C_USING_DMA) + if ((i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = HAL_I2C_Master_Seq_Receive_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode); } else +#endif /* defined(RT_I2C_USING_DMA) */ +#if defined(RT_I2C_USING_INT) + if(i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_INT_RX) { + HAL_GPIO_WritePin(GPIOA, DEBUG_IO_Pin, GPIO_PIN_SET); ret = HAL_I2C_Master_Seq_Receive_IT(handle,(msg->addr<<1), msg->buf, msg->len, mode); } + else +#endif /* defined(RT_I2C_USING_INT) */ +#if defined(RT_I2C_USING_POLL) + { + ret = HAL_I2C_Master_Receive(handle, (msg->addr<<1), msg->buf, msg->len, timeout); + } +#endif /* defined(RT_I2C_USING_POLL) */ if (ret != RT_EOK) { LOG_D("[%s:%d]I2C Read error(%d)!\n", __func__, __LINE__, ret); goto out; } +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) if (rt_completion_wait(completion, timeout) != RT_EOK) { LOG_D("receive time out"); goto out; } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ } else { LOG_D("xfer trans msgs[%d] hal mode = %s", i, mode == I2C_FIRST_AND_NEXT_FRAME ? "I2C_FIRST_AND_NEXT_FRAME" : mode == I2C_LAST_FRAME ? "I2C_LAST_FRAME" : mode == I2C_LAST_FRAME_NO_STOP ? "I2C_FIRST_FRAME/I2C_LAST_FRAME_NO_STOP" : "nuknown mode"); - if ((i2c_obj->i2c_dma_flag & I2C_USING_TX_DMA_FLAG) && (msg->len >= DMA_TRANS_MIN_LEN)) +#if defined(RT_I2C_USING_DMA) + if ((i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (msg->len >= DMA_TRANS_MIN_LEN)) { ret = HAL_I2C_Master_Seq_Transmit_DMA(handle, (msg->addr<<1), msg->buf, msg->len, mode); } else +#endif /* defined(RT_I2C_USING_DMA) */ +#if defined(RT_I2C_USING_INT) + if(i2c_obj->i2c_dma_flag & RT_DEVICE_FLAG_INT_TX) { ret = HAL_I2C_Master_Seq_Transmit_IT(handle, (msg->addr<<1), msg->buf, msg->len, mode); } + else +#endif /* defined(RT_I2C_USING_INT) */ +#if defined(RT_I2C_USING_POLL) + { + ret = HAL_I2C_Master_Transmit(handle, (msg->addr<<1), msg->buf, msg->len, timeout); + } +#endif /* defined(RT_I2C_USING_POLL) */ if (ret != RT_EOK) { LOG_D("[%s:%d]I2C Write error(%d)!\n", __func__, __LINE__, ret); goto out; } +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) if (rt_completion_wait(completion, timeout) != RT_EOK) { LOG_D("transmit time out"); goto out; } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ } ret = num; LOG_D("xfer end %d mags\r\n", num); @@ -321,17 +394,54 @@ static rt_ssize_t stm32_i2c_master_xfer(struct rt_i2c_bus_device *bus, if (handle->ErrorCode == HAL_I2C_ERROR_BERR) { LOG_D("I2C BUS Error now stoped"); +#if defined(SOC_SERIES_STM32H7) + handle->Instance->CR1 |= I2C_IT_STOPI; +#else handle->Instance->CR1 |= I2C_CR1_STOP; +#endif /* defined(SOC_SERIES_STM32H7) */ ret=i-1; } return ret; } +rt_err_t stm_i2c_bus_control(struct rt_i2c_bus_device *bus, int cmd, void *args) +{ + struct stm32_i2c *i2c_obj; + RT_ASSERT(bus != RT_NULL); + + i2c_obj = rt_container_of(bus, struct stm32_i2c, i2c_bus); + RT_ASSERT(i2c_obj != RT_NULL); + + switch (cmd) + { + case BSP_I2C_CTRL_SET_TIMING: + { + rt_uint32_t timing = (rt_uint32_t)args; + if(timing > 0) + { + i2c_obj->config->timing = timing; + stm32_i2c_configure(&i2c_objs->i2c_bus); + } + else + { + return -RT_ERROR; + } + break; + } + + default: + { + break; + } + } + return -RT_EINVAL; +} + static const struct rt_i2c_bus_device_ops stm32_i2c_ops = { .master_xfer = stm32_i2c_master_xfer, RT_NULL, - RT_NULL + .i2c_bus_control = stm_i2c_bus_control, }; int RT_hw_i2c_bus_init(void) @@ -344,8 +454,11 @@ int RT_hw_i2c_bus_init(void) i2c_objs[i].i2c_bus.ops = &stm32_i2c_ops; i2c_objs[i].config = &i2c_config[i]; i2c_objs[i].i2c_bus.timeout = i2c_config[i].timeout; + i2c_objs[i].i2c_bus.config.max_hz = DEFAULT_BAUD_RATE; + i2c_objs[i].i2c_bus.config.usage_freq = DEFAULT_BAUD_RATE; - if (i2c_objs[i].i2c_dma_flag & I2C_USING_TX_DMA_FLAG) +#ifdef RT_I2C_USING_DMA + if (i2c_objs[i].i2c_dma_flag & RT_DEVICE_FLAG_DMA_TX) { i2c_objs[i].dma.handle_tx.Instance = i2c_config[i].dma_tx->Instance; #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) @@ -370,7 +483,7 @@ int RT_hw_i2c_bus_init(void) i2c_objs[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4; #endif /* defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7) */ } - if ((i2c_objs[i].i2c_dma_flag & I2C_USING_RX_DMA_FLAG)) + if (i2c_objs[i].i2c_dma_flag & RT_DEVICE_FLAG_DMA_RX) { i2c_objs[i].dma.handle_rx.Instance = i2c_config[i].dma_rx->Instance; #if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) @@ -412,51 +525,74 @@ int RT_hw_i2c_bus_init(void) #endif /* defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) */ UNUSED(tmpreg); /* To avoid compiler warnings */ } +#endif /* RT_I2C_USING_DMA */ +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) rt_completion_init(&i2c_objs[i].completion); +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ stm32_i2c_configure(&i2c_objs[i].i2c_bus); ret = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_objs[i].config->name); - RT_ASSERT(ret == RT_EOK); - LOG_D("%s bus init done", i2c_config[i].name); + if(ret != RT_EOK) + { + LOG_E("%s bus init failed %d", i2c_config[i].name, ret); + } + else + { + LOG_D("%s bus init done", i2c_config[i].name); + } } return ret; } -static void stm32_get_dma_info(void) + +static void stm32_get_info(void) { +#ifdef RT_I2C_USING_POLL + LOG_D("I2C using poll mode"); +#elif defined (RT_I2C_USING_INT) + for(i2c_index_t i = 0; i < sizeof(i2c_objs) / sizeof(i2c_objs[0]); i++) + { + i2c_objs[i].i2c_dma_flag |= RT_DEVICE_FLAG_INT_RX; + i2c_objs[i].i2c_dma_flag |= RT_DEVICE_FLAG_INT_TX; + } + LOG_D("I2C using interrupt mode"); +#elif defined (RT_I2C_USING_DMA) + LOG_D("I2C using DMA mode"); #ifdef BSP_I2C1_RX_USING_DMA - i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config I2C1_dma_rx = I2C1_RX_DMA_CONFIG; i2c_config[I2C1_INDEX].dma_rx = &I2C1_dma_rx; #endif /* BSP_I2C1_RX_USING_DMA */ #ifdef BSP_I2C1_TX_USING_DMA - i2c_objs[I2C1_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + i2c_objs[I2C1_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config I2C1_dma_tx = I2C1_TX_DMA_CONFIG; i2c_config[I2C1_INDEX].dma_tx = &I2C1_dma_tx; #endif /* BSP_I2C1_TX_USING_DMA */ #ifdef BSP_I2C2_RX_USING_DMA - i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config I2C2_dma_rx = I2C2_RX_DMA_CONFIG; i2c_config[I2C2_INDEX].dma_rx = &I2C2_dma_rx; #endif /* BSP_I2C2_RX_USING_DMA */ #ifdef BSP_I2C2_TX_USING_DMA - i2c_objs[I2C2_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + i2c_objs[I2C2_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config I2C2_dma_tx = I2C2_TX_DMA_CONFIG; i2c_config[I2C2_INDEX].dma_tx = &I2C2_dma_tx; #endif /* BSP_I2C2_TX_USING_DMA */ #ifdef BSP_I2C3_RX_USING_DMA - i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_RX_DMA_FLAG; + i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config I2C3_dma_rx = I2C3_RX_DMA_CONFIG; i2c_config[I2C3_INDEX].dma_rx = &I2C3_dma_rx; #endif /* BSP_I2C3_RX_USING_DMA */ #ifdef BSP_I2C3_TX_USING_DMA - i2c_objs[I2C3_INDEX].i2c_dma_flag |= I2C_USING_TX_DMA_FLAG; + i2c_objs[I2C3_INDEX].i2c_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config I2C3_dma_tx = I2C3_TX_DMA_CONFIG; i2c_config[I2C3_INDEX].dma_tx = &I2C3_dma_tx; #endif /* BSP_I2C3_TX_USING_DMA */ +#endif /* RT_I2C_USING_POLL */ } +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) { struct stm32_i2c *i2c_drv = rt_container_of(hi2c, struct stm32_i2c, handle); @@ -464,6 +600,7 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) } void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) { + HAL_GPIO_WritePin(GPIOA, DEBUG_IO_Pin, GPIO_PIN_RESET); struct stm32_i2c *i2c_drv = rt_container_of(hi2c, struct stm32_i2c, handle); rt_completion_done(&i2c_drv->completion); } @@ -482,39 +619,41 @@ void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) hi2c->Instance->CR1 |= I2C_IT_STOPI; } #endif /* defined(SOC_SERIES_STM32H7) */ - } +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ + +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) #ifdef BSP_USING_HARD_I2C1 /** - * @brief This function handles I2C2 event interrupt. + * @brief This function handles I2C1 event interrupt. */ void I2C1_EV_IRQHandler(void) { - /* USER CODE BEGIN I2C2_EV_IRQn 0 */ + /* USER CODE BEGIN I2C1_EV_IRQn 0 */ /* enter interrupt */ rt_interrupt_enter(); - /* USER CODE END I2C2_EV_IRQn 0 */ + /* USER CODE END I2C1_EV_IRQn 0 */ HAL_I2C_EV_IRQHandler(&i2c_objs[I2C1_INDEX].handle); - /* USER CODE BEGIN I2C2_EV_IRQn 1 */ + /* USER CODE BEGIN I2C1_EV_IRQn 1 */ /* leave interrupt */ rt_interrupt_leave(); - /* USER CODE END I2C2_EV_IRQn 1 */ + /* USER CODE END I2C1_EV_IRQn 1 */ } /** - * @brief This function handles I2C2 error interrupt. + * @brief This function handles I2C1 error interrupt. */ void I2C1_ER_IRQHandler(void) { - /* USER CODE BEGIN I2C2_ER_IRQn 0 */ + /* USER CODE BEGIN I2C1_ER_IRQn 0 */ /* enter interrupt */ rt_interrupt_enter(); - /* USER CODE END I2C2_ER_IRQn 0 */ + /* USER CODE END I2C1_ER_IRQn 0 */ HAL_I2C_ER_IRQHandler(&i2c_objs[I2C1_INDEX].handle); - /* USER CODE BEGIN I2C2_ER_IRQn 1 */ + /* USER CODE BEGIN I2C1_ER_IRQn 1 */ /* leave interrupt */ rt_interrupt_leave(); - /* USER CODE END I2C2_ER_IRQn 1 */ + /* USER CODE END I2C1_ER_IRQn 1 */ } #endif /* BSP_USING_HARD_I2C1 */ @@ -554,38 +693,73 @@ void I2C2_ER_IRQHandler(void) #ifdef BSP_USING_HARD_I2C3 /** - * @brief This function handles I2C2 event interrupt. + * @brief This function handles I2C3 event interrupt. */ void I2C3_EV_IRQHandler(void) { - /* USER CODE BEGIN I2C2_EV_IRQn 0 */ + /* USER CODE BEGIN I2C3_EV_IRQn 0 */ /* enter interrupt */ rt_interrupt_enter(); - /* USER CODE END I2C2_EV_IRQn 0 */ + /* USER CODE END I2C3_EV_IRQn 0 */ HAL_I2C_EV_IRQHandler(&i2c_objs[I2C3_INDEX].handle); - /* USER CODE BEGIN I2C2_EV_IRQn 1 */ + /* USER CODE BEGIN I2C3_EV_IRQn 1 */ /* leave interrupt */ rt_interrupt_leave(); - /* USER CODE END I2C2_EV_IRQn 1 */ + /* USER CODE END I2C3_EV_IRQn 1 */ } /** - * @brief This function handles I2C2 error interrupt. + * @brief This function handles I2C3 error interrupt. */ void I2C3_ER_IRQHandler(void) { - /* USER CODE BEGIN I2C2_ER_IRQn 0 */ + /* USER CODE BEGIN I2C3_ER_IRQn 0 */ /* enter interrupt */ rt_interrupt_enter(); - /* USER CODE END I2C2_ER_IRQn 0 */ + /* USER CODE END I2C3_ER_IRQn 0 */ HAL_I2C_ER_IRQHandler(&i2c_objs[I2C3_INDEX].handle); - /* USER CODE BEGIN I2C2_ER_IRQn 1 */ + /* USER CODE BEGIN I2C3_ER_IRQn 1 */ /* leave interrupt */ rt_interrupt_leave(); /* USER CODE END I2C2_ER_IRQn 1 */ } #endif /* BSP_USING_HARD_I2C3 */ +#ifdef BSP_USING_HARD_I2C4 +/** + * @brief This function handles I2C4 event interrupt. + */ +void I2C4_EV_IRQHandler(void) +{ + /* USER CODE BEGIN I2C4_EV_IRQn 0 */ + /* enter interrupt */ + rt_interrupt_enter(); + /* USER CODE END I2C4_EV_IRQn 0 */ + HAL_I2C_EV_IRQHandler(&i2c_objs[I2C4_INDEX].handle); + /* USER CODE BEGIN I2C4_EV_IRQn 1 */ + /* leave interrupt */ + rt_interrupt_leave(); + /* USER CODE END I2C4_EV_IRQn 1 */ +} + +/** + * @brief This function handles I2C4 error interrupt. + */ +void I2C4_ER_IRQHandler(void) +{ + /* USER CODE BEGIN I2C4_ER_IRQn 0 */ + /* enter interrupt */ + rt_interrupt_enter(); + /* USER CODE END I2C4_ER_IRQn 0 */ + HAL_I2C_ER_IRQHandler(&i2c_objs[I2C4_INDEX].handle); + /* USER CODE BEGIN I2C4_ER_IRQn 1 */ + /* leave interrupt */ + rt_interrupt_leave(); + /* USER CODE END I2C4_ER_IRQn 1 */ +} +#endif /* BSP_USING_HARD_I2C4 */ +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ + #if defined(BSP_USING_HARD_I2C1) && defined(BSP_I2C1_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. @@ -694,7 +868,7 @@ void I2C3_DMA_TX_IRQHandler(void) } #endif /* defined(BSP_USING_HARD_I2C3) && defined(BSP_I2C3_TX_USING_DMA) */ -#if defined(BSP_USING_I2C4) && defined(BSP_I2C4_RX_USING_DMA) +#if defined(BSP_USING_HARD_I2C4) && defined(BSP_I2C4_RX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -710,9 +884,9 @@ void I2C4_DMA_RX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_USING_I2C4) && defined(BSP_I2C4_RX_USING_DMA) */ +#endif /* defined(BSP_USING_HARD_I2C4) && defined(BSP_I2C4_RX_USING_DMA) */ -#if defined(BSP_USING_I2C4) && defined(BSP_I2C4_TX_USING_DMA) +#if defined(BSP_USING_HARD_I2C4) && defined(BSP_I2C4_TX_USING_DMA) /** * @brief This function handles DMA Rx interrupt request. * @param None @@ -728,13 +902,13 @@ void I2C4_DMA_TX_IRQHandler(void) /* leave interrupt */ rt_interrupt_leave(); } -#endif /* defined(BSP_USING_I2C4) && defined(BSP_I2C4_TX_USING_DMA) */ +#endif /* defined(BSP_USING_HARD_I2C4) && defined(BSP_I2C4_TX_USING_DMA) */ int rt_hw_hw_i2c_init(void) { - stm32_get_dma_info(); + stm32_get_info(); return RT_hw_i2c_bus_init(); } INIT_CORE_EXPORT(rt_hw_hw_i2c_init); -#endif /* defined(BSP_USING_HARD_I2C1) || defined(BSP_USING_HARD_I2C2) || defined(BSP_USING_HARD_I2C3) */ +#endif /* defined(BSP_HARDWARE_I2C) */ diff --git a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h index 5e91a26471f0..b9b9abc654df 100644 --- a/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h +++ b/bsp/stm32/libraries/HAL_Drivers/drivers/drv_hard_i2c.h @@ -1,11 +1,12 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2024, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: - * Date Author Notes - * 2024-02-17 Dyyt587 first version + * Date Author Notes + * 2024-02-17 Dyyt587 first version + * 2024-06-23 wdfk-prog Add timing Settings */ #ifndef __DRV_HARD_I2C_H__ @@ -26,36 +27,41 @@ extern "C" { #endif +#define BSP_I2C_CTRL_SET_TIMING 0x40 + struct stm32_i2c_config { const char *name; - I2C_TypeDef *Instance; - rt_uint32_t timing; + I2C_TypeDef *Instance; + rt_uint32_t timing; rt_uint32_t timeout; - IRQn_Type evirq_type; - IRQn_Type erirq_type; - struct dma_config *dma_rx, *dma_tx; + IRQn_Type evirq_type; + IRQn_Type erirq_type; +#ifdef RT_I2C_USING_DMA + struct dma_config *dma_rx; + struct dma_config *dma_tx; +#endif /* RT_I2C_USING_DMA */ }; struct stm32_i2c { - I2C_HandleTypeDef handle; + I2C_HandleTypeDef handle; + struct stm32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; + rt_uint16_t i2c_dma_flag; +#if defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) + struct rt_completion completion; +#endif /* defined(RT_I2C_USING_INT) || defined(RT_I2C_USING_DMA) */ +#ifdef RT_I2C_USING_DMA struct { DMA_HandleTypeDef handle_rx; DMA_HandleTypeDef handle_tx; } dma; - struct stm32_i2c_config *config; - struct rt_i2c_bus_device i2c_bus; - rt_uint8_t i2c_dma_flag; - struct rt_completion completion; - +#endif /* RT_I2C_USING_DMA */ }; -#define I2C_USING_TX_DMA_FLAG (1U) -#define I2C_USING_RX_DMA_FLAG (1U << 1) - #ifdef __cplusplus } #endif diff --git a/bsp/stm32/stm32h750-artpi/board/Kconfig b/bsp/stm32/stm32h750-artpi/board/Kconfig index 0358b44c74ba..9faa4d56e294 100644 --- a/bsp/stm32/stm32h750-artpi/board/Kconfig +++ b/bsp/stm32/stm32h750-artpi/board/Kconfig @@ -1,372 +1,614 @@ menu "Hardware Drivers Config" + config BOARD_STM32H750_ARTPI + bool + select SOC_STM32H750XB + default y -menu "Board extended module" - - menuconfig ART_PI_USING_MEDIA_IO - bool "Media-IO" - default n - if ART_PI_USING_MEDIA_IO - config BSP_USING_SPI_LCD_ILI9488 - bool - config PKG_USING_PERSIMMON_SRC - bool + config SOC_STM32H750XB + bool + select SOC_SERIES_STM32H7 + select SOC_FAMILY_STM32 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select RT_USING_CACHE + select BSP_SCB_ENABLE_I_CACHE + select BSP_SCB_ENABLE_D_CACHE + + config SOC_SERIES_STM32H7 + bool + select ARCH_ARM_CORTEX_M7 - config MEDIA_IO_USING_SCREEN - select BSP_USING_SPI - select BSP_USING_SPI2 - select BSP_USING_SDRAM - select BSP_USING_SPI_LCD_ILI9488 - select PKG_USING_PERSIMMON_SRC - bool "Enable Screen" - default y + config SOC_FAMILY_STM32 + bool + config BSP_SCB_ENABLE_I_CACHE + bool + config BSP_SCB_ENABLE_D_CACHE + bool - if MEDIA_IO_USING_SCREEN - config BSP_USING_LVGL - bool "Enable LVGL for LCD" + menu "Board extended module" + + menuconfig ART_PI_USING_MEDIA_IO + bool "Media-IO" + default n + if ART_PI_USING_MEDIA_IO + config BSP_USING_SPI_LCD_ILI9488 + bool + config PKG_USING_PERSIMMON_SRC + bool + + config MEDIA_IO_USING_SCREEN + select BSP_USING_SPI + select BSP_USING_SPI2 + select BSP_USING_SDRAM select BSP_USING_SPI_LCD_ILI9488 - select PKG_USING_LVGL - select PKG_USING_LV_MUSIC_DEMO + select PKG_USING_PERSIMMON_SRC + bool "Enable Screen" + default y + config MEDIA_IO_USING_TOUCH + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select BSP_USING_I2C + select BSP_USING_I2C2 + select PKG_USING_TOUCH_DRIVERS + select PKG_USING_FT6236 + bool "Enable Touch" + default y + config MEDIA_IO_USING_AUDIO + select RT_USING_AUDIO + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select BSP_USING_I2C + select BSP_USING_I2C3 + bool "Enable Audio" + default y + if MEDIA_IO_USING_AUDIO + config AUDIO_MP3 + bool "Support MP3" + select PKG_USING_HELIX + default y + endif + endif + + menuconfig ART_PI_USING_INDUSTRY_IO + bool "Industry-IO" + default n + if ART_PI_USING_INDUSTRY_IO + config INDUSTRY_IO_USING_ETH + select BSP_USING_ETH + select PHY_USING_LAN8720A + bool "Enable Ethernet" + default y + endif + + menuconfig ART_PI_USING_LORA_SHIELD_LRS007 + bool "LoRa Shield" + default n + if ART_PI_USING_LORA_SHIELD_LRS007 + config ART_PI_USING_LORA_SHIELD_LRS007_RF_A + select BSP_USING_SPI + select BSP_USING_SPI2 + bool "Enable LRS007 RF_A Channel" + default n + config ART_PI_USING_LORA_SHIELD_LRS007_RF_B + select BSP_USING_SPI + select BSP_USING_SPI4 + bool "Enable LRS007 RF_B Channel" default n endif - - config MEDIA_IO_USING_TOUCH - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select BSP_USING_I2C - select BSP_USING_I2C2 - select PKG_USING_FT6236 - bool "Enable Touch" - default y - - config MEDIA_IO_USING_AUDIO - select RT_USING_AUDIO - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select BSP_USING_I2C - select BSP_USING_I2C3 - bool "Enable Audio" - default y - if MEDIA_IO_USING_AUDIO - config AUDIO_MP3 - bool "Support MP3" - select PKG_USING_HELIX + + endmenu + + menu "Onboard Peripheral" + + config BSP_USING_USB_TO_USART + bool "Enable Debuger USART (uart4)" + select BSP_USING_UART + select BSP_USING_UART4 + default n + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select RT_USING_FAL + select FAL_USING_SFUD_PORT + select RT_USING_SFUD + default n + + config BSP_USING_QSPI_FLASH + bool "Enable QSPI FLASH (w25q64 qspi)" + select BSP_USING_QSPI + select FAL_USING_SFUD_PORT + select RT_USING_SFUD + select RT_SFUD_USING_QSPI + default n + + config BSP_USING_WIFI + bool "Enable wifi (AP6212)" + select ART_PI_USING_WIFI_6212_LIB + select ART_PI_USING_OTA_LIB + select BSP_USING_SPI_FLASH + select RT_USING_WIFI + select RT_USING_SAL + default n + + config BSP_USING_OV2640 + bool "Enable camera (ov2640)" + select BSP_USING_DCMI + select BSP_USING_I2C + select BSP_USING_I2C2 + default n + + config BSP_USING_GC0328C + bool "Enable camera (gc0328)" + select BSP_USING_DCMI + select BSP_USING_I2C + select BSP_USING_I2C2 + default n + + menuconfig BSP_USING_FS + bool "Enable filesystem" + select RT_USING_DFS + select RT_USING_DFS_ROMFS + default n + if BSP_USING_FS + config BSP_USING_SDCARD_FS + bool "Enable SDCARD filesystem" + select BSP_USING_SDIO + select BSP_USING_SDIO1 + select RT_USING_DFS_ELMFAT + default n + config BSP_USING_SPI_FLASH_FS + bool "Enable SPI FLASH filesystem" + select BSP_USING_SPI_FLASH + select RT_USING_MTD_NOR + select PKG_USING_LITTLEFS + default n + endif + + endmenu + + menu "On-chip Peripheral" + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + config BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + endif + + config BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_USING_DMA + bool "Enable UART3 RX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_TX_USING_DMA + bool "Enable UART3 TX DMA" + depends on BSP_USING_UART3 && RT_SERIAL_USING_DMA + default n + + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + config BSP_USING_UART4 + bool "Enable UART4 (Debugger)" default y - endif - endif - - menuconfig ART_PI_USING_INDUSTRY_IO - bool "Industry-IO" - default n - if ART_PI_USING_INDUSTRY_IO - config INDUSTRY_IO_USING_ETH - select BSP_USING_ETH - select PHY_USING_LAN8720A - bool "Enable Ethernet" - default y - endif - -endmenu - -menu "Onboard Peripheral Drivers" - - config BSP_USING_USB_TO_USART - bool "Enable Debuger USART (uart4)" - select BSP_USING_UART - select BSP_USING_UART4 - default n - - config BSP_USING_SPI_FLASH - bool "Enable SPI FLASH (spi1)" - select BSP_USING_SPI - select BSP_USING_SPI1 - select RT_USING_FAL - select FAL_USING_SFUD_PORT - select RT_USING_SFUD - default n - - config BSP_USING_QSPI_FLASH - bool "Enable QSPI FLASH (w25q64 qspi)" - select BSP_USING_QSPI - select FAL_USING_SFUD_PORT - select RT_USING_SFUD - select RT_SFUD_USING_QSPI - default n - - menuconfig BSP_USING_FS - bool "Enable filesystem" - select RT_USING_DFS - select RT_USING_DFS_ROMFS - default n - if BSP_USING_FS - config BSP_USING_SDCARD_FS - bool "Enable SDCARD filesystem" - select BSP_USING_SDIO_ARTPI - select BSP_USING_SDIO1 - select RT_USING_DFS_ELMFAT - default n - config BSP_USING_SPI_FLASH_FS - bool "Enable SPI FLASH filesystem" - select BSP_USING_SPI_FLASH - select RT_USING_MTD_NOR - select PKG_USING_LITTLEFS - default n - endif - - config BSP_USING_WIFI - bool "Enable wifi (AP6212)" - select ART_PI_USING_WIFI_6212_LIB - select BSP_USING_SPI_FLASH - select RT_USING_WIFI - select RT_USING_SAL - default n - -endmenu - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_UART - bool "Enable UART" - default n - select RT_USING_SERIAL - select RT_SERIAL_USING_DMA - if BSP_USING_UART - menuconfig BSP_USING_UART1 - bool "Enable UART1" - default n - if BSP_USING_UART1 - config BSP_UART1_RX_USING_DMA - bool "Enable UART1 RX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + if BSP_USING_UART4 + config BSP_UART4_RX_USING_DMA + bool "Enable UART4 RX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_TX_USING_DMA + bool "Enable UART4 TX DMA" + depends on BSP_USING_UART4 && RT_SERIAL_USING_DMA + default n + + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + config BSP_USING_UART6 + bool "Enable UART6" default n - - config BSP_UART1_TX_USING_DMA - bool "Enable UART1 TX DMA" - depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + endif + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + endif + config BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + depends on BSP_USING_SPI4 + default n + + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + depends on BSP_USING_SPI4 + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + config BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + + menuconfig BSP_USING_I2C + bool "Enable I2C" + default n + select RT_USING_I2C + if BSP_USING_I2C + choice + prompt "Choice I2C mode" + default BSP_SOFTWARE_I2C + config BSP_SOFTWARE_I2C + bool "Enable I2C BUS (software simulation)" + select RT_USING_I2C_BITOPS + select RT_USING_PIN default n - - config BSP_UART1_RX_BUFSIZE - int "Set UART1 RX buffer size" - range 64 65535 - depends on BSP_USING_UART1 - default 256 - - config BSP_UART1_TX_BUFSIZE - int "Set UART1 TX buffer size" - range 0 65535 - depends on BSP_USING_UART1 - default 0 - - endif - - menuconfig BSP_USING_UART3 - bool "Enable UART3" - default n - if BSP_USING_UART3 - config BSP_UART3_RX_BUFSIZE - int "Set UART3 RX buffer size" - range 64 65535 - depends on BSP_USING_UART3 - default 256 - - config BSP_UART3_TX_BUFSIZE - int "Set UART3 TX buffer size" - range 0 65535 - depends on BSP_USING_UART3 - default 0 - endif - - menuconfig BSP_USING_UART4 - bool "Enable UART4" - default n - if BSP_USING_UART4 - config BSP_UART4_RX_BUFSIZE - int "Set UART4 RX buffer size" - range 64 65535 - depends on BSP_USING_UART4 - default 256 - - config BSP_UART4_TX_BUFSIZE - int "Set UART4 TX buffer size" - range 0 65535 - depends on BSP_USING_UART4 - default 0 + config BSP_HARDWARE_I2C + bool "Enable I2C BUS (hardware)" + endchoice + if BSP_SOFTWARE_I2C + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default n + if BSP_USING_I2C1 + comment "Notice: PB6 --> 22; PB7 --> 23" + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 0 175 + default 22 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 0 175 + default 23 + endif + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS (software simulation)" + default n + if BSP_USING_I2C2 + comment "Notice: PH13 --> 125; PH15 --> 127" + config BSP_I2C2_SCL_PIN + int "i2c2 scl pin number" + range 1 176 + default 127 + config BSP_I2C2_SDA_PIN + int "I2C2 sda pin number" + range 0 175 + default 125 + endif + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS (software simulation)" + default n + if BSP_USING_I2C3 + comment "Notice: PH12 --> 124; PH11 --> 123" + config BSP_I2C3_SCL_PIN + int "i2c3 scl pin number" + range 0 175 + default 123 + config BSP_I2C3_SDA_PIN + int "I2C3 sda pin number" + range 0 175 + default 124 + endif endif - menuconfig BSP_USING_UART6 - bool "Enable UART6" - default n - if BSP_USING_UART6 - config BSP_UART6_RX_BUFSIZE - int "Set UART6 RX buffer size" - range 64 65535 - depends on BSP_USING_UART6 - default 256 - - config BSP_UART6_TX_BUFSIZE - int "Set UART6 TX buffer size" - range 0 65535 - depends on BSP_USING_UART6 - default 0 - + if BSP_HARDWARE_I2C + menuconfig BSP_USING_HARD_I2C1 + bool "Enable I2C1 BUS (hardware)" + default n + if BSP_USING_HARD_I2C1 + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + depends on RT_I2C_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + depends on RT_I2C_USING_DMA + endif + menuconfig BSP_USING_HARD_I2C2 + bool "Enable I2C2 BUS (hardware)" + default n + if BSP_USING_HARD_I2C2 + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + depends on RT_I2C_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + depends on RT_I2C_USING_DMA + endif + menuconfig BSP_USING_HARD_I2C3 + bool "Enable I2C3 BUS (hardware)" + default n + if BSP_USING_HARD_I2C3 + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + depends on RT_I2C_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + depends on RT_I2C_USING_DMA + endif + menuconfig BSP_USING_HARD_I2C4 + bool "Enable I2C4 BUS (hardware)" + default n endif - endif - - menuconfig BSP_USING_SPI - bool "Enable SPI" - default n - select RT_USING_SPI - if BSP_USING_SPI - config BSP_USING_SPI1 - bool "Enable SPI1" - default n - config BSP_USING_SPI2 - bool "Enable SPI2" - default n - config BSP_USING_SPI3 - bool "Enable SPI3" - default n - config BSP_USING_SPI4 - bool "Enable SPI4" - default n - endif - - config BSP_USING_QSPI - bool "Enable QSPI BUS" - select RT_USING_QSPI - select RT_USING_SPI - default n - - config BSP_USING_ONCHIP_RTC - bool "Enable Onchip RTC" - select RT_USING_RTC - default n + endif - menuconfig BSP_USING_I2C - bool "Enable I2C BUS (software simulation)" - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - default n - if BSP_USING_I2C - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - comment "Notice: PB6 --> 22; PB7 --> 23" - config BSP_I2C1_SCL_PIN - int "I2C1 scl pin number" - range 0 175 - default 22 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 0 175 - default 23 - endif - menuconfig BSP_USING_I2C2 - bool "Enable I2C2 BUS (software simulation)" - default n - if BSP_USING_I2C2 - comment "Notice: PH13 --> 125; PH15 --> 127" - config BSP_I2C2_SCL_PIN - int "i2c2 scl pin number" - range 1 176 - default 127 - config BSP_I2C2_SDA_PIN - int "I2C2 sda pin number" - range 0 175 - default 125 - endif - menuconfig BSP_USING_I2C3 - bool "Enable I2C3 BUS (software simulation)" + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + config BSP_USING_SDRAM + bool "Enable SDRAM" + default n + + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + if BSP_USING_ETH + config ETH_RESET_PIN + string "ETH RESET PIN" + default "PA.3" + endif + if BSP_USING_ETH + choice + prompt "Choose ETH PHY" + default PHY_USING_LAN8720A + config PHY_USING_LAN8720A + bool "USING LAN8720A" + default n + endchoice + endif + + config BSP_USING_LCD + bool "Enable LCD" + select BSP_USING_GPIO + select BSP_USING_SDRAM + select RT_USING_MEMHEAP + default n + + config BSP_USING_DCMI + bool "Enable DCMI" + default n + + menuconfig BSP_USING_FDCAN + bool "Enable FDCAN" + default n + select RT_USING_CAN + if BSP_USING_FDCAN + config BSP_USING_FDCAN1 + bool "USING FDCAN1" + default n + endif + + config BSP_USING_USBD + bool "Enable USB Device" + select RT_USING_USB_DEVICE + default n + + menuconfig BSP_USING_USBH + bool "Enable USB Host" + select RT_USING_USB_HOST + default n + if BSP_USING_USBH + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + + menuconfig BSP_USING_TIM + bool "Enable timer" + default n + select RT_USING_HWTIMER + if BSP_USING_TIM + config BSP_USING_TIM13 + bool "Enable TIM13" + default n + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM5 + bool "Enable Timer5 output pwm" default n - if BSP_USING_I2C3 - comment "Notice: PH12 --> 124; PH11 --> 123" - config BSP_I2C3_SCL_PIN - int "i2c3 scl pin number" - range 0 175 - default 123 - config BSP_I2C3_SDA_PIN - int "I2C3 sda pin number" - range 0 175 - default 124 + if BSP_USING_PWM5 + config BSP_USING_PWM5_CH1 + bool "Enable PWM5 channel1" + default n endif - endif - - config BSP_USING_SDRAM - bool "Enable SDRAM" - default n - - config BSP_USING_WDT - bool "Enable Watchdog Timer" - select RT_USING_WDT - default n - - config BSP_USING_LCD - bool "Enable LCD" - select BSP_USING_LTDC - select BSP_USING_GPIO - select BSP_USING_SDRAM - select RT_USING_MEMHEAP - default n - - menuconfig BSP_USING_SDIO_ARTPI - bool "Enable SDIO" - default n - select RT_USING_SDIO - if BSP_USING_SDIO_ARTPI - config BSP_USING_SDIO1 - bool "Enable SDIO1" + config SAMPLES_USING_PWM + bool "SAMPLE PWM5 channel1" default n - config BSP_USING_SDIO2 - bool "Enable SDIO2" - default n - endif - - config BSP_USING_USBD - bool "Enable USB Device" - select RT_USING_USB_DEVICE - default n - - menuconfig BSP_USING_USBH - bool "Enable USB Host" - select RT_USING_USB_HOST - default n - if BSP_USING_USBH - menuconfig RT_USBH_MSTORAGE - bool "Enable Udisk Drivers" - select RT_USING_DFS - select RT_USING_DFS_ELMFAT - default n - if RT_USBH_MSTORAGE - config UDISK_MOUNTPOINT - string "Udisk mount dir" - default "/" - endif - endif - - menuconfig BSP_USING_ETH_H750 - bool "Enable Ethernet" - default n - select RT_USING_LWIP - if BSP_USING_ETH_H750 - config ETH_RESET_PIN - string "ETH RESET PIN" - default "PA.3" - endif - if BSP_USING_ETH_H750 - choice - prompt "Choose ETH PHY" - default PHY_USING_LAN8720A - config PHY_USING_LAN8720A - bool "USING LAN8720A" + endif + + config BSP_USING_ONCHIP_RTC + bool "Enable Onchip RTC" + select RT_USING_RTC + default n + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + config BSP_USING_ADC1 + bool "Enable ADC1" + default n + endif + if BSP_USING_ADC + config BSP_USING_ADC2 + bool "Enable ADC2" + default n + endif + if BSP_USING_ADC + config BSP_USING_ADC3 + bool "Enable ADC3" default n endchoice endif