diff --git a/bsp/nxp/S32K3/README.md b/bsp/nxp/S32K3/README.md new file mode 100644 index 000000000000..bc7d625cc530 --- /dev/null +++ b/bsp/nxp/S32K3/README.md @@ -0,0 +1,52 @@ +# S32K3 BSP 说明 + +## S32K344 + +### 1. 介绍： + +基础工程： + +- LPUART3(PD3-Rx, PD2-Tx) : + - 每2s打印hello + - finsh + +使用软件包：SW32K3_S32M27x_RTD_R21-11_5.0.0 + +生成工具：S32 Design Studio for S32 Platform 3.5 + + +使用样板： + +![](./img/使用样板.png) + +### 2. 例程使用准备： + +- 目前仅使用gcc编译，为了增加同通用性，例程尽量使用了寄存器操作。在编译前请将`bsp\nxp\S32K3\S32K344-core\libraries\s32k344_SDK`和`board`中的文件补充完整： + + | 目录名 | 对应nxp目录 | 备注 | + | -------------------- | ------------------------------------------ | --------------------------------------- | + | header | BaseNXP_TS_T40D34M50I0R0\header | 寄存器定义（在nxp软件包目录下查找） | + | include | | 在下一步中补充 | + | Startup_Code\inc | Platform_TS_T40D34M50I0R0\startup\include | 芯片启动头文件（在nxp软件包目录下查找） | + | Startup_Code\src | 生成模板工程\Project_Settings\Startup_Code | 芯片启动源文件 | + | linker_scripts | 生成模板工程\Project_Settings\Linker_Files | 芯片链接脚本（在board中） | + +- 在补充完成后： + + 1. 编译，寻找缺失头文件，在`BaseNXP_TS_T40D34M50I0R0\include`目录下查找并放入目录`include` + + 2. 重复步骤 1 直到缺失的头文件无法在`BaseNXP_TS_T40D34M50I0R0\include`目录下找到，或者不在是头文件缺失错误 + + 3. 删除`include` 目录下的`Mcal.h`，将工程中所有的 `#include "Mcal.h"`替换为`#include "S32K344.h"` + + 4. 在`ststem.h`头部添加： + + ```c + #define OsIf_GetCoreID() Sys_GetCoreID() + #define MCAL_DATA_SYNC_BARRIER() __asm__(" DSB") + #define MCAL_INSTRUCTION_SYNC_BARRIER() __asm__(" ISB") + ``` + + 5. 删除`exceptions.c`中的`PendSV_Handler`和`SysTick_Handler`实现。 + + 6. 修改`startup_cm7.s`：`main`改为 RTT 入口`entry`，删除 `_start:` diff --git a/bsp/nxp/S32K3/S32K344-core/.config b/bsp/nxp/S32K3/S32K344-core/.config new file mode 100644 index 000000000000..c3c0c01c644d --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/.config @@ -0,0 +1,288 @@ + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=1024 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=1024 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice optimization +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +CONFIG_RT_USING_OVERFLOW_CHECK=y + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +# CONFIG_RT_USING_SCHED_THREAD_CTX is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart3" +CONFIG_RT_VER_NUM=0x50200 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_KTIME is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# CONFIG_RT_USING_VBUS is not set + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# Hardware Drivers Config +# +CONFIG_CPU_S32K344=y +CONFIG_BSP_USING_SHELL_TO_USART=y + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART3=y +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/nxp/S32K3/S32K344-core/.gitignore b/bsp/nxp/S32K3/S32K344-core/.gitignore new file mode 100644 index 000000000000..2a7ed905837e --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/.gitignore @@ -0,0 +1,5 @@ +board/linker_scripts/*.ld +libraries/s32k344_SDK/**/*.c +libraries/s32k344_SDK/**/*.s +libraries/s32k344_SDK/**/*.h +libraries/s32k344_SDK/**/*.svd \ No newline at end of file diff --git a/bsp/nxp/S32K3/S32K344-core/Kconfig b/bsp/nxp/S32K3/S32K344-core/Kconfig new file mode 100644 index 000000000000..64355c48b86b --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/Kconfig @@ -0,0 +1,13 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "libraries/Kconfig" +rsource "board/Kconfig" + diff --git a/bsp/nxp/S32K3/S32K344-core/SConscript b/bsp/nxp/S32K3/S32K344-core/SConscript new file mode 100644 index 000000000000..20f7689c53ca --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/nxp/S32K3/S32K344-core/SConstruct b/bsp/nxp/S32K3/S32K344-core/SConstruct new file mode 100644 index 000000000000..4dc1058c2d11 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/SConstruct @@ -0,0 +1,60 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +S32K3_library = 's32k344_SDK/header' +rtconfig.BSP_LIBRARY_TYPE = S32K3_library + +# include libraries +objs.extend(SConscript(os.path.join(libraries_path_prefix, S32K3_library, 'SConscript'))) + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'Drivers', 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/nxp/S32K3/S32K344-core/applications/SConscript b/bsp/nxp/S32K3/S32K344-core/applications/SConscript new file mode 100644 index 000000000000..ca2395451a1c --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/applications/SConscript @@ -0,0 +1,11 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/nxp/S32K3/S32K344-core/applications/main.c b/bsp/nxp/S32K3/S32K344-core/applications/main.c new file mode 100644 index 000000000000..1e0d02456157 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/applications/main.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-16 Pillar first version + */ + +#include +#include + +void print_thread(void *parameter) +{ + while (1) + { + rt_kprintf("hello\n"); + rt_thread_mdelay(2000); + } +} + +int main(void) +{ + rt_thread_t tid; + tid = rt_thread_create("print", print_thread, RT_NULL, 512, 16, 10); + if (tid != RT_NULL) + rt_thread_startup(tid); +} diff --git a/bsp/nxp/S32K3/S32K344-core/board/Kconfig b/bsp/nxp/S32K3/S32K344-core/board/Kconfig new file mode 100644 index 000000000000..73286bbb42a7 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/board/Kconfig @@ -0,0 +1,28 @@ +menu "Hardware Drivers Config" + +config CPU_S32K344 + bool + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + select BSP_USING_SHELL_TO_USART + default y + +config BSP_USING_SHELL_TO_USART + bool "Enable SHELL TO USART (uart3)" + select BSP_USING_UART + select BSP_USING_UART3 + default y + +menu "On-chip Peripheral Drivers" + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART3 + bool "Enable UART3(PD2,PD3)" + default y + endif +endmenu + +endmenu \ No newline at end of file diff --git a/bsp/nxp/S32K3/S32K344-core/board/SConscript b/bsp/nxp/S32K3/S32K344-core/board/SConscript new file mode 100644 index 000000000000..84141a6f6435 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/board/SConscript @@ -0,0 +1,25 @@ +import os +import rtconfig +from building import * + +Import('SDK_LIB') + +cwd = GetCurrentDir() +chip_lib_path = SDK_LIB + '/s32k344_SDK' + +# add general drivers +src = Split(''' +board.c +''') + +path = [cwd] +path += [chip_lib_path + '/Startup_Code/inc'] + +startup_path_prefix = chip_lib_path + '/Startup_Code/src' +if rtconfig.PLATFORM in ['gcc']: + src += Glob(startup_path_prefix + '/*.c') + src += Glob(startup_path_prefix + '/*.s') + +CPPDEFINES = ['I_CACHE_ENABLE', 'D_CACHE_ENABLE', 'ENABLE_FPU', 'MPU_ENABLE', 'S32K344'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) +Return('group') diff --git a/bsp/nxp/S32K3/S32K344-core/board/board.c b/bsp/nxp/S32K3/S32K344-core/board/board.c new file mode 100644 index 000000000000..b5c5f04dc016 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/board/board.c @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-16 Pillar first version + */ + +#include "board.h" +#include "drv_uart.h" + +static inline uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > S32_SysTick_RVR_RELOAD_MASK) + { + return 1; + } + + S32_SysTick->RVR = (uint32_t)(ticks - 1UL); + S32_SysTick->CVR = 0UL; + S32_SysTick->CSRr = S32_SysTick_CSR_ENABLE(1) | + S32_SysTick_CSR_TICKINT(1) | + S32_SysTick_CSR_CLKSOURCE(1); + return 0; +} + +#define SYSCLK 48000000 + +void rt_hw_board_init(void) +{ + SysTick_Config(SYSCLK / RT_TICK_PER_SECOND); + +#if defined(RT_USING_HEAP) + /* Heap initialization */ + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_SERIAL + rt_hw_usart_init(); +#endif + +#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif +} + +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} \ No newline at end of file diff --git a/bsp/nxp/S32K3/S32K344-core/board/board.h b/bsp/nxp/S32K3/S32K344-core/board/board.h new file mode 100644 index 000000000000..154fe40be437 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/board/board.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-16 Pillar first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include + +#include "S32K344.h" +#include + +#define SRAM_SIZE (184) +#define SRAM_END (0x20400000 + SRAM_SIZE * 1024) + +extern int __sram_data_end__; +#define HEAP_BEGIN ((void *)&__sram_data_end__) +#define HEAP_END SRAM_END + +#ifdef __cplusplus +extern "C" { +#endif + +void rt_hw_board_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __BOARD_H__ */ diff --git a/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/SConscript b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/SConscript new file mode 100644 index 000000000000..35fe1a09ce16 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/SConscript @@ -0,0 +1,14 @@ +Import('RTT_ROOT') +Import('rtconfig') +from building import * +import os +cwd = GetCurrentDir() +group = [] +src = [] +path = [cwd] + +src += ['drv_uart.c'] + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path) + +Return('group') \ No newline at end of file diff --git a/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.c b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.c new file mode 100644 index 000000000000..04e19e24a5f7 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.c @@ -0,0 +1,257 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-19 Pillar first version + */ + +#include "drv_uart.h" +#include "board.h" + +typedef void (*Uart_Irq_Handler_t)(void); + +struct s32k3_uart_config +{ + const char *name; + LPUART_Type *Instance; + IRQn_Type irq_type; + rt_uint8_t priority; +}; + +struct s32k3_uart_pin +{ + SIUL2_Type *base; + rt_uint32_t tx_pinIdx; + rt_uint32_t tx_mux; + rt_uint32_t rx_pinIdx; + rt_uint32_t rx_mux; + rt_uint32_t rx_input_mux_reg; + rt_uint32_t rx_input_mux; +}; + +struct s32k3_uart +{ + struct s32k3_uart_config *config; + struct s32k3_uart_pin *pin_config; + struct rt_serial_device serial; +}; + +#ifndef BSP_USING_UART3 +#error "Please define BSP_USING_UART3" +#endif + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = IP_LPUART_3, \ + .irq_type = LPUART3_IRQn, \ + .priority = 0 \ + } +#endif /* UART3_CONFIG */ +#endif /* BSP_USING_UART3 */ + +enum +{ +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +}; + +static struct s32k3_uart_config uart_config[] = +{ +#ifdef BSP_USING_UART3 + UART3_CONFIG, +#endif +}; + +static struct s32k3_uart_pin uart_pin[] = +{ +#ifdef BSP_USING_UART3 + { + .base = IP_SIUL2, + .tx_pinIdx = 98, + .tx_mux = 6, + .rx_pinIdx = 99, + .rx_mux = 0, + .rx_input_mux_reg = 190, + .rx_input_mux = 3, + }, +#endif +}; + +static struct s32k3_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; + +static inline void _lpuart3_clock_init() +{ + /* just for LPUART3 */ + IP_MC_ME->PRTN1_COFB2_CLKEN |= MC_ME_PRTN1_COFB2_CLKEN_REQ77_MASK; + IP_MC_ME->PRTN1_COFB0_CLKEN &= (~MC_ME_PRTN1_COFB0_CLKEN_REQ24_MASK); + IP_MC_ME->PRTN1_PCONF |= MC_ME_PRTN1_PCONF_PCE_MASK; + IP_MC_ME->PRTN1_PUPD |= MC_ME_PRTN1_PUPD_PCUD_MASK; + + IP_MC_ME->CTL_KEY = 0x5AF0U; /* Enter key */ + IP_MC_ME->CTL_KEY = 0xA50FU; +} + +static inline void _lpuart_set_int(LPUART_Type * Base, rt_uint32_t mask, rt_bool_t Enable) +{ + if (Enable) + Base->CTRL |= mask; + else + Base->CTRL &= ~mask; +} + +#if defined(BSP_USING_UART3) +void uart3_isr() +{ + rt_interrupt_enter(); + rt_hw_serial_isr(&uart_obj[UART3_INDEX].serial, RT_SERIAL_EVENT_RX_IND); + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#ifndef INT_CTRL_IP_NVIC_PRIO_BITS +#define INT_CTRL_IP_NVIC_PRIO_BITS (4U) +#endif + +#define SIUL2_MSCR_SSS_ALL_MASK (0x0F) +#define SIUL2_MSCR_SSS_ALL_SHIFT (0) +#define SIUL2_MSCR_SSS_ALL(x) (((rt_uint32_t)(((rt_uint32_t)(x)) << SIUL2_MSCR_SSS_ALL_SHIFT)) & SIUL2_MSCR_SSS_ALL_MASK) +#define SIUL2_MAX_NUM_OF_IMCR_REG (512u) + +static rt_err_t uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) +{ + struct s32k3_uart *uart = rt_container_of(serial, struct s32k3_uart, serial); + LPUART_Type *Instance = uart->config->Instance; + SIUL2_Type *base = uart->pin_config->base; + rt_uint32_t irqn = (rt_uint32_t)uart->config->irq_type; + rt_uint8_t shift = (rt_uint8_t) (8U - INT_CTRL_IP_NVIC_PRIO_BITS); + Uart_Irq_Handler_t *vector = (Uart_Irq_Handler_t *)S32_SCB->VTOR; + + _lpuart3_clock_init(); + + /* tx Pin set */ + rt_uint32_t pin_val = 0; + pin_val |= SIUL2_MSCR_OBE_MASK; + pin_val |= SIUL2_MSCR_SSS_ALL(uart->pin_config->tx_mux); + base->MSCR[uart->pin_config->tx_pinIdx] = pin_val; + /* rx Pin set */ + pin_val = 0; + pin_val |= SIUL2_MSCR_IBE_MASK; + pin_val |= SIUL2_MSCR_SSS_ALL(uart->pin_config->rx_mux); + base->IMCR[uart->pin_config->rx_input_mux_reg] = SIUL2_IMCR_SSS(uart->pin_config->rx_input_mux); + base->MSCR[uart->pin_config->rx_pinIdx] = pin_val; + + /* set IRQ */ + /* clear pending flag */ + S32_NVIC->ICPR[irqn >> 5U] = (rt_uint32_t)(1UL << (irqn & (rt_uint32_t)0x1FU)); + /* set Priority */ + S32_NVIC->IP[irqn] = (rt_uint8_t)((((rt_uint32_t)uart->config->priority) << shift) & 0xFFUL); + /* Install the configured handler */ + vector[irqn + 16] = uart3_isr; + /* eable irq */ + S32_NVIC->ISER[irqn >> 5U] = (rt_uint32_t)(1UL << (irqn & (rt_uint32_t)0x1FU)); + + /* disable TE and RE */ + Instance->CTRL &= ~LPUART_CTRL_TE_MASK; + Instance->CTRL &= ~LPUART_CTRL_RE_MASK; + + /* set baud rate */ + Instance->BAUD &= ~LPUART_BAUD_SBR_MASK; + Instance->BAUD |= LPUART_BAUD_SBR((24000000)/(uart->serial.config.baud_rate*16)); + + /* enable TE and RE */ + Instance->CTRL |= LPUART_CTRL_TE_MASK; + Instance->CTRL |= LPUART_CTRL_RE_MASK; + return RT_EOK; +} + +static rt_err_t uart_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct s32k3_uart *uart = rt_container_of(serial, struct s32k3_uart, serial); + switch (cmd) + { + /* disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + { + rt_uint32_t direction = (rt_uint32_t)arg; + if(direction == RT_DEVICE_FLAG_INT_RX) + _lpuart_set_int(uart->config->Instance, LPUART_CTRL_RIE_MASK, RT_FALSE); + + break; + } + + /* enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + { + // HAL_NVIC_SetPriority(uart->config->irq_type, 1, 0); + rt_uint32_t direction = (rt_uint32_t)arg; + if(direction == RT_DEVICE_FLAG_INT_RX) + _lpuart_set_int(uart->config->Instance, LPUART_CTRL_RIE_MASK, RT_TRUE); + + break; + } + + default: + break; + } + return RT_EOK; +} + +static int uart_putchar(struct rt_serial_device *serial, char ch) +{ + struct s32k3_uart *uart = rt_container_of(serial, struct s32k3_uart, serial); + LPUART_Type *base = uart->config->Instance; + + while((base->STAT &LPUART_STAT_TDRE_MASK) != LPUART_STAT_TDRE_MASK); + + base->DATA = ch; + return 1; +} + +static int uart_getchar(struct rt_serial_device *serial) +{ + struct s32k3_uart *uart = rt_container_of(serial, struct s32k3_uart, serial); + LPUART_Type *base = uart->config->Instance; + + if ((base->STAT & LPUART_STAT_RDRF_MASK) != LPUART_STAT_RDRF_MASK) + return -1; + else + return base->DATA; +} + +static const struct rt_uart_ops uart_ops = +{ + .configure = uart_configure, + .control = uart_control, + .putc = uart_putchar, + .getc = uart_getchar, +}; + +int rt_hw_usart_init(void) +{ + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + rt_err_t result = 0; + + for (rt_size_t i = 0; i < sizeof(uart_obj) / sizeof(uart_obj[0]); i++) + { + /* init UART object */ + uart_obj[i].config = &uart_config[i]; + uart_obj[i].pin_config = &uart_pin[i]; + uart_obj[i].serial.ops = &uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, + RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, + RT_NULL); + RT_ASSERT(result == RT_EOK); + } + + return result; +} diff --git a/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.h b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.h new file mode 100644 index 000000000000..233c1054f247 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/libraries/Drivers/drv_uart.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024-10-19 Pillar first version + */ + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef RT_USING_SERIAL +#include "rtdevice.h" +#include + +int rt_hw_usart_init(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ diff --git a/bsp/nxp/S32K3/S32K344-core/libraries/Kconfig b/bsp/nxp/S32K3/S32K344-core/libraries/Kconfig new file mode 100644 index 000000000000..2885ba9d8071 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/libraries/Kconfig @@ -0,0 +1,7 @@ +config SOC_FAMILY_S32K3 + bool + +config SOC_SERIES_S32K344 + bool + select ARCH_ARM_CORTEX_M7 + select SOC_FAMILY_S32K3 \ No newline at end of file diff --git a/bsp/nxp/S32K3/S32K344-core/libraries/s32k344_SDK/header/SConscript b/bsp/nxp/S32K3/S32K344-core/libraries/s32k344_SDK/header/SConscript new file mode 100644 index 000000000000..7dda4c0e2a89 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/libraries/s32k344_SDK/header/SConscript @@ -0,0 +1,16 @@ +import rtconfig +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. + +src = [] +path = [cwd , + cwd + '/../include'] + +CPPDEFINES = [] +group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/nxp/S32K3/S32K344-core/rtconfig.h b/bsp/nxp/S32K3/S32K344-core/rtconfig.h new file mode 100644 index 000000000000..5ce3c80db074 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/rtconfig.h @@ -0,0 +1,160 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 1024 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 1024 + +/* kservice optimization */ + +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_USING_OVERFLOW_CHECK + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart3" +#define RT_VER_NUM 0x50200 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* Hardware Drivers Config */ + +#define CPU_S32K344 +#define BSP_USING_SHELL_TO_USART + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define BSP_USING_UART3 +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/nxp/S32K3/S32K344-core/rtconfig.py b/bsp/nxp/S32K3/S32K344-core/rtconfig.py new file mode 100644 index 000000000000..4db12cb207c1 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/rtconfig.py @@ -0,0 +1,188 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m7' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'C:\Users\XXYYZZ' +elif CROSS_TOOL == 'keil': + print('================ERROR============================') + print('Not support keil yet!') + print('=================================================') + exit(0) +elif CROSS_TOOL == 'iar': + print('================ERROR============================') + print('Not support iar yet!') + print('=================================================') + exit(0) + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m7 -mthumb -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rt-thread.map,-cref,-u,Reset_Handler -T board/linker_scripts/linker_flash_s32k344.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7 ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rt-thread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'armclang': + # toolchains + CC = 'armclang' + CXX = 'armclang' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M7.fp ' + CFLAGS = ' --target=arm-arm-none-eabi -mcpu=cortex-m7 ' + CFLAGS += ' -mcpu=cortex-m7 ' + CFLAGS += ' -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar ' + CFLAGS += ' -gdwarf-3 -ffunction-sections ' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers ' + LFLAGS += ' --list rt-thread.map ' + LFLAGS += r' --strict --scatter "board\linker_scripts\link.sct" ' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCLANG/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCLANG/lib' + + EXEC_PATH += '/ARM/ARMCLANG/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O1' # armclang recommend + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M7' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M7' + AFLAGS += ' --fpu None' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/nxp/S32K3/S32K344-core/template.ewp b/bsp/nxp/S32K3/S32K344-core/template.ewp new file mode 100644 index 000000000000..d63b5fe881f5 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/template.ewp @@ -0,0 +1,2114 @@ + + + 3 + + rt-thread + + ARM + + 1 + + General + 3 + + 31 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 1 + + + + + + + + + CUSTOM + 3 + + + + 1 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 1 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 36 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 10 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 23 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + diff --git a/bsp/nxp/S32K3/S32K344-core/template.eww b/bsp/nxp/S32K3/S32K344-core/template.eww new file mode 100644 index 000000000000..bd036bb4c98c --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/nxp/S32K3/S32K344-core/template.uvoptx b/bsp/nxp/S32K3/S32K344-core/template.uvoptx new file mode 100644 index 000000000000..2b7d33fccd04 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/template.uvoptx @@ -0,0 +1,185 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 0 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + JL2CM3 + -U59701291 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(4) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512.FLM -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 0 + 0 + 0 + 0 + + + diff --git a/bsp/nxp/S32K3/S32K344-core/template.uvprojx b/bsp/nxp/S32K3/S32K344-core/template.uvprojx new file mode 100644 index 000000000000..03ea186a2bc5 --- /dev/null +++ b/bsp/nxp/S32K3/S32K344-core/template.uvprojx @@ -0,0 +1,395 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + APM32F103ZE + Geehy + Geehy.APM32F1xx_DFP.1.0.8 + https://www.geehy.com/uploads/tool/ + IRAM(0x20000000,0x00020000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0APM32F10x_512 -FS08000000 -FL080000 -FP0($$Device:APM32F103ZE$Flash\APM32F10x_512.FLM)) + 0 + $$Device:APM32F103ZE$Device\Include\apm32f10x.h + + + + + + + + + + $$Device:APM32F103ZE$SVD\APM32F103xx.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DCM.DLL + -pCM3 + SARMCM3.DLL + + TCM.DLL + -pCM3 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M3" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x20000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Source Group 1 + + + + + + + + + + + + diff --git "a/bsp/nxp/S32K3/img/\344\275\277\347\224\250\346\240\267\346\235\277.png" "b/bsp/nxp/S32K3/img/\344\275\277\347\224\250\346\240\267\346\235\277.png" new file mode 100644 index 000000000000..971b521d30b4 Binary files /dev/null and "b/bsp/nxp/S32K3/img/\344\275\277\347\224\250\346\240\267\346\235\277.png" differ