HDL_bit_wave.vcd

$date
	Wed Jul 24 11:07:17 2024
$end
$version
	Icarus Verilog
$end
$timescale
	1ps
$end
$scope module pul_sync_wrapper_tb $end
$var wire 1 ! d_sync_pos $end
$var wire 1 " d_sync_neg $end
$var parameter 32 # CLKa_FREQ $end
$var parameter 32 $ CLKb_FREQ $end
$var reg 1 % clk_des $end
$var reg 1 & clk_src $end
$var reg 1 ' d_in $end
$var reg 1 ( rst_b $end
$scope module u_pul_sync_wrapper $end
$var wire 1 % clk_des $end
$var wire 1 & clk_src $end
$var wire 1 ' d_in $end
$var wire 1 " d_sync_neg $end
$var wire 1 ! d_sync_pos $end
$var wire 1 ( rst_b $end
$var wire 1 ) d_src_sync $end
$var wire 1 * d_des_sync $end
$var reg 1 + d_des_sync_dly $end
$var reg 2 , d_in_clk_cross_des [1:0] $end
$var reg 2 - d_in_clk_cross_src [1:0] $end
$var reg 1 . d_in_lev $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
b10100 $
b1100100 #
$end
#0
$dumpvars
x.
bx -
bx ,
x+
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x)
x(
0'
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x%
x"
x!
$end
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