diff --git a/Makefile b/Makefile index 671b0214..c89507db 100644 --- a/Makefile +++ b/Makefile @@ -120,7 +120,7 @@ $(TOPDIR)/toolchain/$(GCC_SOURCE): gcc-unpacked: $(TOPDIR)/toolchain/$(GCC_SOURCE) $(Q) if [ ! -d $(TOOLCHAINPATH) ]; then \ - tar xjf $(TOPDIR)/toolchain/$(GCC_SOURCE) -C $(TOPDIR)/toolchain ; \ + tar xvf $(TOPDIR)/toolchain/$(GCC_SOURCE) -C $(TOPDIR)/toolchain ; \ fi toolchain: check_context Make.defs .config $(TOPDIR)/toolchain/$(GCC_SOURCE) gcc-unpacked diff --git a/README.md b/README.md index bd3ee4fd..d1f703d9 100644 --- a/README.md +++ b/README.md @@ -34,19 +34,22 @@ the beginnings of corresponding files; also, all licenses are listed in --- ## 3. Platforms supported -| **NuMaker-PFM-M2351** | **M2351-Badge** | **V2M-MPS2-Qemu** | **How to add a platform** | +| **NuMaker-PFM-M2351** | **M2351-Badge** | **V2M-MPS2-Qemu** | **RISCV SparkFun RedBoard** | |-----------------------|---------------------------|-------------|-----------| -|[![](docs/images/platforms/numaker_pfm_m2351/numaker_pfm_m2351.png)](docs/numaker_pfm_m2351.md)|[![](docs/images/platforms/m2351_badge/m2351_badge.png)](docs/m2351_badge.md) |[![V2M-MPS2-Qemu](docs/images/platforms/v2m-mps2/v2m-mps2.png)](docs/v2m-mps2-qemu.md)|[![](docs/images/platforms/add_new_board.jpg)](docs/port-new-platform.md)| +|[![](docs/images/platforms/numaker_pfm_m2351/numaker_pfm_m2351.png)](docs/numaker_pfm_m2351.md)|[![](docs/images/platforms/m2351_badge/m2351_badge.png)](docs/m2351_badge.md) |[![V2M-MPS2-Qemu](docs/images/platforms/v2m-mps2/v2m-mps2.png)](docs/v2m-mps2-qemu.md)|[![](docs/images/platforms/sparkfun_redboard/sparkfun_redboard.png)](docs/sparkfun_redboard.md)| +| **How to add a platform** |||| +|[![](docs/images/platforms/add_new_board.jpg)](docs/port-new-platform.md)|||| Several platforms are supported. In order to manage slight differences between platforms, a `PLATFORM` flag has been introduced. -| Platform | Composite PLATFORM flag | Maintained | -|-----------------------|------------------------------------|------------| -| [NuMaker-PFM-M2351] |`PLATFORM=numaker_pfm_m2351` | v0.4 | -| [M2351-Badge] |`PLATFORM=m2351_badge` | v0.4 | -| [V2M-MPS2-Qemu] |`PLATFORM=mps2_an505_qemu` | v0.4 | +| Platform | Composite PLATFORM flag | Maintained | +|---------------------------|------------------------------------|------------| +| [NuMaker-PFM-M2351] |`PLATFORM=numaker_pfm_m2351` | v0.4 | +| [M2351-Badge] |`PLATFORM=m2351_badge` | v0.4 | +| [V2M-MPS2-Qemu] |`PLATFORM=mps2_an505_qemu` | v0.4 | +| [SparkFun RED-V RedBoard] |`PLATFORM=sparkfun_redboard` | v0.5 | For information on adding a new platform see the [how to add a platform]. @@ -98,3 +101,4 @@ you can find here](.github/CONTRIBUTING.md). [NuMaker-PFM-M2351]: http://www.nuvoton.com.cn/hq/products/iot-solution/iot-platform/numaker-maker-platform/numaker-pfm-m2351?__locale=en [M2351-Badge]: docs/schemes/m2351_badge [V2M-MPS2-Qemu]: https://developer.arm.com/documentation/100964/1114/Microcontroller-Prototyping-System-2?lang=en +[SparkFun RED-V RedBoard]: https://www.sparkfun.com/products/15594 diff --git a/arch/Kconfig b/arch/Kconfig index 79a3a628..13d31004 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -17,12 +17,18 @@ config ARCH_CORTEX_M33 ---help--- The ARM architecture +config ARCH_RISCV_32 + bool "riscv32" + ---help--- + The ARM architecture + endchoice config ARCH string default "cortex-m23" if ARCH_CORTEX_M23 default "cortex-m33" if ARCH_CORTEX_M33 + default "riscv32" if ARCH_RISCV_32 if ARCH_CORTEX_M23 source arch/cortex-m23/Kconfig @@ -32,6 +38,10 @@ if ARCH_CORTEX_M33 source arch/cortex-m33/Kconfig endif +if ARCH_RISCV_32 +source arch/riscv32/Kconfig +endif + comment "Toolchain Configuration Options" choice prompt "Toolchain Selection" @@ -53,6 +63,12 @@ config GCC_VERSION_8_2018Q4 # depends on ARCH_FAMILY_MPS2 # bool "GCC compiler Version: 8 2019 q3" +config GCC_VERSION_10_2_0_2020_12 + bool "GCC compiler Version: SiFive GCC-Metal 10.2.0-2020.12.8" + +config GCC_VERSION_T_HEAD_10_2_0 + bool "GCC compiler Version: T-Head GCC 10.2.0" + endchoice config GCC_VERSION @@ -61,6 +77,7 @@ config GCC_VERSION default arm-none-eabi-6-2017-q2-update-linux if GCC_VERSION_6_1_2017Q2 default arm-none-eabi-8-2018-q4-major-linux if GCC_VERSION_8_2018Q4 # default gcc-arm-none-eabi-8-2019-q3-update-linux if GCC_VERSION_8_2019Q3 + default riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14 if GCC_VERSION_10_2_0_2020_12 config GCC_SITE string @@ -70,6 +87,8 @@ config GCC_SITE # default "https://developer.arm.com/-/media/Files/downloads/gnu-rm/8-2019q3" if GCC_VERSION_8_2019Q3 # default "https://developer.arm.com/-/media/Files/downloads/gnu-rm/8-2019q3/RC1.1" if GCC_VERSION_8_2019Q3 # https://developer.arm.com/-/media/Files/downloads/gnu-rm/8-2019q3/RC1.1/gcc-arm-none-eabi-8-2019-q3-update-linux.tar.bz2?revision=c34d758a-be0c-476e-a2de-af8c6e16a8a2?product=GNU%20Arm%20Embedded%20Toolchain%20Downloads,64-bit,,Linux,8-2019-q3-update + default "https://static.dev.sifive.com/dev-tools/freedom-tools/v2020.12" if GCC_VERSION_10_2_0_2020_12 + default "https://github.com/bouffalolab/toolchain_gcc_t-head_linux" if GCC_VERSION_T_HEAD_10_2_0 config GCC_FOLDER string @@ -77,4 +96,5 @@ config GCC_FOLDER default "gcc-arm-none-eabi-6-2017-q2-update" if GCC_VERSION_6_1_2017Q2 default "gcc-arm-none-eabi-8-2018-q4-major" if GCC_VERSION_8_2018Q4 # default "gcc-arm-none-eabi-8-2019-q3-update" if GCC_VERSION_8_2019Q3 - + default "riscv64-unknown-elf-toolchain-10.2.0-2020.12.8-x86_64-linux-ubuntu14" if GCC_VERSION_10_2_0_2020_12 + default "toolchain_gcc_t-head_linux-master" if GCC_VERSION_T_HEAD_10_2_0 diff --git a/arch/cortex-m23/m2351/src/m2351_badge/nonsecure/Makefile b/arch/cortex-m23/m2351/src/m2351_badge/nonsecure/Makefile index 68dc07fa..b1f44d08 100644 --- a/arch/cortex-m23/m2351/src/m2351_badge/nonsecure/Makefile +++ b/arch/cortex-m23/m2351/src/m2351_badge/nonsecure/Makefile @@ -77,7 +77,7 @@ $(COBJS_NS): $(OBJDIR)/%$(OBJEXT): %.c $(Q) $(CC) -c $(CFLAGS) $< -o $@ mtower_ns$(EXEEXT): $(OBJS_NS) - $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" libFreeRTOS_ns.a + $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" FREE_RTOS_ARCH=ARM_V8M libFreeRTOS_ns.a $(Q) $(MAKE) -C ../../StdDriver/src/ TOPDIR="$(TOPDIR)" libm2351_StdDriver_ns.a @echo "LD: mTower_ns$(EXEEXT)" $(Q) $(CC) $(CFLAGS) -Wl,--section-start=.text=$(CONFIG_START_ADDRESS_BL33) -Tnonsecure.ld $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf diff --git a/arch/cortex-m23/m2351/src/numaker_pfm_m2351/nonsecure/Makefile b/arch/cortex-m23/m2351/src/numaker_pfm_m2351/nonsecure/Makefile index f136afd8..e022fe35 100644 --- a/arch/cortex-m23/m2351/src/numaker_pfm_m2351/nonsecure/Makefile +++ b/arch/cortex-m23/m2351/src/numaker_pfm_m2351/nonsecure/Makefile @@ -77,7 +77,7 @@ $(COBJS_NS): $(OBJDIR)/%$(OBJEXT): %.c $(Q) $(CC) -c $(CFLAGS) $< -o $@ mtower_ns$(EXEEXT): $(OBJS_NS) - $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" libFreeRTOS_ns.a + $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" FREE_RTOS_ARCH=ARM_V8M libFreeRTOS_ns.a $(Q) $(MAKE) -C ../../StdDriver/src/ TOPDIR="$(TOPDIR)" libm2351_StdDriver_ns.a @echo "LD: mTower_ns$(EXEEXT)" $(Q) $(CC) $(CFLAGS) -Wl,--section-start=.text=$(CONFIG_START_ADDRESS_BL33) -Tnonsecure.ld $(OBJS_NS) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/bl33.elf diff --git a/arch/cortex-m33/mps2/src/mps2_an505_qemu/nonsecure/Makefile b/arch/cortex-m33/mps2/src/mps2_an505_qemu/nonsecure/Makefile index ba244521..3d610630 100644 --- a/arch/cortex-m33/mps2/src/mps2_an505_qemu/nonsecure/Makefile +++ b/arch/cortex-m33/mps2/src/mps2_an505_qemu/nonsecure/Makefile @@ -75,7 +75,6 @@ OBJS_NS = $(AOBJS_NS) $(COBJS_NS) LIBPATHS = -L. -L"$(TOPDIR)/lib" -# LIBS = -lm -lc -lnosys -lStdDriver_ns -lnsc -lFreeRTOS_ns LIBS = -lm -lc -lnosys -lnsc -lFreeRTOS_ns $(AOBJS_NS): $(OBJDIR)/%$(OBJEXT): %.S @@ -90,7 +89,7 @@ $(COBJS_NS): $(OBJDIR)/%$(OBJEXT): %.c $(Q) $(CC) -c $(CFLAGS) $< -o $@ mtower_ns$(EXEEXT): $(OBJS_NS) - $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" libFreeRTOS_ns.a + $(Q) $(MAKE) -C $(TOPDIR)/freertos/ TOPDIR="$(TOPDIR)" FREE_RTOS_ARCH=ARM_V8M libFreeRTOS_ns.a # $(Q) $(MAKE) -C ../../StdDriver/src/ TOPDIR="$(TOPDIR)" libStdDriver_ns.a @echo "LD: mTower_ns$(EXEEXT)" $(Q) $(CC) $(CFLAGS) -Tnonsecure.ld $(OBJS_NS) $(LIBPATHS) $(LIBS) -Wl,-Map=output.map -o $(OBJDIR)/bl33.elf diff --git a/arch/riscv32/Kconfig b/arch/riscv32/Kconfig new file mode 100644 index 00000000..5966ff7b --- /dev/null +++ b/arch/riscv32/Kconfig @@ -0,0 +1,36 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the docs folder of mTower repository. +# + +choice + prompt "MCU Family" + default FE310 + +config ARCH_FAMILY_FE310 + bool "FE310" + ---help--- + The FE310 architecture + +config ARCH_FAMILY_BL808 + bool "BL808" + ---help--- + The BL808 architecture + +endchoice + +config ARCH_FAMILY + string + default "fe310" if ARCH_FAMILY_FE310 + default "bl808" if ARCH_FAMILY_BL808 + +if ARCH_FAMILY_FE310 +comment "FE310 Configuration Options" +source arch/riscv32/fe310/Kconfig +endif + +if ARCH_FAMILY_BL808 +comment "BL808 Configuration Options" +source arch/riscv32/bl808/Kconfig +endif + \ No newline at end of file diff --git a/arch/riscv32/fe310/Kconfig b/arch/riscv32/fe310/Kconfig new file mode 100644 index 00000000..188955dd --- /dev/null +++ b/arch/riscv32/fe310/Kconfig @@ -0,0 +1,2481 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the docs folder of mTower repository. +# + +choice + prompt "FE310 platform selection" + default PLATFORM_SPARKFUN_RED_BOARD + +config PLATFORM_SPARKFUN_RED_BOARD + bool "Sparkfun RED board" + ---help--- + Sparkfun RED board. + +endchoice + +config PLATFORM + string + default "sparkfun_redboard" if PLATFORM_SPARKFUN_RED_BOARD + + +if PLATFORM_SPARKFUN_RED_BOARD +#comment "Sparkfun RED board Peripheral Configuration Options" +# source arch/riscv32/fe310/src/sparkfun_redboard/Kconfig +endif # PLATFORM_SPARKFUN_RED_BOARD + +choice + prompt "Non-secure debug UART configuration" + default NONSECURE_DEBUG_UART1 + +config NONSECURE_DEBUG_UART0 + bool "UART0" + ---help--- + UART0 is non-secure debug port. + +config NONSECURE_DEBUG_UART1 + bool "UART1" + ---help--- + UART1 is non-secure debug port. + +config NONSECURE_DEBUG_UART2 + bool "UART2" + ---help--- + UART2 is non-secure debug port. + +config NONSECURE_DEBUG_UART3 + bool "UART3" + ---help--- + UART3 is non-secure debug port. + +config NONSECURE_DEBUG_UART4 + bool "UART4" + ---help--- + UART4 is non-secure debug port. + +config NONSECURE_DEBUG_UART5 + bool "UART5" + ---help--- + UART5 is non-secure debug port. +endchoice + +config NONSECURE_DEBUG_UART + string + default "UART0_NS" if NONSECURE_DEBUG_UART0 + default "UART1_NS" if NONSECURE_DEBUG_UART1 + default "UART2_NS" if NONSECURE_DEBUG_UART2 + default "UART3_NS" if NONSECURE_DEBUG_UART3 + default "UART4_NS" if NONSECURE_DEBUG_UART4 + default "UART5_NS" if NONSECURE_DEBUG_UART5 + +choice + prompt "Non-secure debug font color configuration" + default NONSECURE_DEBUG_RED + +config NONSECURE_FONT_RED + bool "RED" + ---help--- + Red is non-secure debug color. + +config NONSECURE_FONT_GREEN + bool "GREEN" + ---help--- + Green is non-secure debug color. + +config NONSECURE_FONT_YELLOW + bool "YELLOW" + ---help--- + Yellow is non-secure debug color. + +config NONSECURE_FONT_BLUE + bool "BLUE" + ---help--- + Blue is non-secure debug color. + +config NONSECURE_FONT_GRAY + bool "GRAY" + ---help--- + Gray is non-secure debug color. +endchoice + +config NONSECURE_FONT_COLOR + int + default 1 if NONSECURE_FONT_RED + default 2 if NONSECURE_FONT_GREEN + default 3 if NONSECURE_FONT_YELLOW + default 4 if NONSECURE_FONT_BLUE + default 7 if NONSECURE_FONT_GRAY + +choice + prompt "Secure debug UART configuration" + default SECURE_DEBUG_UART0 + +config SECURE_DEBUG_UART0 + bool "UART0" + ---help--- + UART0 is secure debug port. + +config SECURE_DEBUG_UART1 + bool "UART1" + ---help--- + UART1 is secure debug port. + +config SECURE_DEBUG_UART2 + bool "UART2" + ---help--- + UART2 is secure debug port. + +config SECURE_DEBUG_UART3 + bool "UART3" + ---help--- + UART3 is secure debug port. + +config SECURE_DEBUG_UART4 + bool "UART4" + ---help--- + UART4 is secure debug port. + +config SECURE_DEBUG_UART5 + bool "UART5" + ---help--- + UART5 is secure debug port. +endchoice + +config SECURE_DEBUG_UART + string + default "UART0" if SECURE_DEBUG_UART0 && !NONSECURE_DEBUG_UART0 + default "UART1" if SECURE_DEBUG_UART1 && !NONSECURE_DEBUG_UART1 + default "UART2" if SECURE_DEBUG_UART2 && !NONSECURE_DEBUG_UART2 + default "UART3" if SECURE_DEBUG_UART3 && !NONSECURE_DEBUG_UART3 + default "UART4" if SECURE_DEBUG_UART4 && !NONSECURE_DEBUG_UART4 + default "UART5" if SECURE_DEBUG_UART5 && !NONSECURE_DEBUG_UART5 + default "UART0_NS" if SECURE_DEBUG_UART0 && NONSECURE_DEBUG_UART0 + default "UART1_NS" if SECURE_DEBUG_UART1 && NONSECURE_DEBUG_UART1 + default "UART2_NS" if SECURE_DEBUG_UART2 && NONSECURE_DEBUG_UART2 + default "UART3_NS" if SECURE_DEBUG_UART3 && NONSECURE_DEBUG_UART3 + default "UART4_NS" if SECURE_DEBUG_UART4 && NONSECURE_DEBUG_UART4 + default "UART5_NS" if SECURE_DEBUG_UART5 && NONSECURE_DEBUG_UART5 + +choice + prompt "Secure debug font color configuration" + default SECURE_DEBUG_RED + +config SECURE_FONT_RED + bool "RED" + ---help--- + Red is secure debug color. + +config SECURE_FONT_GREEN + bool "GREEN" + ---help--- + Green is secure debug color. + +config SECURE_FONT_YELLOW + bool "YELLOW" + ---help--- + Yellow is secure debug color. + +config SECURE_FONT_BLUE + bool "BLUE" + ---help--- + Blue is secure debug color. + +config SECURE_FONT_GRAY + bool "GRAY" + ---help--- + Gray is secure debug color. +endchoice + +config SECURE_FONT_COLOR + int + default 1 if SECURE_FONT_RED + default 2 if SECURE_FONT_GREEN + default 3 if SECURE_FONT_YELLOW + default 4 if SECURE_FONT_BLUE + default 7 if NONSECURE_FONT_GRAY + +menu "Secure Attribution Configuration" + +menu "GPIO Secure Attribution Configuration" + +choice + prompt "Port A secure configuration" + default GPIO_SECURE_PA + +config GPIO_NONSECURE_PA + bool "PA non-secure" + ---help--- + GPIO PA is non-secure. + +config GPIO_SECURE_PA + bool "PA secure" + ---help--- + GPIO PA is secure. +endchoice + +choice + prompt "Port B secure configuration" + default GPIO_SECURE_PB + +config GPIO_NONSECURE_PB + bool "PB non-secure" + ---help--- + GPIO PB is non-secure. + +config GPIO_SECURE_PB + bool "PB secure" + ---help--- + GPIO PB is secure. +endchoice + +choice + prompt "Port C secure configuration" + default GPIO_SECURE_PC + +config GPIO_NONSECURE_PC + bool "PC non-secure" + ---help--- + GPIO PC is non-secure. + +config GPIO_SECURE_PC + bool "PC secure" + ---help--- + GPIO PC is secure. +endchoice + +choice + prompt "Port D secure configuration" + default GPIO_SECURE_PD + +config GPIO_NONSECURE_PD + bool "PD non-secure" + ---help--- + GPIO PD is non-secure. + +config GPIO_SECURE_PD + bool "PD secure" + ---help--- + GPIO PD is secure. +endchoice + +choice + prompt "Port E secure configuration" + default GPIO_SECURE_PE + +config GPIO_NONSECURE_PE + bool "PE non-secure" + ---help--- + GPIO PE is non-secure. + +config GPIO_SECURE_PE + bool "PE secure" + ---help--- + GPIO PE is secure. +endchoice + +choice + prompt "Port F secure configuration" + default GPIO_SECURE_PF + +config GPIO_NONSECURE_PF + bool "PF non-secure" + ---help--- + GPIO PF is non-secure. + +config GPIO_SECURE_PF + bool "PF secure" + ---help--- + GPIO PF is secure. +endchoice + +choice + prompt "Port G secure configuration" + default GPIO_SECURE_PG + +config GPIO_NONSECURE_PG + bool "PG non-secure" + ---help--- + GPIO PG is non-secure. + +config GPIO_SECURE_PG + bool "PG secure" + ---help--- + GPIO PG is secure. +endchoice + +choice + prompt "Port H secure configuration" + default GPIO_SECURE_PH + +config GPIO_NONSECURE_PH + bool "PH non-secure" + ---help--- + GPIO PH is non-secure. + +config GPIO_SECURE_PH + bool "PH secure" + ---help--- + GPIO PH is secure. +endchoice + +endmenu # GPIO Secure Attribution Configuration + +choice + prompt "Secure SRAM size" + default SCU_SECURE_SRAM_32 + +config SCU_SECURE_SRAM_0 + bool "Secure SRAM 0KB" +config SCU_SECURE_SRAM_8 + bool "Secure SRAM 8KB" +config SCU_SECURE_SRAM_16 + bool "Secure SRAM 16KB" +config SCU_SECURE_SRAM_24 + bool "Secure SRAM 24KB" +config SCU_SECURE_SRAM_32 + bool "Secure SRAM 32KB" +config SCU_SECURE_SRAM_40 + bool "Secure SRAM 40KB" +config SCU_SECURE_SRAM_48 + bool "Secure SRAM 48KB" +config SCU_SECURE_SRAM_56 + bool "Secure SRAM 56KB" +config SCU_SECURE_SRAM_64 + bool "Secure SRAM 64KB" +config SCU_SECURE_SRAM_72 + bool "Secure SRAM 72KB" +config SCU_SECURE_SRAM_80 + bool "Secure SRAM 80KB" +config SCU_SECURE_SRAM_88 + bool "Secure SRAM 88KB" +config SCU_SECURE_SRAM_96 + bool "Secure SRAM 96KB" +endchoice + +config SCU_SECURE_SRAM_SIZE + hex + default 0x0000 if SCU_SECURE_SRAM_0 + default 0x2000 if SCU_SECURE_SRAM_8 + default 0x4000 if SCU_SECURE_SRAM_16 + default 0x6000 if SCU_SECURE_SRAM_24 + default 0x8000 if SCU_SECURE_SRAM_32 + default 0xA000 if SCU_SECURE_SRAM_40 + default 0xC000 if SCU_SECURE_SRAM_48 + default 0xE000 if SCU_SECURE_SRAM_56 + default 0x10000 if SCU_SECURE_SRAM_64 + default 0x12000 if SCU_SECURE_SRAM_72 + default 0x14000 if SCU_SECURE_SRAM_80 + default 0x16000 if SCU_SECURE_SRAM_88 + default 0x18000 if SCU_SECURE_SRAM_96 + +config FMC_SECURE_ROM_SIZE + hex "Secure Flash ROM Size" + default 0x40000 + range 0x1000 0x40000 + ---help--- + "Secure Flash ROM Size." + +menu "Peripheral Secure Attribution Configuration" + +choice + prompt "USBH secure configuration" + default USBH_SECURE + +config USBH_NONSECURE + bool "USBH non-secure" + ---help--- + USBH is non-secure. + +config USBH_SECURE + bool "USBH secure" + ---help--- + USBH is secure. +endchoice + +choice + prompt "SDO secure configuration" + default SDO_SECURE + +config SDO_NONSECURE + bool "SDO non-secure" + ---help--- + SDO is non-secure. + +config SDO_SECURE + bool "SDO secure" + ---help--- + SDO is secure. +endchoice + +choice + prompt "EBI secure configuration" + default EBI_SECURE + +config EBI_NONSECURE + bool "EBI non-secure" + ---help--- + EBI is non-secure. + +config EBI_SECURE + bool "EBI secure" + ---help--- + EBI is secure. +endchoice + +choice + prompt "PDMA1 secure configuration" + default PDMA1_SECURE + +config PDMA1_NONSECURE + bool "PDMA1 non-secure" + ---help--- + PDMA1 is non-secure. + +config PDMA1_SECURE + bool "PDMA1 secure" + ---help--- + PDMA1 is secure. +endchoice + +choice + prompt "CRC secure configuration" + default CRC_SECURE + +config CRC_NONSECURE + bool "CRC non-secure" + ---help--- + CRC is non-secure. + +config CRC_SECURE + bool "CRC secure" + ---help--- + CRC is secure. +endchoice + +choice + prompt "CRPT secure configuration" + default CRPT_SECURE + +config CRPT_NONSECURE + bool "CRPT non-secure" + ---help--- + CRPT is non-secure. + +config CRPT_SECURE + bool "CRPT secure" + ---help--- + CRPT is secure. +endchoice + +choice + prompt "RTC secure configuration" + default RTC_SECURE + +config RTC_NONSECURE + bool "RTC non-secure" + ---help--- + RTC is non-secure. + +config RTC_SECURE + bool "RTC secure" + ---help--- + RTC is secure. +endchoice + +choice + prompt "EADC secure configuration" + default EADC_SECURE + +config EADC_NONSECURE + bool "EADC non-secure" + ---help--- + EADC is non-secure. + +config EADC_SECURE + bool "EADC secure" + ---help--- + EADC is secure. +endchoice + +choice + prompt "ACMP01 secure configuration" + default ACMP01_SECURE + +config ACMP01_NONSECURE + bool "ACMP01 non-secure" + ---help--- + ACMP01 is non-secure. + +config ACMP01_SECURE + bool "ACMP01 secure" + ---help--- + ACMP01 is secure. +endchoice + +choice + prompt "DAC secure configuration" + default DAC_SECURE + +config DAC_NONSECURE + bool "DAC non-secure" + ---help--- + DAC is non-secure. + +config DAC_SECURE + bool "DAC secure" + ---help--- + DAC is secure. +endchoice + +choice + prompt "I2S0 secure configuration" + default I2S0_SECURE + +config I2S0_NONSECURE + bool "I2S0 non-secure" + ---help--- + I2S0 is non-secure. + +config I2S0_SECURE + bool "I2S0 secure" + ---help--- + I2S0 is secure. +endchoice + +choice + prompt "OTG secure configuration" + default OTG_SECURE + +config OTG_NONSECURE + bool "OTG non-secure" + ---help--- + OTG is non-secure. + +config OTG_SECURE + bool "OTG secure" + ---help--- + OTG is secure. +endchoice + +choice + prompt "TMR23 secure configuration" + default TMR23_SECURE + +config TMR23_NONSECURE + bool "TMR23 non-secure" + ---help--- + TMR23 is non-secure. + +config TMR23_SECURE + bool "TMR23 secure" + ---help--- + TMR23 is secure. +endchoice + +choice + prompt "EPWM0 secure configuration" + default EPWM0_SECURE + +config EPWM0_NONSECURE + bool "EPWM0 non-secure" + ---help--- + EPWM0 is non-secure. + +config EPWM0_SECURE + bool "EPWM0 secure" + ---help--- + EPWM0 is secure. +endchoice + +choice + prompt "EPWM1 secure configuration" + default EPWM1_SECURE + +config EPWM1_NONSECURE + bool "EPWM1 non-secure" + ---help--- + EPWM1 is non-secure. + +config EPWM1_SECURE + bool "EPWM1 secure" + ---help--- + EPWM1 is secure. +endchoice + +choice + prompt "BPWM0 secure configuration" + default BPWM0_SECURE + +config BPWM0_NONSECURE + bool "BPWM0 non-secure" + ---help--- + BPWM0 is non-secure. + +config BPWM0_SECURE + bool "BPWM0 secure" + ---help--- + BPWM0 is secure. +endchoice + +choice + prompt "BPWM1 secure configuration" + default BPWM1_SECURE + +config BPWM1_NONSECURE + bool "BPWM1 non-secure" + ---help--- + BPWM1 is non-secure. + +config BPWM1_SECURE + bool "BPWM1 secure" + ---help--- + BPWM1 is secure. +endchoice + +choice + prompt "QSPI0 secure configuration" + default QSPI0_SECURE + +config QSPI0_NONSECURE + bool "QSPI0 non-secure" + ---help--- + QSPI0 is non-secure. + +config QSPI0_SECURE + bool "QSPI0 secure" + ---help--- + QSPI0 is secure. +endchoice + +choice + prompt "SPI0 secure configuration" + default SPI0_SECURE + +config SPI0_NONSECURE + bool "SPI0 non-secure" + ---help--- + SPI0 is non-secure. + +config SPI0_SECURE + bool "SPI0 secure" + ---help--- + SPI0 is secure. +endchoice + +choice + prompt "SPI1 secure configuration" + default SPI1_SECURE + +config SPI1_NONSECURE + bool "SPI1 non-secure" + ---help--- + SPI1 is non-secure. + +config SPI1_SECURE + bool "SPI1 secure" + ---help--- + SPI1 is secure. +endchoice + +choice + prompt "SPI2 secure configuration" + default SPI2_SECURE + +config SPI2_NONSECURE + bool "SPI2 non-secure" + ---help--- + SPI2 is non-secure. + +config SPI2_SECURE + bool "SPI2 secure" + ---help--- + SPI2 is secure. +endchoice + +choice + prompt "SPI3 secure configuration" + default SPI3_SECURE + +config SPI3_NONSECURE + bool "SPI3 non-secure" + ---help--- + SPI3 is non-secure. + +config SPI3_SECURE + bool "SPI3 secure" + ---help--- + SPI3 is secure. +endchoice + +choice + prompt "UART0 secure configuration" + default UART0_SECURE + +config UART0_NONSECURE + bool "UART0 non-secure" + ---help--- + UART0 is non-secure. + +config UART0_SECURE + bool "UART0 secure" + ---help--- + UART0 is secure. +endchoice + +choice + prompt "UART1 secure configuration" + default UART1_SECURE + +config UART1_NONSECURE + bool "UART1 non-secure" + ---help--- + UART1 is non-secure. + +config UART1_SECURE + bool "UART1 secure" + ---help--- + UART1 is secure. +endchoice + +choice + prompt "UART2 secure configuration" + default UART2_SECURE + +config UART2_NONSECURE + bool "UART2 non-secure" + ---help--- + UART2 is non-secure. + +config UART2_SECURE + bool "UART2 secure" + ---help--- + UART2 is secure. +endchoice + +choice + prompt "UART3 secure configuration" + default UART3_SECURE + +config UART3_NONSECURE + bool "UART3 non-secure" + ---help--- + UART3 is non-secure. + +config UART3_SECURE + bool "UART3 secure" + ---help--- + UART3 is secure. +endchoice + +choice + prompt "UART4 secure configuration" + default UART4_SECURE + +config UART4_NONSECURE + bool "UART4 non-secure" + ---help--- + UART4 is non-secure. + +config UART4_SECURE + bool "UART4 secure" + ---help--- + UART4 is secure. +endchoice + +choice + prompt "UART5 secure configuration" + default UART5_SECURE + +config UART5_NONSECURE + bool "UART5 non-secure" + ---help--- + UART5 is non-secure. + +config UART5_SECURE + bool "UART5 secure" + ---help--- + UART5 is secure. +endchoice + +choice + prompt "I2C0 secure configuration" + default I2C0_SECURE + +config I2C0_NONSECURE + bool "I2C0 non-secure" + ---help--- + I2C0 is non-secure. + +config I2C0_SECURE + bool "I2C0 secure" + ---help--- + I2C0 is secure. +endchoice + +choice + prompt "I2C1 secure configuration" + default I2C1_SECURE + +config I2C1_NONSECURE + bool "I2C1 non-secure" + ---help--- + I2C1 is non-secure. + +config I2C1_SECURE + bool "I2C1 secure" + ---help--- + I2C1 is secure. +endchoice + +choice + prompt "I2C2 secure configuration" + default I2C2_SECURE + +config I2C2_NONSECURE + bool "I2C2 non-secure" + ---help--- + I2C2 is non-secure. + +config I2C2_SECURE + bool "I2C2 secure" + ---help--- + I2C2 is secure. +endchoice + +choice + prompt "SC0 secure configuration" + default SC0_SECURE + +config SC0_NONSECURE + bool "SC0 non-secure" + ---help--- + SC0 is non-secure. + +config SC0_SECURE + bool "SC0 secure" + ---help--- + SC0 is secure. +endchoice + +choice + prompt "SC1 secure configuration" + default SC1_SECURE + +config SC1_NONSECURE + bool "SC1 non-secure" + ---help--- + SC1 is non-secure. + +config SC1_SECURE + bool "SC1 secure" + ---help--- + SC1 is secure. +endchoice + +choice + prompt "SC2 secure configuration" + default SC2_SECURE + +config SC2_NONSECURE + bool "SC2 non-secure" + ---help--- + SC2 is non-secure. + +config SC2_SECURE + bool "SC2 secure" + ---help--- + SC2 is secure. +endchoice + +choice + prompt "CAN0 secure configuration" + default CAN0_SECURE + +config CAN0_NONSECURE + bool "CAN0 non-secure" + ---help--- + CAN0 is non-secure. + +config CAN0_SECURE + bool "CAN0 secure" + ---help--- + CAN0 is secure. +endchoice + +choice + prompt "QEI0 secure configuration" + default QEI0_SECURE + +config QEI0_NONSECURE + bool "QEI0 non-secure" + ---help--- + QEI0 is non-secure. + +config QEI0_SECURE + bool "QEI0 secure" + ---help--- + QEI0 is secure. +endchoice + +choice + prompt "QEI1 secure configuration" + default QEI1_SECURE + +config QEI1_NONSECURE + bool "QEI1 non-secure" + ---help--- + QEI1 is non-secure. + +config QEI1_SECURE + bool "QEI1 secure" + ---help--- + QEI1 is secure. +endchoice + +choice + prompt "ECAP0 secure configuration" + default ECAP0_SECURE + +config ECAP0_NONSECURE + bool "ECAP0 non-secure" + ---help--- + ECAP0 is non-secure. + +config ECAP0_SECURE + bool "ECAP0 secure" + ---help--- + ECAP0 is secure. +endchoice + +choice + prompt "ECAP1 secure configuration" + default ECAP1_SECURE + +config ECAP1_NONSECURE + bool "ECAP1 non-secure" + ---help--- + ECAP1 is non-secure. + +config ECAP1_SECURE + bool "ECAP1 secure" + ---help--- + ECAP1 is secure. +endchoice + +choice + prompt "TRNG secure configuration" + default TRNG_SECURE + +config TRNG_NONSECURE + bool "TRNG non-secure" + ---help--- + TRNG is non-secure. + +config TRNG_SECURE + bool "TRNG secure" + ---help--- + TRNG is secure. +endchoice + +choice + prompt "USBD secure configuration" + default USBD_SECURE + +config USBD_NONSECURE + bool "USBD non-secure" + ---help--- + USBD is non-secure. + +config USBD_SECURE + bool "USBD secure" + ---help--- + USBD is secure. +endchoice + +choice + prompt "USCI0 secure configuration" + default USCI0_SECURE + +config USCI0_NONSECURE + bool "USCI0 non-secure" + ---help--- + USCI0 is non-secure. + +config USCI0_SECURE + bool "USCI0 secure" + ---help--- + USCI0 is secure. +endchoice + +choice + prompt "USCI1 secure configuration" + default USCI1_SECURE + +config USCI1_NONSECURE + bool "USCI1 non-secure" + ---help--- + USCI1 is non-secure. + +config USCI1_SECURE + bool "USCI1 secure" + ---help--- + USCI1 is secure. +endchoice + +endmenu # Peripheral Secure Attribution Configuration + +menu "Assign Interrupt to Secure or Non-secure Vector" +choice + prompt "RTC Interrupt target secure configuration" + default RTC_INTERRUPT_SECURE + +config RTC_INTERRUPT_NONSECURE + bool "RTC interrupt non-secure" + ---help--- + RTC interrupt is non-secure. + +config RTC_INTERRUPT_SECURE + bool "RTC interrupt secure" + ---help--- + RTC interrupt is secure. +endchoice + +choice + prompt "TAMPER Interrupt target secure configuration" + default TAMPER_INTERRUPT_SECURE + +config TAMPER_INTERRUPT_NONSECURE + bool "TAMPER interrupt non-secure" + ---help--- + TAMPER interrupt is non-secure. + +config TAMPER_INTERRUPT_SECURE + bool "TAMPER interrupt secure" + ---help--- + TAMPER interrupt is secure. +endchoice + +choice + prompt "EINT0 Interrupt target secure configuration" + default EINT0_INTERRUPT_SECURE + +config EINT0_INTERRUPT_NONSECURE + bool "EINT0 interrupt non-secure" + ---help--- + EINT0 interrupt is non-secure. + +config EINT0_INTERRUPT_SECURE + bool "EINT0 interrupt secure" + ---help--- + EINT0 interrupt is secure. +endchoice + +choice + prompt "EINT1 Interrupt target secure configuration" + default EINT1_INTERRUPT_SECURE + +config EINT1_INTERRUPT_NONSECURE + bool "EINT1 interrupt non-secure" + ---help--- + EINT1 interrupt is non-secure. + +config EINT1_INTERRUPT_SECURE + bool "EINT1 interrupt secure" + ---help--- + EINT1 interrupt is secure. +endchoice + +choice + prompt "EINT2 Interrupt target secure configuration" + default EINT2_INTERRUPT_SECURE + +config EINT2_INTERRUPT_NONSECURE + bool "EINT2 interrupt non-secure" + ---help--- + EINT2 interrupt is non-secure. + +config EINT2_INTERRUPT_SECURE + bool "EINT2 interrupt secure" + ---help--- + EINT2 interrupt is secure. +endchoice + +choice + prompt "EINT3 Interrupt target secure configuration" + default EINT3_INTERRUPT_SECURE + +config EINT3_INTERRUPT_NONSECURE + bool "EINT3 interrupt non-secure" + ---help--- + EINT3 interrupt is non-secure. + +config EINT3_INTERRUPT_SECURE + bool "EINT3 interrupt secure" + ---help--- + EINT3 interrupt is secure. +endchoice + +choice + prompt "EINT4 Interrupt target secure configuration" + default EINT4_INTERRUPT_SECURE + +config EINT4_INTERRUPT_NONSECURE + bool "EINT4 interrupt non-secure" + ---help--- + EINT4 interrupt is non-secure. + +config EINT4_INTERRUPT_SECURE + bool "EINT4 interrupt secure" + ---help--- + EINT4 interrupt is secure. +endchoice + +choice + prompt "EINT5 Interrupt target secure configuration" + default EINT5_INTERRUPT_SECURE + +config EINT5_INTERRUPT_NONSECURE + bool "EINT5 interrupt non-secure" + ---help--- + EINT5 interrupt is non-secure. + +config EINT5_INTERRUPT_SECURE + bool "EINT5 interrupt secure" + ---help--- + EINT5 interrupt is secure. +endchoice + +choice + prompt "GPA Interrupt target secure configuration" + default GPA_INTERRUPT_SECURE + +config GPA_INTERRUPT_NONSECURE + bool "GPA interrupt non-secure" + ---help--- + GPA interrupt is non-secure. + +config GPA_INTERRUPT_SECURE + bool "GPA interrupt secure" + ---help--- + GPA interrupt is secure. +endchoice + +choice + prompt "GPB Interrupt target secure configuration" + default GPB_INTERRUPT_SECURE + +config GPB_INTERRUPT_NONSECURE + bool "GPB interrupt non-secure" + ---help--- + GPB interrupt is non-secure. + +config GPB_INTERRUPT_SECURE + bool "GPB interrupt secure" + ---help--- + GPB interrupt is secure. +endchoice + +choice + prompt "GPC Interrupt target secure configuration" + default GPC_INTERRUPT_SECURE + +config GPC_INTERRUPT_NONSECURE + bool "GPC interrupt non-secure" + ---help--- + GPC interrupt is non-secure. + +config GPC_INTERRUPT_SECURE + bool "GPC interrupt secure" + ---help--- + GPC interrupt is secure. +endchoice + +choice + prompt "GPD Interrupt target secure configuration" + default GPD_INTERRUPT_SECURE + +config GPD_INTERRUPT_NONSECURE + bool "GPD interrupt non-secure" + ---help--- + GPD interrupt is non-secure. + +config GPD_INTERRUPT_SECURE + bool "GPD interrupt secure" + ---help--- + GPD interrupt is secure. +endchoice + +choice + prompt "GPE Interrupt target secure configuration" + default GPE_INTERRUPT_SECURE + +config GPE_INTERRUPT_NONSECURE + bool "GPE interrupt non-secure" + ---help--- + GPE interrupt is non-secure. + +config GPE_INTERRUPT_SECURE + bool "GPE interrupt secure" + ---help--- + GPE interrupt is secure. +endchoice + +choice + prompt "GPF Interrupt target secure configuration" + default GPF_INTERRUPT_SECURE + +config GPF_INTERRUPT_NONSECURE + bool "GPF interrupt non-secure" + ---help--- + GPF interrupt is non-secure. + +config GPF_INTERRUPT_SECURE + bool "GPF interrupt secure" + ---help--- + GPF interrupt is secure. +endchoice + +choice + prompt "QSPI0 Interrupt target secure configuration" + default QSPI0_INTERRUPT_SECURE + +config QSPI0_INTERRUPT_NONSECURE + bool "QSPI0 interrupt non-secure" + ---help--- + QSPI0 interrupt is non-secure. + +config QSPI0_INTERRUPT_SECURE + bool "QSPI0 interrupt secure" + ---help--- + QSPI0 interrupt is secure. +endchoice + +choice + prompt "SPI0 Interrupt target secure configuration" + default SPI0_INTERRUPT_SECURE + +config SPI0_INTERRUPT_NONSECURE + bool "SPI0 interrupt non-secure" + ---help--- + SPI0 interrupt is non-secure. + +config SPI0_INTERRUPT_SECURE + bool "SPI0 interrupt secure" + ---help--- + SPI0 interrupt is secure. +endchoice + +choice + prompt "BRAKE0 Interrupt target secure configuration" + default BRAKE0_INTERRUPT_SECURE + +config BRAKE0_INTERRUPT_NONSECURE + bool "BRAKE0 interrupt non-secure" + ---help--- + BRAKE0 interrupt is non-secure. + +config BRAKE0_INTERRUPT_SECURE + bool "BRAKE0 interrupt secure" + ---help--- + BRAKE0 interrupt is secure. +endchoice + +choice + prompt "EPWM0_P0 Interrupt target secure configuration" + default EPWM0_P0_INTERRUPT_SECURE + +config EPWM0_P0_INTERRUPT_NONSECURE + bool "EPWM0_P0 interrupt non-secure" + ---help--- + EPWM0_P0 interrupt is non-secure. + +config EPWM0_P0_INTERRUPT_SECURE + bool "EPWM0_P0 interrupt secure" + ---help--- + EPWM0_P0 interrupt is secure. +endchoice + +choice + prompt "EPWM0_P1 Interrupt target secure configuration" + default EPWM0_P1_INTERRUPT_SECURE + +config EPWM0_P1_INTERRUPT_NONSECURE + bool "EPWM0_P1 interrupt non-secure" + ---help--- + EPWM0_P1 interrupt is non-secure. + +config EPWM0_P1_INTERRUPT_SECURE + bool "EPWM0_P1 interrupt secure" + ---help--- + EPWM0_P1 interrupt is secure. +endchoice + +choice + prompt "EPWM0_P2 Interrupt target secure configuration" + default EPWM0_P2_INTERRUPT_SECURE + +config EPWM0_P2_INTERRUPT_NONSECURE + bool "EPWM0_P2 interrupt non-secure" + ---help--- + EPWM0_P2 interrupt is non-secure. + +config EPWM0_P2_INTERRUPT_SECURE + bool "EPWM0_P2 interrupt secure" + ---help--- + EPWM0_P2 interrupt is secure. +endchoice + +choice + prompt "BRAKE1 Interrupt target secure configuration" + default BRAKE1_INTERRUPT_SECURE + +config BRAKE1_INTERRUPT_NONSECURE + bool "BRAKE1 interrupt non-secure" + ---help--- + BRAKE1 interrupt is non-secure. + +config BRAKE1_INTERRUPT_SECURE + bool "BRAKE1 interrupt secure" + ---help--- + BRAKE1 interrupt is secure. +endchoice + +choice + prompt "EPWM1_P0 Interrupt target secure configuration" + default EPWM1_P0_INTERRUPT_SECURE + +config EPWM1_P0_INTERRUPT_NONSECURE + bool "EPWM1_P0 interrupt non-secure" + ---help--- + EPWM1_P0 interrupt is non-secure. + +config EPWM1_P0_INTERRUPT_SECURE + bool "EPWM1_P0 interrupt secure" + ---help--- + EPWM1_P0 interrupt is secure. +endchoice + +choice + prompt "EPWM1_P1 Interrupt target secure configuration" + default EPWM1_P1_INTERRUPT_SECURE + +config EPWM1_P1_INTERRUPT_NONSECURE + bool "EPWM1_P1 interrupt non-secure" + ---help--- + EPWM1_P1 interrupt is non-secure. + +config EPWM1_P1_INTERRUPT_SECURE + bool "EPWM1_P1 interrupt secure" + ---help--- + EPWM1_P1 interrupt is secure. +endchoice + +choice + prompt "EPWM1_P2 Interrupt target secure configuration" + default EPWM1_P2_INTERRUPT_SECURE + +config EPWM1_P2_INTERRUPT_NONSECURE + bool "EPWM1_P2 interrupt non-secure" + ---help--- + EPWM1_P2 interrupt is non-secure. + +config EPWM1_P2_INTERRUPT_SECURE + bool "EPWM1_P2 interrupt secure" + ---help--- + EPWM1_P2 interrupt is secure. +endchoice + +choice + prompt "TMR2 Interrupt target secure configuration" + default TMR2_INTERRUPT_SECURE + +config TMR2_INTERRUPT_NONSECURE + bool "TMR2 interrupt non-secure" + ---help--- + TMR2 interrupt is non-secure. + +config TMR2_INTERRUPT_SECURE + bool "TMR2 interrupt secure" + ---help--- + TMR2 interrupt is secure. +endchoice + +choice + prompt "TMR3 Interrupt target secure configuration" + default TMR3_INTERRUPT_SECURE + +config TMR3_INTERRUPT_NONSECURE + bool "TMR3 interrupt non-secure" + ---help--- + TMR3 interrupt is non-secure. + +config TMR3_INTERRUPT_SECURE + bool "TMR3 interrupt secure" + ---help--- + TMR3 interrupt is secure. +endchoice + +choice + prompt "UART0 Interrupt target secure configuration" + default UART0_INTERRUPT_SECURE + +config UART0_INTERRUPT_NONSECURE + bool "UART0 interrupt non-secure" + ---help--- + UART0 interrupt is non-secure. + +config UART0_INTERRUPT_SECURE + bool "UART0 interrupt secure" + ---help--- + UART0 interrupt is secure. +endchoice + +choice + prompt "UART1 Interrupt target secure configuration" + default UART1_INTERRUPT_SECURE + +config UART1_INTERRUPT_NONSECURE + bool "UART1 interrupt non-secure" + ---help--- + UART1 interrupt is non-secure. + +config UART1_INTERRUPT_SECURE + bool "UART1 interrupt secure" + ---help--- + UART1 interrupt is secure. +endchoice + +choice + prompt "I2C0 Interrupt target secure configuration" + default I2C0_INTERRUPT_SECURE + +config I2C0_INTERRUPT_NONSECURE + bool "I2C0 interrupt non-secure" + ---help--- + I2C0 interrupt is non-secure. + +config I2C0_INTERRUPT_SECURE + bool "I2C0 interrupt secure" + ---help--- + I2C0 interrupt is secure. +endchoice + +choice + prompt "I2C1 Interrupt target secure configuration" + default I2C1_INTERRUPT_SECURE + +config I2C1_INTERRUPT_NONSECURE + bool "I2C1 interrupt non-secure" + ---help--- + I2C1 interrupt is non-secure. + +config I2C1_INTERRUPT_SECURE + bool "I2C1 interrupt secure" + ---help--- + I2C1 interrupt is secure. +endchoice + +choice + prompt "DAC Interrupt target secure configuration" + default DAC_INTERRUPT_SECURE + +config DAC_INTERRUPT_NONSECURE + bool "DAC interrupt non-secure" + ---help--- + DAC interrupt is non-secure. + +config DAC_INTERRUPT_SECURE + bool "DAC interrupt secure" + ---help--- + DAC interrupt is secure. +endchoice + +choice + prompt "EADC0 Interrupt target secure configuration" + default EADC0_INTERRUPT_SECURE + +config EADC0_INTERRUPT_NONSECURE + bool "EADC0 interrupt non-secure" + ---help--- + EADC0 interrupt is non-secure. + +config EADC0_INTERRUPT_SECURE + bool "EADC0 interrupt secure" + ---help--- + EADC0 interrupt is secure. +endchoice + +choice + prompt "EADC1 Interrupt target secure configuration" + default EADC1_INTERRUPT_SECURE + +config EADC1_INTERRUPT_NONSECURE + bool "EADC1 interrupt non-secure" + ---help--- + EADC1 interrupt is non-secure. + +config EADC1_INTERRUPT_SECURE + bool "EADC1 interrupt secure" + ---help--- + EADC1 interrupt is secure. +endchoice + +choice + prompt "ACMP01 Interrupt target secure configuration" + default ACMP01_INTERRUPT_SECURE + +config ACMP01_INTERRUPT_NONSECURE + bool "ACMP01 interrupt non-secure" + ---help--- + ACMP01 interrupt is non-secure. + +config ACMP01_INTERRUPT_SECURE + bool "ACMP01 interrupt secure" + ---help--- + ACMP01 interrupt is secure. +endchoice + +choice + prompt "EADC2 Interrupt target secure configuration" + default EADC2_INTERRUPT_SECURE + +config EADC2_INTERRUPT_NONSECURE + bool "EADC2 interrupt non-secure" + ---help--- + EADC2 interrupt is non-secure. + +config EADC2_INTERRUPT_SECURE + bool "EADC2 interrupt secure" + ---help--- + EADC2 interrupt is secure. +endchoice + +choice + prompt "EADC3 Interrupt target secure configuration" + default EADC3_INTERRUPT_SECURE + +config EADC3_INTERRUPT_NONSECURE + bool "EADC3 interrupt non-secure" + ---help--- + EADC3 interrupt is non-secure. + +config EADC3_INTERRUPT_SECURE + bool "EADC3 interrupt secure" + ---help--- + EADC3 interrupt is secure. +endchoice + +choice + prompt "UART2 Interrupt target secure configuration" + default UART2_INTERRUPT_SECURE + +config UART2_INTERRUPT_NONSECURE + bool "UART2 interrupt non-secure" + ---help--- + UART2 interrupt is non-secure. + +config UART2_INTERRUPT_SECURE + bool "UART2 interrupt secure" + ---help--- + UART2 interrupt is secure. +endchoice + +choice + prompt "UART3 Interrupt target secure configuration" + default UART3_INTERRUPT_SECURE + +config UART3_INTERRUPT_NONSECURE + bool "UART3 interrupt non-secure" + ---help--- + UART3 interrupt is non-secure. + +config UART3_INTERRUPT_SECURE + bool "UART3 interrupt secure" + ---help--- + UART3 interrupt is secure. +endchoice + +choice + prompt "SPI1 Interrupt target secure configuration" + default SPI1_INTERRUPT_SECURE + +config SPI1_INTERRUPT_NONSECURE + bool "SPI1 interrupt non-secure" + ---help--- + SPI1 interrupt is non-secure. + +config SPI1_INTERRUPT_SECURE + bool "SPI1 interrupt secure" + ---help--- + SPI1 interrupt is secure. +endchoice + +choice + prompt "SPI2 Interrupt target secure configuration" + default SPI2_INTERRUPT_SECURE + +config SPI2_INTERRUPT_NONSECURE + bool "SPI2 interrupt non-secure" + ---help--- + SPI2 interrupt is non-secure. + +config SPI2_INTERRUPT_SECURE + bool "SPI2 interrupt secure" + ---help--- + SPI2 interrupt is secure. +endchoice + +choice + prompt "USBD Interrupt target secure configuration" + default USBD_INTERRUPT_SECURE + +config USBD_INTERRUPT_NONSECURE + bool "USBD interrupt non-secure" + ---help--- + USBD interrupt is non-secure. + +config USBD_INTERRUPT_SECURE + bool "USBD interrupt secure" + ---help--- + USBD interrupt is secure. +endchoice + +choice + prompt "USBH Interrupt target secure configuration" + default USBH_INTERRUPT_SECURE + +config USBH_INTERRUPT_NONSECURE + bool "USBH interrupt non-secure" + ---help--- + USBH interrupt is non-secure. + +config USBH_INTERRUPT_SECURE + bool "USBH interrupt secure" + ---help--- + USBH interrupt is secure. +endchoice + +choice + prompt "USBOTG Interrupt target secure configuration" + default USBOTG_INTERRUPT_SECURE + +config USBOTG_INTERRUPT_NONSECURE + bool "USBOTG interrupt non-secure" + ---help--- + USBOTG interrupt is non-secure. + +config USBOTG_INTERRUPT_SECURE + bool "USBOTG interrupt secure" + ---help--- + USBOTG interrupt is secure. +endchoice + +choice + prompt "CAN0 Interrupt target secure configuration" + default CAN0_INTERRUPT_SECURE + +config CAN0_INTERRUPT_NONSECURE + bool "CAN0 interrupt non-secure" + ---help--- + CAN0 interrupt is non-secure. + +config CAN0_INTERRUPT_SECURE + bool "CAN0 interrupt secure" + ---help--- + CAN0 interrupt is secure. +endchoice + +choice + prompt "SC0 Interrupt target secure configuration" + default SC0_INTERRUPT_SECURE + +config SC0_INTERRUPT_NONSECURE + bool "SC0 interrupt non-secure" + ---help--- + SC0 interrupt is non-secure. + +config SC0_INTERRUPT_SECURE + bool "SC0 interrupt secure" + ---help--- + SC0 interrupt is secure. +endchoice + +choice + prompt "SC1 Interrupt target secure configuration" + default SC1_INTERRUPT_SECURE + +config SC1_INTERRUPT_NONSECURE + bool "SC1 interrupt non-secure" + ---help--- + SC1 interrupt is non-secure. + +config SC1_INTERRUPT_SECURE + bool "SC1 interrupt secure" + ---help--- + SC1 interrupt is secure. +endchoice + +choice + prompt "SC2 Interrupt target secure configuration" + default SC2_INTERRUPT_SECURE + +config SC2_INTERRUPT_NONSECURE + bool "SC2 interrupt non-secure" + ---help--- + SC2 interrupt is non-secure. + +config SC2_INTERRUPT_SECURE + bool "SC2 interrupt secure" + ---help--- + SC2 interrupt is secure. +endchoice + +choice + prompt "SPI3 Interrupt target secure configuration" + default SPI3_INTERRUPT_SECURE + +config SPI3_INTERRUPT_NONSECURE + bool "SPI3 interrupt non-secure" + ---help--- + SPI3 interrupt is non-secure. + +config SPI3_INTERRUPT_SECURE + bool "SPI3 interrupt secure" + ---help--- + SPI3 interrupt is secure. +endchoice + +choice + prompt "SDH0 Interrupt target secure configuration" + default SDH0_INTERRUPT_SECURE + +config SDH0_INTERRUPT_NONSECURE + bool "SDH0 interrupt non-secure" + ---help--- + SDH0 interrupt is non-secure. + +config SDH0_INTERRUPT_SECURE + bool "SDH0 interrupt secure" + ---help--- + SDH0 interrupt is secure. +endchoice + +choice + prompt "I2S0 Interrupt target secure configuration" + default I2S0_INTERRUPT_SECURE + +config I2S0_INTERRUPT_NONSECURE + bool "I2S0 interrupt non-secure" + ---help--- + I2S0 interrupt is non-secure. + +config I2S0_INTERRUPT_SECURE + bool "I2S0 interrupt secure" + ---help--- + I2S0 interrupt is secure. +endchoice + +choice + prompt "CRYPTO Interrupt target secure configuration" + default CRYPTO_INTERRUPT_SECURE + +config CRYPTO_INTERRUPT_NONSECURE + bool "CRYPTO interrupt non-secure" + ---help--- + CRYPTO interrupt is non-secure. + +config CRYPTO_INTERRUPT_SECURE + bool "CRYPTO interrupt secure" + ---help--- + CRYPTO interrupt is secure. +endchoice + +choice + prompt "GPG Interrupt target secure configuration" + default GPG_INTERRUPT_SECURE + +config GPG_INTERRUPT_NONSECURE + bool "GPG interrupt non-secure" + ---help--- + GPG interrupt is non-secure. + +config GPG_INTERRUPT_SECURE + bool "GPG interrupt secure" + ---help--- + GPG interrupt is secure. +endchoice + +choice + prompt "EINT6 Interrupt target secure configuration" + default EINT6_INTERRUPT_SECURE + +config EINT6_INTERRUPT_NONSECURE + bool "EINT6 interrupt non-secure" + ---help--- + EINT6 interrupt is non-secure. + +config EINT6_INTERRUPT_SECURE + bool "EINT6 interrupt secure" + ---help--- + EINT6 interrupt is secure. +endchoice + +choice + prompt "UART4 Interrupt target secure configuration" + default UART4_INTERRUPT_SECURE + +config UART4_INTERRUPT_NONSECURE + bool "UART4 interrupt non-secure" + ---help--- + UART4 interrupt is non-secure. + +config UART4_INTERRUPT_SECURE + bool "UART4 interrupt secure" + ---help--- + UART4 interrupt is secure. +endchoice + +choice + prompt "UART5 Interrupt target secure configuration" + default UART5_INTERRUPT_SECURE + +config UART5_INTERRUPT_NONSECURE + bool "UART5 interrupt non-secure" + ---help--- + UART5 interrupt is non-secure. + +config UART5_INTERRUPT_SECURE + bool "UART5 interrupt secure" + ---help--- + UART5 interrupt is secure. +endchoice + +choice + prompt "USCI0 Interrupt target secure configuration" + default USCI0_INTERRUPT_SECURE + +config USCI0_INTERRUPT_NONSECURE + bool "USCI0 interrupt non-secure" + ---help--- + USCI0 interrupt is non-secure. + +config USCI0_INTERRUPT_SECURE + bool "USCI0 interrupt secure" + ---help--- + USCI0 interrupt is secure. +endchoice + +choice + prompt "USCI1 Interrupt target secure configuration" + default USCI1_INTERRUPT_SECURE + +config USCI1_INTERRUPT_NONSECURE + bool "USCI1 interrupt non-secure" + ---help--- + USCI1 interrupt is non-secure. + +config USCI1_INTERRUPT_SECURE + bool "USCI1 interrupt secure" + ---help--- + USCI1 interrupt is secure. +endchoice + +choice + prompt "BPWM0 Interrupt target secure configuration" + default BPWM0_INTERRUPT_SECURE + +config BPWM0_INTERRUPT_NONSECURE + bool "BPWM0 interrupt non-secure" + ---help--- + BPWM0 interrupt is non-secure. + +config BPWM0_INTERRUPT_SECURE + bool "BPWM0 interrupt secure" + ---help--- + BPWM0 interrupt is secure. +endchoice + +choice + prompt "BPWM1 Interrupt target secure configuration" + default BPWM1_INTERRUPT_SECURE + +config BPWM1_INTERRUPT_NONSECURE + bool "BPWM1 interrupt non-secure" + ---help--- + BPWM1 interrupt is non-secure. + +config BPWM1_INTERRUPT_SECURE + bool "BPWM1 interrupt secure" + ---help--- + BPWM1 interrupt is secure. +endchoice + +choice + prompt "I2C2 Interrupt target secure configuration" + default I2C2_INTERRUPT_SECURE + +config I2C2_INTERRUPT_NONSECURE + bool "I2C2 interrupt non-secure" + ---help--- + I2C2 interrupt is non-secure. + +config I2C2_INTERRUPT_SECURE + bool "I2C2 interrupt secure" + ---help--- + I2C2 interrupt is secure. +endchoice + +choice + prompt "QEI0 Interrupt target secure configuration" + default QEI0_INTERRUPT_SECURE + +config QEI0_INTERRUPT_NONSECURE + bool "QEI0 interrupt non-secure" + ---help--- + QEI0 interrupt is non-secure. + +config QEI0_INTERRUPT_SECURE + bool "QEI0 interrupt secure" + ---help--- + QEI0 interrupt is secure. +endchoice + +choice + prompt "QEI1 Interrupt target secure configuration" + default QEI1_INTERRUPT_SECURE + +config QEI1_INTERRUPT_NONSECURE + bool "QEI1 interrupt non-secure" + ---help--- + QEI1 interrupt is non-secure. + +config QEI1_INTERRUPT_SECURE + bool "QEI1 interrupt secure" + ---help--- + QEI1 interrupt is secure. +endchoice + +choice + prompt "ECAP0 Interrupt target secure configuration" + default ECAP0_INTERRUPT_SECURE + +config ECAP0_INTERRUPT_NONSECURE + bool "ECAP0 interrupt non-secure" + ---help--- + ECAP0 interrupt is non-secure. + +config ECAP0_INTERRUPT_SECURE + bool "ECAP0 interrupt secure" + ---help--- + ECAP0 interrupt is secure. +endchoice + +choice + prompt "ECAP1 Interrupt target secure configuration" + default ECAP1_INTERRUPT_SECURE + +config ECAP1_INTERRUPT_NONSECURE + bool "ECAP1 interrupt non-secure" + ---help--- + ECAP1 interrupt is non-secure. + +config ECAP1_INTERRUPT_SECURE + bool "ECAP1 interrupt secure" + ---help--- + ECAP1 interrupt is secure. +endchoice + +choice + prompt "GPH Interrupt target secure configuration" + default GPH_INTERRUPT_SECURE + +config GPH_INTERRUPT_NONSECURE + bool "GPH interrupt non-secure" + ---help--- + GPH interrupt is non-secure. + +config GPH_INTERRUPT_SECURE + bool "GPH interrupt secure" + ---help--- + GPH interrupt is secure. +endchoice + +choice + prompt "EINT7 Interrupt target secure configuration" + default EINT7_INTERRUPT_SECURE + +config EINT7_INTERRUPT_NONSECURE + bool "EINT7 interrupt non-secure" + ---help--- + EINT7 interrupt is non-secure. + +config EINT7_INTERRUPT_SECURE + bool "EINT7 interrupt secure" + ---help--- + EINT7 interrupt is secure. +endchoice + +choice + prompt "PDMA1 Interrupt target secure configuration" + default PDMA1_INTERRUPT_SECURE + +config PDMA1_INTERRUPT_NONSECURE + bool "PDMA1 interrupt non-secure" + ---help--- + PDMA1 interrupt is non-secure. + +config PDMA1_INTERRUPT_SECURE + bool "PDMA1 interrupt secure" + ---help--- + PDMA1 interrupt is secure. +endchoice + +choice + prompt "TRNG Interrupt target secure configuration" + default TRNG_INTERRUPT_SECURE + +config TRNG_INTERRUPT_NONSECURE + bool "TRNG interrupt non-secure" + ---help--- + TRNG interrupt is non-secure. + +config TRNG_INTERRUPT_SECURE + bool "TRNG interrupt secure" + ---help--- + TRNG interrupt is secure. +endchoice + +endmenu # Assign Interrupt to Secure or Non-secure Vector + +menu "Enable secure violation interrupts" + +config APB0IEN_SECURE_VIOLATION_INTERRUPT + bool "APB0 secure violation interrupt enable" + default n + ---help--- + APB0 secure violation interrupt enable. + +config APB1IEN_SECURE_VIOLATION_INTERRUPT + bool "APB1 secure violation interrupt enable" + default n + ---help--- + APB1 secure violation interrupt enable. + +config GPIOIEN_SECURE_VIOLATION_INTERRUPT + bool "GPIO secure violation interrupt enable" + default n + ---help--- + GPIO secure violation interrupt enable. + +config EBIIEN_SECURE_VIOLATION_INTERRUPT + bool "EBI secure violation interrupt enable" + default n + ---help--- + EBI secure violation interrupt enable. + +config USBHIEN_SECURE_VIOLATION_INTERRUPT + bool "USBH secure violation interrupt enable" + default n + ---help--- + USBH secure violation interrupt enable. + +config CRCIEN_SECURE_VIOLATION_INTERRUPT + bool "CRC secure violation interrupt enable" + default n + ---help--- + CRC secure violation interrupt enable. + +config SDH0IEN_SECURE_VIOLATION_INTERRUPT + bool "SDH0 secure violation interrupt enable" + default n + ---help--- + SDH0 secure violation interrupt enable. + +config PDMA0IEN_SECURE_VIOLATION_INTERRUPT + bool "PDMA0 secure violation interrupt enable" + default n + ---help--- + PDMA0 secure violation interrupt enable. + +config PDMA1IEN_SECURE_VIOLATION_INTERRUPT + bool "PDMA1 secure violation interrupt enable" + default n + ---help--- + PDMA1 secure violation interrupt enable. + +config SRAM0IEN_SECURE_VIOLATION_INTERRUPT + bool "SRAM0 secure violation interrupt enable" + default n + ---help--- + SRAM0 secure violation interrupt enable. + +config SRAM1IEN_SECURE_VIOLATION_INTERRUPT + bool "SRAM1 secure violation interrupt enable" + default n + ---help--- + SRAM1 secure violation interrupt enable. + +config FMCIEN_SECURE_VIOLATION_INTERRUPT + bool "FMC secure violation interrupt enable" + default n + ---help--- + FMC secure violation interrupt enable. + +config FLASHIEN_SECURE_VIOLATION_INTERRUPT + bool "FLASH secure violation interrupt enable" + default n + ---help--- + FLASH secure violation interrupt enable. + +config SCUIEN_SECURE_VIOLATION_INTERRUPT + bool "SCU secure violation interrupt enable" + default n + ---help--- + SCU secure violation interrupt enable. + +config SYSIEN_SECURE_VIOLATION_INTERRUPT + bool "SYS secure violation interrupt enable" + default n + ---help--- + SYS secure violation interrupt enable. + +config CRPTIEN_SECURE_VIOLATION_INTERRUPT + bool "CRPT secure violation interrupt enable" + default n + ---help--- + CRPT secure violation interrupt enable. + +endmenu # Enable sercure violation interrupts + +config SAU_CONTROL + bool "Secure Attribute Unit (SAU) Control" + default y + ---help--- + "Secure Attribute Unit (SAU) Control". + +config ENABLE_SAU + bool "Enable SAU" + depends on SAU_CONTROL + default y + ---help--- + "Enable SAU". + +choice + prompt "All Memory Attribute When SAU is disabled" + depends on SAU_CONTROL + default ALL_MEMORY_SECURE + +config ALL_MEMORY_NONSECURE + bool "All Memory non-secure" + ---help--- + All Memory is non-secure. + +config ALL_MEMORY_SECURE + bool "All Memory secure" + ---help--- + All Memory is secure. +endchoice + +menu "Enable and Set Secure/Non-Secure region" + +config SAU_INIT_REGION0 + bool "Setup SAU Region 0" + default y + ---help--- + Setup SAU Region 0. + +config SAU_INIT_START0 + hex "Start address of SAU region 0" + depends on SAU_INIT_REGION0 + default 0x20000000 + ---help--- + "Start address of SAU region 0." + +config SAU_INIT_END0 + hex "End address of SAU region 0" + depends on SAU_INIT_REGION0 + default 0x20008000 + ---help--- + "End address of SAU region 0." + +choice + prompt "Region 0 secure configuration" + depends on SAU_INIT_REGION0 + default REGION0_SECURE + +config REGION0_NONSECURE + bool "Region 0 non-secure" + ---help--- + Region 0 is non-secure. + +config REGION0_SECURE + bool "Region 0 secure" + ---help--- + Region 0 is secure. +endchoice + +config SAU_INIT_REGION1 + bool "Setup SAU Region 1" + default n + ---help--- + Setup SAU Region 1. + +config SAU_INIT_START1 + hex "Start address of SAU region 1" + depends on SAU_INIT_REGION1 + default 0x10040000 + ---help--- + "Start address of SAU region 1." + +config SAU_INIT_END1 + hex "End address of SAU region 1" + depends on SAU_INIT_REGION1 + default 0x1007FFFF + ---help--- + "End address of SAU region 1." + +choice + prompt "Region 1 secure configuration" + depends on SAU_INIT_REGION1 + default REGION1_NONSECURE + +config REGION1_NONSECURE + bool "Region 1 non-secure" + ---help--- + Region 1 is non-secure. + +config REGION1_SECURE + bool "Region 1 secure" + ---help--- + Region 1 is secure. +endchoice + +config SAU_INIT_REGION2 + bool "Setup SAU Region 2" + default n + ---help--- + Setup SAU Region 2. + +config SAU_INIT_START2 + hex "Start address of SAU region 2" + depends on SAU_INIT_REGION2 + default 0x2000F000 + ---help--- + "Start address of SAU region 2." + +config SAU_INIT_END2 + hex "End address of SAU region 2" + depends on SAU_INIT_REGION2 + default 0x2000FFFF + ---help--- + "End address of SAU region 2." + +choice + prompt "Region 2 secure configuration" + depends on SAU_INIT_REGION2 + default REGION2_SECURE + +config REGION2_NONSECURE + bool "Region 2 non-secure" + ---help--- + Region 2 is non-secure. + +config REGION2_SECURE + bool "Region 2 secure" + ---help--- + Region 2 is secure. +endchoice + +config SAU_INIT_REGION3 + bool "Setup SAU Region 3" + default y + ---help--- + Setup SAU Region 3. + +config SAU_INIT_START3 + hex "Start address of SAU region 3" + depends on SAU_INIT_REGION3 + default 0x0003F000 + ---help--- + "Start address of SAU region 3." + +config SAU_INIT_END3 + hex "End address of SAU region 3" + depends on SAU_INIT_REGION3 + default 0x0003F7FF + ---help--- + "End address of SAU region 3." + +choice + prompt "Region 3 secure configuration" + depends on SAU_INIT_REGION3 + default REGION3_SECURE + +config REGION3_NONSECURE + bool "Region 3 non-secure" + ---help--- + Region 3 is non-secure. + +config REGION3_SECURE + bool "Region 3 secure" + ---help--- + Region 3 is secure. +endchoice + +config SAU_INIT_REGION4 + bool "Setup SAU Region 4" + default y + ---help--- + Setup SAU Region 4. + +config SAU_INIT_START4 + hex "Start address of SAU region 4" + depends on SAU_INIT_REGION4 + default 0x10040000 + ---help--- + "Start address of SAU region 4." + +config SAU_INIT_END4 + hex "End address of SAU region 4" + depends on SAU_INIT_REGION4 + default 0x1007FFFF + ---help--- + "End address of SAU region 4." + +choice + prompt "Region 4 secure configuration" + depends on SAU_INIT_REGION4 + default REGION4_NONSECURE + +config REGION4_NONSECURE + bool "Region 4 non-secure" + ---help--- + Region 4 is non-secure. + +config REGION4_SECURE + bool "Region 4 secure" + ---help--- + Region 4 is secure. +endchoice + +config SAU_INIT_REGION5 + bool "Setup SAU Region 5" + default y + ---help--- + Setup SAU Region 5. + +config SAU_INIT_START5 + hex "Start address of SAU region 5" + depends on SAU_INIT_REGION5 + default 0x00807E00 + ---help--- + "Start address of SAU region 5." + +config SAU_INIT_END5 + hex "End address of SAU region 5" + depends on SAU_INIT_REGION5 + default 0x00807FFF + ---help--- + "End address of SAU region 5." + +choice + prompt "Region 5 secure configuration" + depends on SAU_INIT_REGION5 + default REGION5_SECURE + +config REGION5_NONSECURE + bool "Region 5 non-secure" + ---help--- + Region 5 is non-secure. + +config REGION5_SECURE + bool "Region 5 secure" + ---help--- + Region 5 is secure. +endchoice + +config SAU_INIT_REGION6 + bool "Setup SAU Region 6" + default y + ---help--- + Setup SAU Region 6. + +config SAU_INIT_START6 + hex "Start address of SAU region 6" + depends on SAU_INIT_REGION6 + default 0x30008000 + ---help--- + "Start address of SAU region 6." + +config SAU_INIT_END6 + hex "End address of SAU region 6" + depends on SAU_INIT_REGION6 + default 0x30017FFF + ---help--- + "End address of SAU region 6." + +choice + prompt "Region 6 secure configuration" + depends on SAU_INIT_REGION6 + default REGION6_NONSECURE + +config REGION6_NONSECURE + bool "Region 6 non-secure" + ---help--- + Region 6 is non-secure. + +config REGION6_SECURE + bool "Region 6 secure" + ---help--- + Region 6 is secure. +endchoice + +config SAU_INIT_REGION7 + bool "Setup SAU Region 7" + default y + ---help--- + Setup SAU Region 7. + +config SAU_INIT_START7 + hex "Start address of SAU region 7" + depends on SAU_INIT_REGION7 + default 0x50000000 + ---help--- + "Start address of SAU region 7." + +config SAU_INIT_END7 + hex "End address of SAU region 7" + depends on SAU_INIT_REGION7 + default 0x5FFFFFFF + ---help--- + "End address of SAU region 7." + +choice + prompt "Region 7 secure configuration" + depends on SAU_INIT_REGION7 + default REGION7_NONSECURE + +config REGION7_NONSECURE + bool "Region 7 non-secure" + ---help--- + Region 7 is non-secure. + +config REGION7_SECURE + bool "Region 7 secure" + ---help--- + Region 7 is secure. +endchoice + +endmenu # Enable and Set Secure/Non-Secure region + +endmenu # Secure Attribution Configuration + +#if PLATFORM_M2351_BADGE +#comment "M2351-Badge Peripheral Configuration Options" +#source arch/cortex-m23/m2351/src/m2351_badge/Kconfig +#endif # PLATFORM_M2351_BADGE + +#if PLATFORM_NUMAKER_PFM_M2351 +#comment "NuMaker-PFM-M2351 Peripheral Configuration Options" +#source arch/cortex-m23/m2351/src/numaker_pfm_m2351/Kconfig +#endif # PLATFORM_NUMAKER_PFM_M2351 diff --git a/arch/riscv32/fe310/src/Makefile b/arch/riscv32/fe310/src/Makefile new file mode 100644 index 00000000..cf4c8331 --- /dev/null +++ b/arch/riscv32/fe310/src/Makefile @@ -0,0 +1,106 @@ +############################################################################ +# arch/cortex-m23/m2351/src/StdDriver/Makefile +# +# Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved. +# Author: Taras Drozdovskyi t.drozdovsky@samsung.com +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include $(TOPDIR)/.config + +CFLAGS += -I../../CMSIS/Include +CFLAGS += -I../../StdDriver/inc +CFLAGS += -I../../Device/Nuvoton/M2351/Include +CFLAGS += -I$(TOPDIR)/include/mtower +CFLAGS += -I$(TOPDIR)/arch/$(CONFIG_ARCH)/$(CONFIG_ARCH_FAMILY)/src/$(CONFIG_PLATFORM) + +ifeq ($(WORLD), secure) +CFLAGS += -mcmse +endif + +CFLAGS += -Wno-unused-parameter -Wno-undef -Wno-maybe-uninitialized +CFLAGS += -Wno-unused-variable -Wno-pointer-compare + +#SRCS += acmp.c +#SRCS += bpwm.c +#SRCS += can.c +#SRCS += crc.c +#SRCS += crypto.c +#SRCS += dac.c +#SRCS += eadc.c +#SRCS += ebi.c +#SRCS += ecap.c +#SRCS += epwm.c +SRCS += fmc.c +SRCS += gpio.c +#SRCS += i2c.c +#SRCS += i2s.c +#SRCS += pdma.c +#SRCS += qei.c +#SRCS += qspi.c +SRCS += retarget.c +#SRCS += rtc.c +#SRCS += sc.c +#SRCS += scuart.c +#SRCS += sdh.c +#SRCS += spi.c +SRCS += sys.c +#SRCS += timer.c +#SRCS += timer_pwm.c +SRCS += uart.c +#SRCS += usbd.c +#SRCS += usci_i2c.c +#SRCS += usci_spi.c +#SRCS += usci_uart.c +#SRCS += wdt.c +#SRCS += wwdt.c + +ifeq ($(WORLD), secure) +SRCS += clk.c +endif + +ifneq ($(WORLD), secure) +CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_NONSECURE_DEBUG_UART)) +CFLAGS += -DDEBUG_OUT_PREFIX=$(CONFIG_NONSECURE_FONT_COLOR) +OBJDIR = $(TOPDIR)/build/nonsecure$(subst $(TOPDIR),,$(shell pwd)) +endif + +ifeq ($(WORLD), secure) +CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_SECURE_DEBUG_UART)) +CFLAGS += -DDEBUG_OUT_PREFIX=$(CONFIG_SECURE_FONT_COLOR) +OBJDIR = $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd)) +endif + +OBJS = $(addprefix $(OBJDIR)/, $(SRCS:.c=.o)) + +current_dir = $(subst $(TOPDIR),,$(shell pwd)) + +$(OBJDIR)/%.o : %.c + $(Q) mkdir -p $(OBJDIR)/$(dir $<) + @echo "CC: $<" + $(Q) $(CC) $(CFLAGS) -c -o $@ $^ + +libm2351_StdDriver_s.a: $(OBJS) + $(Q) $(AR) $(OBJDIR)/$@ $(OBJS) + $(Q) cp $(OBJDIR)/$@ $(TOPDIR)/lib/$@ + +libm2351_StdDriver_ns.a: $(OBJS) + $(Q) $(AR) $(OBJDIR)/$@ $(OBJS) + $(Q) cp $(OBJDIR)/$@ $(TOPDIR)/lib/$@ + +clean: + rm -f libm2351_StdDriver.a + diff --git a/arch/riscv32/fe310/src/NuBL2/.gitignore b/arch/riscv32/fe310/src/NuBL2/.gitignore new file mode 100644 index 00000000..c3edecc2 --- /dev/null +++ b/arch/riscv32/fe310/src/NuBL2/.gitignore @@ -0,0 +1,4 @@ +FwInfo.c +NuBL2.h +VerifyNuBL3x.c +main.c diff --git a/arch/riscv32/fe310/src/NuBL2/KeyInfo/NuBL3xKeyStorage.S b/arch/riscv32/fe310/src/NuBL2/KeyInfo/NuBL3xKeyStorage.S new file mode 100644 index 00000000..c9b96b2e --- /dev/null +++ b/arch/riscv32/fe310/src/NuBL2/KeyInfo/NuBL3xKeyStorage.S @@ -0,0 +1,33 @@ + .syntax unified + .arch armv8 - m.base + + .section .rodata + .align 3 + + .global g_NuBL32KeyStart + .global g_NuBL32KeyEnd + .global g_NuBL32KeyHashStart + .global g_NuBL32KeyHashEnd + + .global g_NuBL33KeyStart + .global g_NuBL33KeyEnd + .global g_NuBL33KeyHashStart + .global g_NuBL33KeyHashEnd + +g_NuBL32KeyStart: + .incbin "KeyInfo/NuBL32PubKeyEncrypted.bin" +g_NuBL32KeyEnd: + +g_NuBL32KeyHashStart: + .incbin "KeyInfo/NuBL32PubKeyEncryptedHash.bin" +g_NuBL32KeyHashEnd: + + +g_NuBL33KeyStart: + .incbin "KeyInfo/NuBL33PubKeyEncrypted.bin" +g_NuBL33KeyEnd: + +g_NuBL33KeyHashStart: + .incbin "KeyInfo/NuBL33PubKeyEncryptedHash.bin" +g_NuBL33KeyHashEnd: + diff --git a/arch/riscv32/fe310/src/NuBL2/Make.defs b/arch/riscv32/fe310/src/NuBL2/Make.defs new file mode 100644 index 00000000..77d2679c --- /dev/null +++ b/arch/riscv32/fe310/src/NuBL2/Make.defs @@ -0,0 +1,42 @@ +############################################################################ +# arch/cortex-m23/m2351/src/NuBL2/Make.defs +# +# Copyright (c) 2018-2019 Samsung Electronics Co., Ltd. All Rights Reserved. +# Author: Taras Drozdovskyi t.drozdovsky@samsung.com +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include $(TOPDIR)/.config + +HEAD_ASRC = + +# Common m2351 files + +CMN_ASRCS = + +CMN_CSRCS = + +# Required CHIP files + +CHIP_ASRCS_S = ../Device/Nuvoton/M2351/Source/GCC/startup_M2351.S \ + KeyInfo/NuBL3xKeyStorage.S + +CHIP_CSRCS_S = ../Device/Nuvoton/M2351/Source/system_M2351.c \ + ../Device/Nuvoton/M2351/Source/GCC/_syscalls.c \ + main.c \ + VerifyNuBL3x.c \ + FwInfo.c + diff --git a/arch/riscv32/fe310/src/NuBL2/Makefile b/arch/riscv32/fe310/src/NuBL2/Makefile new file mode 100644 index 00000000..e0989154 --- /dev/null +++ b/arch/riscv32/fe310/src/NuBL2/Makefile @@ -0,0 +1,77 @@ +############################################################################ +# arch/cortex-m23/m2351/src/NuBL2/Makefile +# +# Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved. +# Author: Taras Drozdovskyi t.drozdovsky@samsung.com +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include $(TOPDIR)/.config +-include Make.defs + +CFLAGS += -I./ +CFLAGS += -I$(TOPDIR)/arch/$(CONFIG_ARCH)/$(CONFIG_ARCH_FAMILY)/src/$(CONFIG_PLATFORM) +CFLAGS += -I$(TOPDIR)/include/mtower +CFLAGS += -I../CMSIS/Include +CFLAGS += -I../StdDriver/inc +CFLAGS += -I../Device/Nuvoton/M2351/Include + +CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_SECURE_DEBUG_UART)) + +OBJDIR = $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd)) + +NuBL2 = NuBL2$(EXEEXT) + +ASRCS_S = $(CHIP_ASRCS_S) $(CMN_ASRCS) +AOBJS_S = $(addprefix $(OBJDIR)/, $(ASRCS_S:.S=$(OBJEXT))) + +CSRCS_S = $(CHIP_CSRCS_S) $(CMN_CSRCS) +COBJS_S = $(addprefix $(OBJDIR)/, $(CSRCS_S:.c=$(OBJEXT))) + +OBJS_S = $(AOBJS_S) $(COBJS_S) + +LIBPATHS = -L. -L"$(TOPDIR)/lib" -L"../StdDriver/src" + +LIBS = -lm -lc -lnosys -lm2351_StdDriver_s -lmkrom + +$(AOBJS_S): $(OBJDIR)/%$(OBJEXT): %.S + $(Q) mkdir -p $(OBJDIR)/$(dir $<) + @echo "AS: $<" + $(Q) $(CC) -c $(AFLAGS) -mcmse $< -o $@ + +$(COBJS_S): $(OBJDIR)/%$(OBJEXT): %.c + $(Q) mkdir -p $(OBJDIR)/$(dir $<) + @echo "CC: $<" + $(Q) $(CC) -c $(CFLAGS) -mcmse $< -o $@ + +Ecdsa_key: + $(Q) $(TOPDIR)/tools/ecdsa_keygen KeyInfo/ + +NuBL2$(EXEEXT): Ecdsa_key $(OBJS_S) + $(Q) $(MAKE) -C ../StdDriver/src/ TOPDIR="$(TOPDIR)" WORLD=secure libm2351_StdDriver_s.a +# $(Q) $(MAKE) -C $(TOPDIR)/crypto/ TOPDIR="$(TOPDIR)" WORLD=secure libcrypt_s.a + + @echo "CC: NuBL2$(EXEEXT)" + $(Q) $(CC) $(CFLAGS) -mcmse -Wl,--section-start=.text=0x00000000 -Tsecure.ld $(OBJS_S) $(LIBPATHS) $(LIBS) -o $(OBJDIR)/$(NuBL2) +# -$(Q) $(LD) --section-start=.gnu.sgstubs=0x3f000 --out-implib=libnsc$(LIBEXT) --cmse-implib $(OBJS_S) $(LIBPATHS) $(LIBS) +# $(Q) cp -f libnsc$(LIBEXT) $(TOPDIR)/lib/ + $(Q) $(OBJCOPY) -O binary $(OBJDIR)/$(NuBL2) $(OBJDIR)/bl2.bin + +clean: + $(Q) rm -f KeyInfo/*.bin + +distclean: clean + diff --git a/arch/riscv32/fe310/src/NuBL2/secure.ld b/arch/riscv32/fe310/src/NuBL2/secure.ld new file mode 100644 index 00000000..63648fca --- /dev/null +++ b/arch/riscv32/fe310/src/NuBL2/secure.ld @@ -0,0 +1,231 @@ +/* Linker script to configure memory regions. */ +MEMORY +{ + /* FLASH (rx) : ORIGIN = 0x00010000, LENGTH = 0x80000 */ /* 512k */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x18000 /* 160k */ + FLASH_NCS (rx) : ORIGIN = 0x0003F000, LENGTH = 0x00000400 +} + +/* Library configurations */ +GROUP(libgcc.a libc.a libm.a libnosys.a) + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + __Vectors_End = .; + __Vectors_Size = __Vectors_End - __Vectors; + __end__ = .; + + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* *(.rodata*) */ + + KEEP(*(.eh_frame*)) + } > FLASH + + .rodata : ALIGN(4) + { + __rodata_start = .; + *(.rodata .rodata.*) + /* + * 8 to avoid unwanted padding between __start_ta_head_section + * and the first structure in ta_head_section, in 64-bit + * builds + */ + . = ALIGN(4); + __start_ta_head_section = . ; + KEEP(*(ta_head_section)) + __stop_ta_head_section = . ; + . = ALIGN(4); + __start_user_ta_head_section = . ; + KEEP(*(user_ta_head_section)) + __stop_user_ta_head_section = . ; + . = ALIGN(4); + __rodata_end = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + .gnu.sgstubs : ALIGN(2048) + { + __start_NSC = .; + . = ALIGN(4); + _ssgstubs = .; + } > FLASH + . = ALIGN(2048); + __end_NSC = .; + __etext = .; + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + /* All data end */ + __data_end__ = .; + + } > RAM + + .bss : + { + . = ALIGN(4); + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + } > RAM + + .heap (COPY): + { + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > RAM + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + /* + __StackTop = ORIGIN(RAM) + LENGTH(RAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + */ + + __StackTop = __HeapLimit + SIZEOF(.stack_dummy); + __StackLimit = __HeapLimit; + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/arch/riscv32/fe310/src/StdDriver/.gitignore b/arch/riscv32/fe310/src/StdDriver/.gitignore new file mode 100644 index 00000000..87256bc2 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/.gitignore @@ -0,0 +1,4 @@ +*.o +!libmkrom.a +*.lib + diff --git a/arch/riscv32/fe310/src/StdDriver/inc/acmp.h b/arch/riscv32/fe310/src/StdDriver/inc/acmp.h new file mode 100644 index 00000000..d35857e4 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/acmp.h @@ -0,0 +1,388 @@ +/**************************************************************************//** + * @file ACMP.h + * @version V3.00 + * @brief M2351 Series ACMP Driver Header File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __ACMP_H__ +#define __ACMP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants + @{ +*/ + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_CTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */ +#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */ +#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */ +#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */ +#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */ +#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */ +#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */ +#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */ +#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */ +#define ACMP_CTL_HYSTERESIS_30MV (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */ +#define ACMP_CTL_HYSTERESIS_20MV (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */ +#define ACMP_CTL_HYSTERESIS_10MV (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */ +#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ACMP_VREF constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */ +#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */ + + +/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Macros and functions */ +/*---------------------------------------------------------------------------------------------------------*/ + + +/** + * @brief This macro is used to enable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function. + */ +#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to disable output inverse function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function. + */ +#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk) + +/** + * @brief This macro is used to select ACMP negative input source + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Src is comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @return None + * @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input. + */ +#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to enable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + */ +#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV) + +/** + * @brief This macro is used to disable hysteresis function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function. + */ +#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk) + +/** + * @brief This macro is used to select hysteresis level + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * @return None + */ +#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel)) + +/** + * @brief This macro is used to enable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function. + * If wake-up function is enabled, the wake-up interrupt will be enabled as well. + */ +#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to disable interrupt + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function. + */ +#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk) + +/** + * @brief This macro is used to enable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator. + */ +#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to disable ACMP + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk) + +/** + * @brief This macro is used to get ACMP output value + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP output value + * @details This macro will return the ACMP output value. + */ +#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to get ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return ACMP interrupt occurred (1) or not (0) + * @details This macro will return the ACMP interrupt flag. + */ +#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0) + +/** + * @brief This macro is used to clear ACMP interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to clear ACMP wake-up interrupt flag + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag. + */ +#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum)))) + +/** + * @brief This macro is used to enable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function. + */ +#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to disable ACMP wake-up function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function. + */ +#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk) + +/** + * @brief This macro is used to select ACMP positive input pin + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Pin Comparator positive pin selection. Including: + * - \ref ACMP_CTL_POSSEL_P0 + * - \ref ACMP_CTL_POSSEL_P1 + * - \ref ACMP_CTL_POSSEL_P2 + * - \ref ACMP_CTL_POSSEL_P3 + * @return None + * @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin. + */ +#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin)) + +/** + * @brief This macro is used to enable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function. + */ +#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to disable ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function. + */ +#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk) + +/** + * @brief This macro is used to set ACMP filter function + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cnt is comparator filter count setting. + * - \ref ACMP_CTL_FILTSEL_OFF + * - \ref ACMP_CTL_FILTSEL_1PCLK + * - \ref ACMP_CTL_FILTSEL_2PCLK + * - \ref ACMP_CTL_FILTSEL_4PCLK + * - \ref ACMP_CTL_FILTSEL_8PCLK + * - \ref ACMP_CTL_FILTSEL_16PCLK + * - \ref ACMP_CTL_FILTSEL_32PCLK + * - \ref ACMP_CTL_FILTSEL_64PCLK + * @return None + * @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]). + */ +#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt)) + +/** + * @brief This macro is used to select comparator reference voltage + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32Level The comparator reference voltage setting. + * The formula is: + * comparator reference voltage = CRV source voltage x (1/6 + u32Level/24) + * The range of u32Level is 0 ~ 15. + * @return None + * @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]). + */ +#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src)) + +/** + * @brief This macro is used to select ACMP interrupt condition + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @param[in] u32Cond Comparator interrupt condition selection. Including: + * - \ref ACMP_CTL_INTPOL_RF + * - \ref ACMP_CTL_INTPOL_R + * - \ref ACMP_CTL_INTPOL_F + * @return None + * @details The ACMP output interrupt condition can be rising edge, falling edge or any edge. + */ +#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond)) + +/** + * @brief This macro is used to enable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode. + * When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch + * block; when ACMP0/1_WLAT pin is at low level, the output of window latch block, + * WLATOUT, is frozen. + */ +#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to disable ACMP window latch mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode. + */ +#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk) + +/** + * @brief This macro is used to enable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode. + * When window compare mode is enabled, user can connect the specific analog voltage + * source to either the positive inputs of both comparators or the negative inputs of + * both comparators. The upper bound and lower bound of the designated range are + * determined by the voltages applied to the other inputs of both comparators. If the + * output of a comparator is low and the other comparator outputs high, which means two + * comparators implies the upper and lower bound. User can directly monitor a specific + * analog voltage source via ACMPWO (ACMP_STATUS[16]). + */ +#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk) + +/** + * @brief This macro is used to disable ACMP window compare mode + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum The ACMP number + * @return None + * @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode. + */ +#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk) + + + + +/* Function prototype declaration */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel); +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum); + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __ACMP_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/bpwm.h b/arch/riscv32/fe310/src/StdDriver/inc/bpwm.h new file mode 100644 index 00000000..ab4ac72f --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/bpwm.h @@ -0,0 +1,363 @@ +/**************************************************************************//** + * @file bpwm.h + * @version V1.00 + * @brief M2351 series BPWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __BPWM_H__ +#define __BPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + +/** @addtogroup BPWM_EXPORTED_CONSTANTS BPWM Exported Constants + @{ +*/ +#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */ +#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */ +#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */ +#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */ +#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */ +#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */ +#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */ +#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */ +#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */ +#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */ +#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define BPWM_SSCTL_SSRC_PWM0 (0UL<SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk) + +/** + * @brief This macro enable BPWM counter synchronous start counting function. + * @param[in] bpwm The pointer of the specified BPWM module + * @return None + * @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * \hideinitializer + */ +#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * \hideinitializer + */ +#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) ((bpwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \ + { \ + (bpwm)->MSKEN = (u32ChannelMask); \ + (bpwm)->MSK = (u32LevelMask); \ + } + +/** + * @brief This macro set the prescaler of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF + * @return None + * \hideinitializer + */ +#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler)) + +/** + * @brief This macro set the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * \hideinitializer + */ +#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) + +/** + * @brief This macro get the duty of the selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @note This new setting will take effect on next BPWM period + * @note BPWM counter will stop if period length set to 0 + * \hideinitializer + */ +#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR)) + +/** + * @brief This macro get the period of all channels + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * \hideinitializer + */ +#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD) + +/** + * @brief This macro set the BPWM aligned type + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @param[in] u32AlignedType BPWM aligned type, valid values are: + * - \ref BPWM_EDGE_ALIGNED + * - \ref BPWM_CENTER_ALIGNED + * @return None + * @note All channels share channel 0's setting. + * \hideinitializer + */ +#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType)) + +/** + * @brief Clear counter of channel 0 + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This macro is used to clear counter of channel 0 + * \hideinitializer + */ +#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref BPWM_OUTPUT_NOTHING + * - \ref BPWM_OUTPUT_LOW + * - \ref BPWM_OUTPUT_HIGH + * - \ref BPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * \hideinitializer + */ +#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define BPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask); +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum); + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __BPWM_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/can.h b/arch/riscv32/fe310/src/StdDriver/inc/can.h new file mode 100644 index 00000000..5a6cfc35 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/can.h @@ -0,0 +1,196 @@ +/**************************************************************************//** + * @file can.h + * @version V1.00 + * @brief M2351 Series CAN Driver Header File + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __CAN_H__ +#define __CAN_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CAN Test Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_NORMAL_MODE 0U /*!< CAN select normal mode */ +#define CAN_BASIC_MODE 1U /*!< CAN select basic mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message ID Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_STD_ID 0UL /*!< CAN select standard ID */ +#define CAN_EXT_ID 1UL /*!< CAN select extended ID */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Message Frame Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */ +#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */ + +/*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */ + + +/** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs + @{ +*/ +/** + * @details CAN message structure + */ +#pragma pack(push) +#pragma pack(1) +typedef struct +{ + uint32_t IdType; /*!< ID type */ + uint32_t FrameType; /*!< Frame type */ + uint32_t Id; /*!< Message ID */ + uint8_t DLC; /*!< Data length */ + uint8_t Data[8]; /*!< Data */ +} STR_CANMSG_T; +#pragma pack(pop) + +/** + * @details CAN mask message structure + */ +#pragma pack(push) +#pragma pack(1) +typedef struct +{ + uint8_t u8Xtd; /*!< Extended ID */ + uint8_t u8Dir; /*!< Direction */ + uint32_t u32Id; /*!< Message ID */ + uint8_t u8IdType; /*!< ID type*/ +} STR_CANMASK_T; +#pragma pack(pop) + +/*@}*/ /* end of group CAN_EXPORTED_STRUCTS */ + +/** @cond HIDDEN_SYMBOLS */ +#define MSG(id) (id) +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** + * @brief Get interrupt status. + * + * @param[in] can The base address of can module. + * + * @return CAN module status register value. + * + * @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]), + * EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]). + */ +#define CAN_GET_INT_STATUS(can) ((can)->STATUS) + +/** + * @brief Get specified interrupt pending status. + * + * @param[in] can The base address of can module. + * + * @return The source of the interrupt. + * + * @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt + * with the highest priority, disregarding their chronological order. + */ +#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR) + +/** + * @brief Disable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details The macro is used to disable wake-up function. + */ +#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0) + +/** + * @brief Enable wake-up function. + * + * @param[in] can The base address of can module. + * + * @return None + * + * @details User can wake-up system when there is a falling edge in the CAN_Rx pin. + */ +#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk) + +/** + * @brief Get specified Message Object new data into bit value. + * + * @param[in] can The base address of can module. + * @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31. + * + * @return Specified Message Object new data into bit value. + * + * @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers + * or by the Message Handler after reception of a Data Frame or after a successful transmission. + */ +#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16))) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define CAN functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate); +void CAN_Close(CAN_T *tCAN); +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode); +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum); +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask); +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask); +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID); +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask); +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg); +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum); +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask); +void CAN_LeaveInitMode(CAN_T *tCAN); +void CAN_WaitMsg(CAN_T *tCAN); +uint32_t CAN_GetCANBitRate(CAN_T *tCAN); +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask); +void CAN_LeaveTestMode(CAN_T *tCAN); +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj); +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg); +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast); +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast); +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg); + + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/clk.h b/arch/riscv32/fe310/src/StdDriver/inc/clk.h new file mode 100644 index 00000000..7bce8dcb --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/clk.h @@ -0,0 +1,860 @@ +/**************************************************************************//** + * @file clk.h + * @version V3.0 + * @brief M2351 series Clock Controller (CLK) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __CLK_H__ +#define __CLK_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + +/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants + @{ +*/ + + +#define FREQ_2MHZ 2000000UL +#define FREQ_8MHZ 8000000UL +#define FREQ_24MHZ 24000000UL +#define FREQ_48MHZ 48000000UL +#define FREQ_64MHZ 64000000UL +#define FREQ_96MHZ 96000000UL +#define FREQ_144MHZ 144000000UL +#define FREQ_200MHZ 200000000UL + + + +/*---------------------------------------------------------------------------------------------------------*/ +/* CLKSEL0 constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<>30) & 0x3UL) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL(x) (((x) >>28) & 0x3UL) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7UL) /*!< Calculate CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1fUL) /*!< Calculate CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV(x) (((x) >>18) & 0x3UL) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xffUL) /*!< Calculate CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1fUL) /*!< Calculate CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1fUL) /*!< Calculate APBCLK offset on MODULE index */ +#define MODULE_NoMsk 0x0UL /*!< Not mask on MODULE index */ +#define NA MODULE_NoMsk /*!< Not Available */ + +#define MODULE_APBCLK_ENC(x) (((x) & 0x03UL) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */ +#define MODULE_CLKSEL_ENC(x) (((x) & 0x03UL) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */ +#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07UL) << 25) /*!< CLKSEL mask offset on MODULE index */ +#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1fUL) << 20) /*!< CLKSEL position offset on MODULE index */ +#define MODULE_CLKDIV_ENC(x) (((x) & 0x03UL) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */ +#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xffUL) << 10) /*!< CLKDIV mask offset on MODULE index */ +#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1fUL) << 5) /*!< CLKDIV position offset on MODULE index */ +#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1fUL) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */ + + +/* AHBCLK */ +#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_PDMA1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */ + +#define ISP_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_ISPCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */ + +#define EBI_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_EBICKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */ + +#define SDH0_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_SDH0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(24UL))/*!< SDH0 Module */ + +#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ + +#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ + +#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_FMCIDLE_Pos)|\ + MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */ + +#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */ + +/* APBCLK0 */ +#define WDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< WDT Module */ + +#define WWDT_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_WDTCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */ + +#define RTC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_RTCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */ + +#define TMR0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR0 Module */ + +#define TMR1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR1 Module */ + +#define TMR2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR2 Module */ + +#define TMR3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_TMR3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 7UL)|MODULE_CLKSEL_Pos_ENC(20UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< TMR3 Module */ + +#define CLKO_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CLKOCKEN_Pos) |\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC(3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< CLKO Module */ + +#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_ACMP01CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */ + +#define I2C0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */ + +#define I2C1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */ + +#define I2C2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2C2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */ + +#define QSPI0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_QSPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< QSPI0 Module */ + +#define SPI0_MODULE (MODULE_APBCLK_ENC(1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI0CKEN_Pos) |\ + MODULE_CLKSEL_ENC(2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI0 Module */ + +#define SPI1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 6UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI1 Module */ + +#define SPI2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_SPI2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(10UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< SPI2 Module */ + +#define UART0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART0 Module */ + +#define UART1_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART1 Module */ + +#define UART2_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART2CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(24UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< UART2 Module */ + +#define UART3_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART3CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(26UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< UART3 Module */ + +#define UART4_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART4CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(28UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< UART4 Module */ + +#define UART5_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_UART5CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ + MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */ + +#define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */ + +#define OTG_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_OTGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< OTG Module */ + +#define USBD_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_USBDCKEN_Pos)|\ + MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(4UL)) /*!< USBD Module */ + +#define EADC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_EADCCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC( NA)|MODULE_CLKSEL_Pos_ENC( NA)|\ + MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< EADC Module */ + +#define I2S0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_I2S0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(16UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC( NA)|MODULE_CLKDIV_Pos_ENC( NA)) /*!< I2S0 Module */ + +/* APBCLK1 */ +#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC0CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 0UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 0UL)) /*!< SC0 Module */ + +#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC1CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 2UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC( 8UL)) /*!< SC1 Module */ + +#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SC2CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC( 4UL)|\ + MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0xFFUL)|MODULE_CLKDIV_Pos_ENC(16UL)) /*!< SC2 Module */ + +#define SPI3_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI3CKEN_Pos) |\ + MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ + +#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ + +#define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */ + +#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_DACCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */ + +#define EPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM0 Module */ + +#define EPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_EPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EPWM1 Module */ + +#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */ + +#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_BPWM1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */ + +#define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */ + +#define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_QEI1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */ + +#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_TRNGCKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */ + +#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP0CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */ + +#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_ECAP1CKEN_Pos)|\ + MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ + MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* PDMSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */ +#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */ +#define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */ +#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */ +#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WKTMRIS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 LIRC clocks (12.8 ms) */ +#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 LIRC clocks (25.6 ms) */ +#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 LIRC clocks (51.2 ms) */ +#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 LIRC clocks (102.4ms) */ +#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 LIRC clocks (409.6ms) */ +#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 LIRC clocks (819.2ms) */ +#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 LIRC clocks (1638.4ms) */ +#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 LIRC clocks (6553.6ms) */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SWKDBCLKSEL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */ +#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode */ +#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode */ +#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode */ +#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */ +#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */ +#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */ +#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */ +#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */ + +#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode \hideinitializer */ +#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode \hideinitializer */ +#define CLK_DISABLE_RTCWK(void) (CLK->PMUCTL &= ~CLK_PMUCTL_RTCWKEN_Msk) /*!< Disable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ +#define CLK_ENABLE_RTCWK(void) (CLK->PMUCTL |= CLK_PMUCTL_RTCWKEN_Msk) /*!< Enable RTC Wake-up at Standby or Deep Power-down mode \hideinitializer */ + + +/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */ + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + + +/** + * @brief Set Wake-up Timer Time-out Interval + * + * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be + * - \ref CLK_PMUCTL_WKTMRIS_128 + * - \ref CLK_PMUCTL_WKTMRIS_256 + * - \ref CLK_PMUCTL_WKTMRIS_512 + * - \ref CLK_PMUCTL_WKTMRIS_1024 + * - \ref CLK_PMUCTL_WKTMRIS_4096 + * - \ref CLK_PMUCTL_WKTMRIS_8192 + * - \ref CLK_PMUCTL_WKTMRIS_16384 + * - \ref CLK_PMUCTL_WKTMRIS_65536 + * + * @return None + * + * @details This function set Wake-up Timer Time-out Interval. + * + * + */ +#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKTMRIS_Msk)) | (u32Interval)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256 + * - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256 + * + * @return None + * + * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up. + * + * + */ +#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us); +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us); + + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex: + * 64MHz => 262143us, 48MHz => 349525us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickDelay(uint32_t us) +{ + SysTick->LOAD = us * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL) + { + } + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) + +__STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us); + +/** + * @brief This function execute delay function. + * @param[in] us Delay time. The Max value is (2^24-1) / CPU Clock(MHz). Ex: + * 64MHz => 262143us, 48MHz => 349525us ... + * @return None + * @details Use the SysTick to generate the delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us) +{ + SysTick_NS->LOAD = us * CyclesPerUs; + SysTick_NS->VAL = (0x00UL); + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick_NS->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick_NS->CTRL = 0UL; +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) */ + + + + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) +{ + uint32_t u32Delay; + + /* It should <= 65536us for each delay loop */ + u32Delay = 65536UL; + + do + { + if(us > u32Delay) + { + us -= u32Delay; + } + else + { + u32Delay = us; + us = 0UL; + } + + SysTick->LOAD = u32Delay * CyclesPerUs; + SysTick->VAL = (0x0UL); + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick->CTRL = 0UL; + + } + while(us > 0UL); + +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) + +__STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us); + +/** + * @brief This function execute long delay function. + * @param[in] us Delay time. + * @return None + * @details Use the SysTick to generate the long delay time and the UNIT is in us. + * The SysTick clock source is from HCLK, i.e the same as system core clock. + * User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function. + */ +__STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us) +{ + uint32_t u32Delay; + + /* It should <= 65536us for each delay loop */ + u32Delay = 65536UL; + + do + { + if(us > u32Delay) + { + us -= u32Delay; + } + else + { + u32Delay = us; + us = 0UL; + } + + SysTick_NS->LOAD = u32Delay * CyclesPerUs; + SysTick_NS->VAL = (0x0UL); + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + + /* Waiting for down-count to zero */ + while((SysTick_NS->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0UL); + + /* Disable SysTick counter */ + SysTick_NS->CTRL = 0UL; + + } + while(us > 0UL); + +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3L) */ + + +void CLK_DisableCKO(void); +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En); +void CLK_PowerDown(void); +void CLK_Idle(void); +uint32_t CLK_GetHXTFreq(void); +uint32_t CLK_GetLXTFreq(void); +uint32_t CLK_GetHCLKFreq(void); +uint32_t CLK_GetPCLK0Freq(void); +uint32_t CLK_GetPCLK1Freq(void); +uint32_t CLK_GetCPUFreq(void); +uint32_t CLK_SetCoreClock(uint32_t u32Hclk); +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv); +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc); +void CLK_EnableXtalRC(uint32_t u32ClkMask); +void CLK_DisableXtalRC(uint32_t u32ClkMask); +void CLK_EnableModuleClock(uint32_t u32ModuleIdx); +void CLK_DisableModuleClock(uint32_t u32ModuleIdx); +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq); +void CLK_DisablePLL(void); +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask); +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count); +void CLK_DisableSysTick(void); +void CLK_SetPowerDownMode(uint32_t u32PDMode); +void CLK_EnableDPDWKPin(uint32_t u32TriggerType); +uint32_t CLK_GetPMUWKSrc(void); +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn); +uint32_t CLK_GetPLLClockFreq(void); +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx); +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx); + + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + + +#endif /* __CLK_H__ */ + + + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/crc.h b/arch/riscv32/fe310/src/StdDriver/inc/crc.h new file mode 100644 index 00000000..3f475ee2 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/crc.h @@ -0,0 +1,116 @@ +/**************************************************************************//** + * @file crc.h + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __CRC_H__ +#define __CRC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* CRC Polynomial Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define CRC_CCITT (0UL << CRC_CTL_CRCMODE_Pos) /*!SEED = (u32Seed); (crc)->CTL |= CRC_CTL_CHKSINIT_Msk; }while(0) + +/** + * @brief Get CRC Seed Value + * + * @param[in] crc The pointer of CRC module. + * + * @return CRC seed value + * + * @details This macro gets the current CRC seed value. + * \hideinitializer + */ +#define CRC_GET_SEED(crc) ((crc)->SEED) + +/** + * @brief CRC Write Data + * + * @param[in] crc The pointer of CRC module. + * @param[in] u32Data Write data + * + * @return None + * + * @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation. + * \hideinitializer + */ +#define CRC_WRITE_DATA(crc, u32Data) ((crc)->DAT = (u32Data)) + + +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen); +uint32_t CRC_GetChecksum(void); + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRC_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/crypto.h b/arch/riscv32/fe310/src/StdDriver/inc/crypto.h new file mode 100644 index 00000000..13ff8b59 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/crypto.h @@ -0,0 +1,393 @@ +/**************************************************************************//** + * @file crypto.h + * @version V1.10 + * @brief Cryptographic Accelerator driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __CRYPTO_H__ +#define __CRYPTO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants + @{ +*/ + +#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */ +#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */ + +#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */ +#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */ + +#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */ +#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */ +#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */ + +#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */ +#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */ +#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */ +#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */ +#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */ +#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */ +#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */ +#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */ + +#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */ +#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */ +#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */ +#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */ + +#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */ +#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */ +#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */ +#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */ +#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */ +#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */ +#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */ +#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */ +#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */ +#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */ + +#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */ +#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */ +#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */ +#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */ +#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */ +#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */ +#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */ +#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */ + +#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */ +#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */ +#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */ +#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */ +#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */ + +#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */ +#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */ +#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */ +#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */ + +#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */ +#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */ +#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */ + + + +typedef enum +{ + CURVE_P_192, + CURVE_P_224, + CURVE_P_256, + CURVE_P_384, + CURVE_P_521, + CURVE_K_163, + CURVE_K_233, + CURVE_K_283, + CURVE_K_409, + CURVE_K_571, + CURVE_B_163, + CURVE_B_233, + CURVE_B_283, + CURVE_B_409, + CURVE_B_571 +} +E_ECC_CURVE; + + + +typedef struct e_curve_t +{ + E_ECC_CURVE curve_id; + int32_t Echar; + char Ea[144]; + char Eb[144]; + char Px[144]; + char Py[144]; + int32_t Epl; + char Pp[176]; + int32_t Eol; + char Eorder[176]; + int32_t key_len; + int32_t irreducible_k1; + int32_t irreducible_k2; + int32_t irreducible_k3; + int32_t GF; +} ECC_CURVE; + + + +/*@}*/ /* end of group CRYPTO_EXPORTED_CONSTANTS */ + + +/** @addtogroup CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros + @{ +*/ + +/*----------------------------------------------------------------------------------------------*/ +/* Macros */ +/*----------------------------------------------------------------------------------------------*/ + +/** + * @brief This macro enables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro disables PRNG interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk) + +/** + * @brief This macro gets PRNG interrupt flag. + * @param crpt Specified crypto module + * @return PRNG interrupt flag. + * \hideinitializer + */ +#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro clears PRNG interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk) + +/** + * @brief This macro enables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro disables AES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk)) + +/** + * @brief This macro gets AES interrupt flag. + * @param crpt Specified crypto module + * @return AES interrupt flag. + * \hideinitializer + */ +#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro clears AES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk)) + +/** + * @brief This macro enables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables AES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro disables TDES interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk)) + +/** + * @brief This macro gets TDES interrupt flag. + * @param crpt Specified crypto module + * @return TDES interrupt flag. + * \hideinitializer + */ +#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro clears TDES interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk)) + +/** + * @brief This macro enables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro disables TDES key protection. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk) + +/** + * @brief This macro enables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro disables SHA interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk)) + +/** + * @brief This macro gets SHA interrupt flag. + * @param crpt Specified crypto module + * @return SHA interrupt flag. + * \hideinitializer + */ +#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro clears SHA interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk)) + +/** + * @brief This macro enables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro disables ECC interrupt. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk)) + +/** + * @brief This macro gets ECC interrupt flag. + * @param crpt Specified crypto module + * @return ECC interrupt flag. + * \hideinitializer + */ +#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + +/** + * @brief This macro clears ECC interrupt flag. + * @param crpt Specified crypto module + * @return None + * \hideinitializer + */ +#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk)) + + +/*@}*/ /* end of group CRYPTO_EXPORTED_MACROS */ + + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed); +void PRNG_Start(CRPT_T *crpt); +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]); +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType); +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize); +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]); +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType); +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode); +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]); +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL); +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt); +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len); +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode); +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt); +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]); +void ECC_DriverISR(CRPT_T *crpt); +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]); +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]); +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]); +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S); +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S); + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __CRYPTO_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/inc/dac.h b/arch/riscv32/fe310/src/StdDriver/inc/dac.h new file mode 100644 index 00000000..bd1bc6c5 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/dac.h @@ -0,0 +1,257 @@ +/****************************************************************************** + * @file dac.h + * @version V1.00 + * @brief M2351 series DAC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __DAC_H__ +#define __DAC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + + +/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* DAC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<SWTRG = DAC_SWTRG_SWTRG_Msk) + +/** + * @brief Enable DAC data left-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion. + */ +#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable DAC data right-aligned. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion. + */ +#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk) + +/** + * @brief Enable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and + * drive external loads directly without having to add an external operational amplifier. + */ +#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk) + +/** + * @brief Disable output voltage buffer. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable output voltage buffer. + */ +#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @return None + * @details This macro is used to enable DAC interrupt. + */ +#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk) + +/** + * @brief Disable the interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @return None + * @details This macro is used to disable DAC interrupt. + */ +#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk) + +/** + * @brief Enable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to enable DMA under-run interrupt. + */ +#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Disable DMA under-run interrupt. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA under-run interrupt. + */ +#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk) + +/** + * @brief Enable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set. + */ +#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk) + +/** + * @brief Disable PDMA mode. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details This macro is used to disable DMA mode. + */ +#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk) + +/** + * @brief Write data for conversion. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF. + * @return None + * @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits. + * 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits. + */ +#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data)) + +/** + * @brief Read DAC 12-bit holding data. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @return Return DAC 12-bit holding data. + * @details This macro is used to read DAC_DAT register. + */ +#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT) + +/** + * @brief Get the busy state of DAC. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state. + */ +#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos) + +/** + * @brief Get the interrupt flag. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @retval 0 DAC is in conversion state. + * @retval 1 DAC conversion finish. + * @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag. + */ +#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk) + +/** + * @brief Get the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @retval 0 No DMA under-run error condition occurred. + * @retval 1 DMA under-run error condition occurred. + * @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state. + */ +#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos) + +/** + * @brief This macro clear the interrupt status bit. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @return None + * @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag. + */ +#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk) + +/** + * @brief This macro clear the DMA under-run flag. + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag. + */ +#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk) + + +/** + * @brief Enable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_ENABLE_GROUP_MODE(dac) ((dac)->CTL |= DAC_CTL_GRPEN_Msk) + +/** + * @brief Disable DAC group mode + * @param[in] dac The pointer of the specified DAC module. + * @return None + * @note Only DAC0 has this control bit. + * \hideinitializer + */ +#define DAC_DISABLE_GROUP_MODE(dac) ((dac)->CTL &= ~DAC_CTL_GRPEN_Msk) + +void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc); +void DAC_Close(DAC_T *dac, uint32_t u32Ch); +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay); + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/eadc.h b/arch/riscv32/fe310/src/StdDriver/inc/eadc.h new file mode 100644 index 00000000..92be4ed2 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/eadc.h @@ -0,0 +1,555 @@ +/****************************************************************************** + * @file eadc.h + * @version V0.10 + * @brief M2351 series EADC driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __EADC_H__ +#define __EADC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* EADC_CTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EADC_CTL_DIFFEN_SINGLE_END (0UL<CTL |= EADC_CTL_ADCRST_Msk) + +/** + * @brief Enable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register, + * user can enable this bit to generate a PDMA data transfer request. + * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt. + */ +#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk) + +/** + * @brief Disable PDMA transfer. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable PDMA transfer. + */ +#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk)) + +/** + * @brief Enable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details The ADC controller supports a double buffer mode in sample module 0~3. + * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable. + */ +#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk) + +/** + * @brief Disable double buffer mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3. + * @return None + * @details Sample has one sample result register. + */ +#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk) + +/** + * @brief Set ADIFn at A/D end of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion. + */ +#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk) + +/** + * @brief Set ADIFn at A/D start of conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @return None + * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion. + */ +#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk) + +/** + * @brief Enable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion. + * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3). + */ +#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Disable the interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status. + * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3. + * @return None + * @details Specific sample module A/D ADINT0 interrupt function Disabled. + */ +#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos)) + +/** + * @brief Enable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask)) + +/** + * @brief Disable the sample module interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3. + * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status. + * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF. + * @return None + * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address. + */ +#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask)) + +/** + * @brief Set the input mode output format. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Format Decides the output format. Valid values are: + * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result. + * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result. + * @return None + * @details The macro is used to set A/D input mode output format. + */ +#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format)) + +/** + * @brief Start the A/D conversion. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18. + * @return None + * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion. + */ +#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask)) + +/** + * @brief Cancel the conversion for sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module. + * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF. + * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18. + * @return None + * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it. + */ +#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask)) + +/** + * @brief Get the conversion pending flag. + * @param[in] eadc The pointer of the specified EADC module. + * @return Return the conversion pending sample module. + * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end, + * the STPFn (n=0~18) bit is automatically cleared to 0. + */ +#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS) + +/** + * @brief Get the conversion data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the conversion data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data. + */ +#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk) + +/** + * @brief Get the data overrun flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF. + * @return Return the data overrun flag of the user-specified sample module. + * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status. + */ +#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask)) + +/** + * @brief Get the data valid flag of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF. + * @return Return the data valid flag of the user-specified sample module. + * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[2:0]) field to get data valid status. + */ +#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask)) + +/** + * @brief Get the double data of the user-specified sample module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @return Return the double data of the user-specified sample module. + * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data. + */ +#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT0_RESULT_Msk) + +/** + * @brief Get the user-specified interrupt flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return Return the user-specified interrupt flags. + * @details This macro is used to get the user-specified interrupt flags. + */ +#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask)) + +/** + * @brief Get the user-specified sample module overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF. + * @return Return the user-specified sample module overrun flags. + * @details This macro is used to get the user-specified sample module overrun flags. + */ +#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask)) + +/** + * @brief Clear the selected interrupt status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status. + * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3. + * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3. + * @return None + * @details This macro is used to clear clear the selected interrupt status bits. + */ +#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask)) + +/** + * @brief Clear the selected sample module overrun status bits. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status. + * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18. + * @return None + * @details This macro is used to clear the selected sample module overrun status bits. + */ +#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask)) + +/** + * @brief Check all sample module A/D result data register overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register overrun flag is set to 1. + * @retval 1 Any one of sample module data register overrun flag is set to 1. + * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1. + */ +#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos) + +/** + * @brief Check all sample module A/D result data register valid flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module data register valid flag is set to 1. + * @retval 1 Any one of sample module data register valid flag is set to 1. + * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1. + */ +#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos) + +/** + * @brief Check all A/D sample module start of conversion overrun flags. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of sample module event overrun flag is set to 1. + * @retval 1 Any one of sample module event overrun flag is set to 1. + * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1. + */ +#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos) + +/** + * @brief Check all A/D interrupt flag overrun bits. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 None of ADINT interrupt flag is overwritten to 1. + * @retval 1 Any one of ADINT interrupt flag is overwritten to 1. + * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1. + */ +#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos) + +/** + * @brief Get the busy state of EADC. + * @param[in] eadc The pointer of the specified EADC module. + * @retval 0 Idle state. + * @retval 1 Busy state. + * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state. + */ +#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos) + +/** + * @brief Configure the comparator 0 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP0(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 1 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP1(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 2 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP2(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Configure the comparator 3 and enable it. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18. + * @param[in] u32Condition specifies the compare condition. Valid values are: + * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value" + * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value + * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF. + * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF. + * @return None + * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE); + * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or + * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP3(eadc,\ + u32ModuleNum,\ + u32Condition,\ + u16CMPData,\ + u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\ + (u32Condition) |\ + ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \ + (((u32MatchCount) - 1UL) << EADC_CMP_CMPMCNT_Pos)|\ + EADC_CMP_ADCMPEN_Msk)) + +/** + * @brief Enable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched. + */ +#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk) + +/** + * @brief Disable the compare window mode. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2. + * @return None + * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched. + */ +#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk) + +/** + * @brief Enable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3) + * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile, + * if ADCMPIE is set to 1, a compare interrupt request is generated. + */ +#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable the compare interrupt. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3. + * @return None + * @details This macro is used to disable the compare interrupt. + */ +#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk) + +/** + * @brief Disable comparator 0. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 0. + */ +#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0UL) + +/** + * @brief Disable comparator 1. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 1. + */ +#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0UL) + +/** + * @brief Disable comparator 2. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 2. + */ +#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0UL) + +/** + * @brief Disable comparator 3. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details This macro is used to disable comparator 3. + */ +#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0UL) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EADC functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode); +void EADC_Close(EADC_T *eadc); +void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSrc, uint32_t u32Channel); +void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider); +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime); + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EADC_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/ebi.h b/arch/riscv32/fe310/src/StdDriver/inc/ebi.h new file mode 100644 index 00000000..bee55c8c --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/ebi.h @@ -0,0 +1,371 @@ +/**************************************************************************//** + * @file ebi.h + * @version V3.00 + * @brief External Bus Interface(EBI) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EBI_H__ +#define __EBI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address \hideinitializer */ +#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address \hideinitializer */ +#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address \hideinitializer */ +#define EBI_BANK0_BASE_ADDR_NS 0x70000000UL /*!< EBI bank0 base address for Non-Secure \hideinitializer */ +#define EBI_BANK1_BASE_ADDR_NS 0x70100000UL /*!< EBI bank1 base address for Non-Secure \hideinitializer */ +#define EBI_BANK2_BASE_ADDR_NS 0x70200000UL /*!< EBI bank2 base address for Non-Secure \hideinitializer */ +#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI bank number */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BANK0 0UL /*!< EBI bank 0 \hideinitializer */ +#define EBI_BANK1 1UL /*!< EBI bank 1 \hideinitializer */ +#define EBI_BANK2 2UL /*!< EBI bank 2 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI data bus width */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit \hideinitializer */ +#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI CS Active Level */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low \hideinitializer */ +#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Constants for EBI MCLK divider and Timing */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 \hideinitializer */ +#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 \hideinitializer */ +#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 \hideinitializer */ +#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 \hideinitializer */ +#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 \hideinitializer */ +#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 \hideinitializer */ +#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 \hideinitializer */ +#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 \hideinitializer */ + +#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest \hideinitializer */ +#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast \hideinitializer */ +#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast \hideinitializer */ +#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal \hideinitializer */ +#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow \hideinitializer */ +#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow \hideinitializer */ +#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest \hideinitializer */ + +#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode \hideinitializer */ +#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode \hideinitializer */ +#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode \hideinitializer */ + +/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */ + + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Read 8-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank0 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank0. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank0. + * \hideinitializer + */ +#define EBI0_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK0_BASE_ADDR:EBI_BANK0_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 32-bit data to EBI bank1 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank1. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank1. + * \hideinitializer + */ +#define EBI1_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK1_BASE_ADDR:EBI_BANK1_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 8-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 8-bit Data + * + * @details This macro is used to read 8-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA8(ebi, u32Addr) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 8-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 8-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA8(ebi, u32Addr, u32Data) (*((volatile unsigned char *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 16-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 16-bit Data + * + * @details This macro is used to read 16-bit data from specify address on EBI bank2. + */ +#define EBI2_READ_DATA16(ebi, u32Addr) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) + +/** + * @brief Write 16-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 16-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA16(ebi, u32Addr, u32Data) (*((volatile unsigned short *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Read 32-bit data on EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * + * @return 32-bit Data + * + * @details This macro is used to read 32-bit data from specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_READ_DATA32(ebi, u32Addr) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr)))) +/** + * @brief Write 32-bit data to EBI bank2 + * + * @param[in] ebi The pointer of EBI module. + * @param[in] u32Addr The data address on EBI bank2. + * @param[in] u32Data Specify data to be written. + * + * @return None + * + * @details This macro is used to write 32-bit data to specify address on EBI bank2. + * \hideinitializer + */ +#define EBI2_WRITE_DATA32(ebi, u32Addr, u32Data) (*((volatile unsigned int *)((((ebi)==EBI)? EBI_BANK2_BASE_ADDR:EBI_BANK2_BASE_ADDR_NS)+(u32Addr))) = (u32Data)) + +/** + * @brief Enable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to improve EBI write operation for all EBI banks. + * \hideinitializer + */ +#define EBI_ENABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 |= EBI_CTL_WBUFEN_Msk); + +/** + * @brief Disable EBI Write Buffer + * + * @param[in] ebi The pointer of EBI module. + * + * @return None + * + * @details This macro is used to disable EBI write buffer function. + * \hideinitializer + */ +#define EBI_DISABLE_WRITE_BUFFER(ebi) ((ebi)->CTL0 &= ~EBI_CTL_WBUFEN_Msk); + +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel); +void EBI_Close(uint32_t u32Bank); +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv); + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EBI_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/ecap.h b/arch/riscv32/fe310/src/StdDriver/inc/ecap.h new file mode 100644 index 00000000..136fe76e --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/ecap.h @@ -0,0 +1,461 @@ +/**************************************************************************//** + * @file ecap.h + * @version V3.00 + + * @brief EnHanced Input Capture Timer(ECAP) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __ECAP_H__ +#define __ECAP_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants + @{ +*/ + +#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit \hideinitializer */ +#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit \hideinitializer */ +#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ECAP CTL0 constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL<CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|(u32ClkSel)) + +/** + * @brief This macro is used to disable noise filter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the noise filter of input capture. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPNFDIS_Msk) + +/** + * @brief This macro is used to enable noise filter + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSel Select noise filter clock divide number + * - \ref ECAP_NOISE_FILTER_CLKDIV_1 + * - \ref ECAP_NOISE_FILTER_CLKDIV_2 + * - \ref ECAP_NOISE_FILTER_CLKDIV_4 + * - \ref ECAP_NOISE_FILTER_CLKDIV_16 + * - \ref ECAP_NOISE_FILTER_CLKDIV_32 + * - \ref ECAP_NOISE_FILTER_CLKDIV_64 + * @return None + * @details This macro will enable the noise filter of input capture and set noise filter clock divide. + * \hideinitializer + */ +#define ECAP_NOISE_FILTER_ENABLE(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPNFDIS_Msk|ECAP_CTL0_NFCLKSEL_Msk))|(u32ClkSel)) + +/** + * @brief This macro is used to enable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will enable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel unit + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_CTL0_IC0EN_Msk + * - \ref ECAP_CTL0_IC1EN_Msk + * - \ref ECAP_CTL0_IC2EN_Msk + * @return None + * @details This macro will disable the input channel_n to input capture. + * \hideinitializer + */ +#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to select input channel source + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Src The input source + * - \ref ECAP_CAP_INPUT_SRC_FROM_IC + * - \ref ECAP_CAP_INPUT_SRC_FROM_CH + * @return None + * @details This macro will select the input source from ICx, CHx. + * \hideinitializer + */ +#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|(((u32Src)<CTL0 |= (u32Mask)) + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return None + * @details This macro will disable the input channel_n interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask)) + +/** + * @brief This macro is used to enable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to disable input channel overflow interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel overflow interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk) + +/** + * @brief This macro is used to enable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to disable input channel compare-match interrupt + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the input channel compare-match interrupt. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk) + +/** + * @brief This macro is used to start capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will start capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to stop capture counter + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will stop capture counter up-counting. + * \hideinitializer + */ +#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk) + +/** + * @brief This macro is used to set event to clear capture counter + * @param[in] ecap Specify ECAP port + * @param[in] u32Event The input channel number + * - \ref ECAP_CTL0_CMPCLREN_Msk + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + + * @return None + * @details This macro will enable and select compare or capture event that can clear capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) do{ \ + if((u32Event) & ECAP_CTL0_CMPCLREN_Msk) \ + (ecap)->CTL0 |= ECAP_CTL0_CMPCLREN_Msk; \ + else \ + (ecap)->CTL0 &= ~ECAP_CTL0_CMPCLREN_Msk; \ + (ecap)->CTL1 = ((ecap)->CTL1 &~0xF00ul) | ((u32Event) & 0xF00); \ + }while(0) + +/** + * @brief This macro is used to enable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable the compare function. + * \hideinitializer + */ +#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to disable compare function + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable the compare function. + * \hideinitializer + */ +#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk) + +/** + * @brief This macro is used to enable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will enable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to disable input capture function. + * @param[in] ecap Specify ECAP port + * @return None + * @details This macro will disable input capture timer/counter. + * \hideinitializer + */ +#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk) + +/** + * @brief This macro is used to select input channel edge detection + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @param[in] u32Edge The input source + * - \ref ECAP_RISING_EDGE + * - \ref ECAP_FALLING_EDGE + * - \ref ECAP_RISING_FALLING_EDGE + * @return None + * @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change. + * \hideinitializer + */ +#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<((u32Index)<<1))) + +/** + * @brief This macro is used to select ECAP counter reload trigger source + * @param[in] ecap Specify ECAP port + * @param[in] u32TrigSrc The input source + * - \ref ECAP_CTL1_CAP0RLDEN_Msk + * - \ref ECAP_CTL1_CAP1RLDEN_Msk + * - \ref ECAP_CTL1_CAP2RLDEN_Msk + * - \ref ECAP_CTL1_OVRLDEN_Msk + * @return None + * @details This macro will select capture counter reload trigger source. + * \hideinitializer + */ +#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~0xF00)|(u32TrigSrc)) + +/** + * @brief This macro is used to select capture timer clock divide. + * @param[in] ecap Specify ECAP port + * @param[in] u32Clkdiv The input source + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_1 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_4 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_16 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_32 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_64 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_96 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_112 + * - \ref ECAP_CAPTURE_TIMER_CLKDIV_128 + * @return None + * @details This macro will select capture timer clock has a pre-divider with eight divided option. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|(u32Clkdiv)) + +/** + * @brief This macro is used to select capture timer/counter clock source + * @param[in] ecap Specify ECAP port + * @param[in] u32ClkSrc The input source + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 + * - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 + * @return None + * @details This macro will select capture timer/clock clock source. + * \hideinitializer + */ +#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRCSEL_Msk)|(u32ClkSrc)) + +/** + * @brief This macro is used to read input capture status + * @param[in] ecap Specify ECAP port + * @return Input capture status flags + * @details This macro will get the input capture interrupt status. + * \hideinitializer + */ +#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS) + +/** + * @brief This macro is used to get input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to get the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0) + +/** + * @brief This macro is used to clear input channel interrupt flag + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel mask + * - \ref ECAP_STATUS_CAPTF0_Msk + * - \ref ECAP_STATUS_CAPTF1_Msk + * - \ref ECAP_STATUS_CAPTF2_Msk + * - \ref ECAP_STATUS_CAPOVF_Msk + * - \ref ECAP_STATUS_CAPCMPF_Msk + * @return None + * @details This macro will write 1 to clear the input channel_n interrupt flag. + * \hideinitializer + */ +#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask)) + +/** + * @brief This macro is used to set input capture counter value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Counter value + * @return None + * @details This macro will set a counter value of input capture. + * \hideinitializer + */ +#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val)) + +/** + * @brief This macro is used to get input capture counter value + * @param[in] ecap Specify ECAP port + * @return Capture counter value + * @details This macro will get a counter value of input capture. + * \hideinitializer + */ +#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT) + +/** + * @brief This macro is used to get input capture counter hold value + * @param[in] ecap Specify ECAP port + * @param[in] u32Index The input channel number + * - \ref ECAP_IC0 + * - \ref ECAP_IC1 + * - \ref ECAP_IC2 + * @return Capture counter hold value + * @details This macro will get a hold value of input capture channel_n. + * \hideinitializer + */ +#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index))) + +/** + * @brief This macro is used to set input capture counter compare value + * @param[in] ecap Specify ECAP port + * @param[in] u32Val Input capture compare value + * @return None + * @details This macro will set a compare value of input capture counter. + * \hideinitializer + */ +#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val)) + +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask); +void ECAP_Close(ECAP_T* ecap); +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask); +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask); +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__ECAP_H__*/ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/epwm.h b/arch/riscv32/fe310/src/StdDriver/inc/epwm.h new file mode 100644 index 00000000..304b1623 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/epwm.h @@ -0,0 +1,626 @@ +/**************************************************************************//** + * @file epwm.h + * @version V3.00 + * @brief M2351 series EPWM driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __EPWM_H__ +#define __EPWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + +/** @addtogroup EPWM_EXPORTED_CONSTANTS EPWM Exported Constants + @{ +*/ +#define EPWM_CHANNEL_NUM (6UL) /*!< EPWM channel number */ +#define EPWM_CH_0_MASK (0x1UL) /*!< EPWM channel 0 mask \hideinitializer */ +#define EPWM_CH_1_MASK (0x2UL) /*!< EPWM channel 1 mask \hideinitializer */ +#define EPWM_CH_2_MASK (0x4UL) /*!< EPWM channel 2 mask \hideinitializer */ +#define EPWM_CH_3_MASK (0x8UL) /*!< EPWM channel 3 mask \hideinitializer */ +#define EPWM_CH_4_MASK (0x10UL) /*!< EPWM channel 4 mask \hideinitializer */ +#define EPWM_CH_5_MASK (0x20UL) /*!< EPWM channel 5 mask \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_UP_COUNTER (0UL) /*!< Up counter type */ +#define EPWM_DOWN_COUNTER (1UL) /*!< Down counter type */ +#define EPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Aligned Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_EDGE_ALIGNED (1UL) /*!< EPWM working in edge aligned type(down count) */ +#define EPWM_CENTER_ALIGNED (2UL) /*!< EPWM working in center aligned type */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_OUTPUT_NOTHING (0UL) /*!< EPWM output nothing */ +#define EPWM_OUTPUT_LOW (1UL) /*!< EPWM output low */ +#define EPWM_OUTPUT_HIGH (2UL) /*!< EPWM output high */ +#define EPWM_OUTPUT_TOGGLE (3UL) /*!< EPWM output toggle */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Synchronous Start Function Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define EPWM_SSCTL_SSRC_EPWM0 (0UL<CTL1 = (epwm)->CTL1 | (0x7ul<CTL1 = (epwm)->CTL1 & ~(0x7ul<CTL0 = (epwm)->CTL0 | EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief This macro disable group mode + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to disable group mode of EPWM module. + * \hideinitializer + */ +#define EPWM_DISABLE_GROUP_MODE(epwm) ((epwm)->CTL0 = (epwm)->CTL0 & ~EPWM_CTL0_GROUPEN_Msk) + +/** + * @brief Enable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32SyncSrc Synchronous start source selection, valid values are: + * - \ref EPWM_SSCTL_SSRC_EPWM0 + * - \ref EPWM_SSCTL_SSRC_EPWM1 + * - \ref EPWM_SSCTL_SSRC_BPWM0 + * - \ref EPWM_SSCTL_SSRC_BPWM1 + * @return None + * @details This macro is used to enable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_TIMER_SYNC(epwm, u32ChannelMask, u32SyncSrc) ((epwm)->SSCTL = ((epwm)->SSCTL & ~EPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask)) + +/** + * @brief Disable timer synchronous start counting function of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to disable timer synchronous start counting function of specified channel(s). + * \hideinitializer + */ +#define EPWM_DISABLE_TIMER_SYNC(epwm, u32ChannelMask) \ + do{ \ + int i;\ + for(i = 0; i < 6; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->SSCTL &= ~(1UL << i); \ + } \ + } \ + }while(0) + +/** + * @brief This macro enable EPWM counter synchronous start counting function. + * @param[in] epwm The pointer of the specified EPWM module + * @return None + * @details This macro is used to make selected EPWM0 and EPWM1 channel(s) start counting at the same time. + * To configure synchronous start counting channel(s) by EPWM_ENABLE_TIMER_SYNC() and EPWM_DISABLE_TIMER_SYNC(). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC_START(epwm) ((epwm)->SSTRG = EPWM_SSTRG_CNTSEN_Msk) + +/** + * @brief This macro enable output inverter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to enable output inverter of specified channel(s). + * \hideinitializer + */ +#define EPWM_ENABLE_OUTPUT_INVERTER(epwm, u32ChannelMask) ((epwm)->POLCTL = (u32ChannelMask)) + +/** + * @brief This macro get captured rising data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured rising data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_RISING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].RCAPDAT) + +/** + * @brief This macro get captured falling data + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This macro is used to get captured falling data of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CAPTURE_FALLING_DATA(epwm, u32ChannelNum) ((epwm)->CAPDAT[(u32ChannelNum)].FCAPDAT) + +/** + * @brief This macro mask output logic to high or low + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32LevelMask Output logic to high or low + * @return None + * @details This macro is used to mask output logic to high or low of specified channel(s). + * @note If u32ChannelMask parameter is 0, then mask function will be disabled. + * \hideinitializer + */ +#define EPWM_MASK_OUTPUT(epwm, u32ChannelMask, u32LevelMask) \ + do{ \ + (epwm)->MSKEN = (u32ChannelMask); \ + (epwm)->MSK = (u32LevelMask); \ + }while(0) + +/** + * @brief This macro set the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @return None + * @details This macro is used to set the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescaler) ((epwm)->CLKPSC[(u32ChannelNum) >> 1] = (u32Prescaler)) + +/** + * @brief This macro get the prescaler of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF + * @details This macro is used to get the prescaler of specified channel. + * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected. + * The clock of EPWM counter is divided by (u32Prescaler + 1). + * \hideinitializer + */ +#define EPWM_GET_PRESCALER(epwm, u32ChannelNum) ((epwm)->CLKPSC[(u32ChannelNum) >> 1U]) + +/** + * @brief This macro set the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_CMR(epwm, u32ChannelNum, u32CMR) ((epwm)->CMPDAT[(u32ChannelNum)]= (u32CMR)) + +/** + * @brief This macro get the comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the comparator of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the comparator of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CMR(epwm, u32ChannelNum) ((epwm)->CMPDAT[(u32ChannelNum)]) + +/** + * @brief This macro set the free trigger comparator of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the free trigger comparator of specified channel. + * @note This new setting will take effect on next EPWM period. + * \hideinitializer + */ +#define EPWM_SET_FTCMR(epwm, u32ChannelNum, u32FTCMR) (((epwm)->FTCMPDAT[((u32ChannelNum) >> 1U)]) = (u32FTCMR)) + +/** + * @brief This macro set the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF + * @return None + * @details This macro is used to set the period of specified channel. + * @note This new setting will take effect on next EPWM period. + * @note EPWM counter will stop if period length set to 0. + * \hideinitializer + */ +#define EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR) ((epwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) + +/** + * @brief This macro get the period of the selected channel + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Return the period of specified channel. Valid values are between 0~0xFFFF + * @details This macro is used to get the period of specified channel. + * \hideinitializer + */ +#define EPWM_GET_CNR(epwm, u32ChannelNum) ((epwm)->PERIOD[(u32ChannelNum)]) + +/** + * @brief This macro set the EPWM aligned type + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32AlignedType EPWM aligned type, valid values are: + * - \ref EPWM_EDGE_ALIGNED + * - \ref EPWM_CENTER_ALIGNED + * @return None + * @details This macro is used to set the EPWM aligned type of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_ALIGNED_TYPE(epwm, u32ChannelMask, u32AlignedType) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) \ + { \ + (epwm)->CTL1 = (((epwm)->CTL1 & ~(3UL << (i << 1))) | ((u32AlignedType) << (i << 1))); \ + } \ + } \ + }while(0) + +/** + * @brief Set load window of window loading mode for specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to set load window of window loading mode for specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_LOAD_WINDOW(epwm, u32ChannelMask) ((epwm)->LOAD |= (u32ChannelMask)) + +/** + * @brief Trigger synchronous event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are 0, 2, 4 + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @return None + * @details This macro is used to trigger synchronous event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_SYNC(epwm, u32ChannelNum) ((epwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1))) + +/** + * @brief Clear counter of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @return None + * @details This macro is used to clear counter of specified channel(s). + * \hideinitializer + */ +#define EPWM_CLR_COUNTER(epwm, u32ChannelMask) ((epwm)->CNTCLR |= (u32ChannelMask)) + +/** + * @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32ZeroLevel output level at zero point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpUpLevel output level at compare up point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32PeriodLevel output level at period(center) point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @param[in] u32CmpDownLevel output level at compare down point, valid values are: + * - \ref EPWM_OUTPUT_NOTHING + * - \ref EPWM_OUTPUT_LOW + * - \ref EPWM_OUTPUT_HIGH + * - \ref EPWM_OUTPUT_TOGGLE + * @return None + * @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s). + * \hideinitializer + */ +#define EPWM_SET_OUTPUT_LEVEL(epwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \ + do{ \ + uint32_t i; \ + for(i = 0UL; i < 6UL; i++) { \ + if((u32ChannelMask) & (1UL << i)) { \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1))); \ + (epwm)->WGCTL0 = (((epwm)->WGCTL0 & ~(3UL << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))) | ((u32PeriodLevel) << (EPWM_WGCTL0_PRDPCTL0_Pos + (i << 1)))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (i << 1))) | ((u32CmpUpLevel) << (i << 1))); \ + (epwm)->WGCTL1 = (((epwm)->WGCTL1 & ~(3UL << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))) | ((u32CmpDownLevel) << (EPWM_WGCTL1_CMPDCTL0_Pos + (i << 1)))); \ + } \ + } \ + }while(0) + +/** + * @brief Trigger brake event from specified channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4 + * @param[in] u32BrakeType Type of brake trigger. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This macro is used to trigger brake event from specified channel(s). + * \hideinitializer + */ +#define EPWM_TRIGGER_BRAKE(epwm, u32ChannelMask, u32BrakeType) ((epwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType))) + +/** + * @brief Set Dead zone clock source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler). + * @return None + * @details This macro is used to set Dead zone clock source. Every two channels share the same setting. + * @note The write-protection function should be disabled before using this function. + * \hideinitializer + */ +#define EPWM_SET_DEADZONE_CLK_SRC(epwm, u32ChannelNum, u32AfterPrescaler) \ + (((epwm)->DTCTL[(u32ChannelNum) >> 1]) = ((epwm)->DTCTL[(u32ChannelNum) >> 1] & ~EPWM_DTCTL0_1_DTCKSEL_Msk) | \ + ((u32AfterPrescaler) << EPWM_DTCTL0_1_DTCKSEL_Pos)) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define EPWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge); +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle); +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition); +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource); +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode); +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration); +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge); +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource); +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc); +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode); +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase); +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask); +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm); +void EPWM_EnableSyncPinInverse(EPWM_T *epwm); +void EPWM_DisableSyncPinInverse(EPWM_T *epwm); +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel); +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel); +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum); +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule); +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable); +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum); + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __EPWM_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/fmc.h b/arch/riscv32/fe310/src/StdDriver/inc/fmc.h new file mode 100644 index 00000000..828dc3ec --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/fmc.h @@ -0,0 +1,495 @@ +/**************************************************************************//** + * @file fmc.h + * @version V3.0 + * $Revision: 2 $ + * $Date: 16/07/29 3:11p $ + * @brief M2351 Series Flash Memory Controller(FMC) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __FMC_H__ +#define __FMC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define ISBEN 0UL + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define Base Address */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */ +#define FMC_APROM_END 0x00080000UL /*!< APROM end address */ +#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address */ +#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */ +#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */ +#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */ +#define FMC_XOMR0_BASE 0x00200000UL /*!< XOMR 0 Base Address */ +#define FMC_XOMR1_BASE 0x00200010UL /*!< XOMR 1 Base Address */ +#define FMC_XOMR2_BASE 0x00200020UL /*!< XOMR 2 Base Address */ +#define FMC_XOMR3_BASE 0x00200030UL /*!< XOMR 3 Base Address */ +#define FMC_NSCBA_BASE 0x00200800UL /*!< Non-Secure base address */ +#define FMC_SCRLOCK_BASE 0x00200804UL /*!< Secure Region Lock base address */ +#define FMC_ARLOCK_BASE 0x00210804UL /*!< All Region Lock base address */ +#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */ +#define FMC_USER_CONFIG_0 0x00300000UL /*!< CONFIG 0 Address */ +#define FMC_USER_CONFIG_1 0x00300004UL /*!< CONFIG 1 Address */ +#define FMC_USER_CONFIG_2 0x00300008UL /*!< CONFIG 2 Address */ +#define FMC_USER_CONFIG_3 0x0030000CUL /*!< CONFIG 3 Address */ +#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address */ +#define FMC_KPROM_BASE 0x00311000UL /*!< Security ROM base address */ + +#define FMC_FLASH_PAGE_SIZE 0x800UL /*!< Flash Page Size (2048 Bytes) */ +#define FMC_PAGE_ADDR_MASK 0xFFFFF800UL /*!< Flash page address mask */ +#define FMC_MULTI_WORD_PROG_LEN 512UL /*!< The maximum length of a multi-word program. */ + +#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */ +#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */ +#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */ +#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* XOM region number constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define XOMR0 0UL /*!< XOM region 0 */ +#define XOMR1 1UL /*!< XOM region 1 */ +#define XOMR2 2UL /*!< XOM region 2 */ +#define XOMR3 3UL /*!< XOM region 3 */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCTL constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define IS_BOOT_FROM_LDROM 0x1UL /*!< ISPCTL setting to select to boot from LDROM */ +#define IS_BOOT_FROM_APROM 0x0UL /*!< ISPCTL setting to select to boot from APROM */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* ISPCMD constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define FMC_ISPCMD_READ 0x00UL /*!< ISP Command: Read Flash */ +#define FMC_ISPCMD_READ_UID 0x04UL /*!< ISP Command: Read Unique ID */ +#define FMC_ISPCMD_READ_ALL1 0x08UL /*!< ISP Command: Read all-one result */ +#define FMC_ISPCMD_READ_CID 0x0BUL /*!< ISP Command: Read Company ID */ +#define FMC_ISPCMD_READ_DID 0x0CUL /*!< ISP Command: Read Device ID */ +#define FMC_ISPCMD_READ_CKS 0x0DUL /*!< ISP Command: Read Checksum */ +#define FMC_ISPCMD_PROGRAM 0x21UL /*!< ISP Command: 32-bit Program Flash */ +#define FMC_ISPCMD_PAGE_ERASE 0x22UL /*!< ISP Command: Page Erase Flash */ +#define FMC_ISPCMD_BANK_ERASE 0x23UL /*!< ISP Command: Erase Flash bank 0 or 1 */ +#define FMC_ISPCMD_BLOCK_ERASE 0x25UL /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 */ +#define FMC_ISPCMD_PROGRAM_MUL 0x27UL /*!< ISP Command: Flash Multi-Word Program */ +#define FMC_ISPCMD_RUN_ALL1 0x28UL /*!< ISP Command: Run all-one verification*/ +#define FMC_ISPCMD_RUN_CKS 0x2DUL /*!< ISP Command: Run Check Calculation */ +#define FMC_ISPCMD_VECMAP 0x2EUL /*!< ISP Command: Set vector mapping */ +#define FMC_ISPCMD_READ_64 0x40UL /*!< ISP Command: 64-bit read Flash */ +#define FMC_ISPCMD_PROGRAM_64 0x61UL /*!< ISP Command: 64-bit program Flash */ + +#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */ +#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */ +#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */ + +/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* FMC Macro Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +/** + * @brief Enable ISP Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to enable ISP function. + * + */ +#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */ + +/** + * @brief Disable ISP Function + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function. + * + */ +#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */ + +/** + * @brief Enable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function. + * User needs to set LDUEN bit before they can update LDROM. + * + */ +#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */ + +/** + * @brief Disable LDROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function. + * + */ +#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */ + +/** + * @brief Enable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function. + * User needs to set CFGUEN bit before they can update User Configuration area. + * + */ +#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */ + +/** + * @brief Disable User Configuration Update Function + * + * @param None + * + * @return None + * + * @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function. + * + */ +#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */ + + +/** + * @brief Enable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will set APUEN bit of ISPCTL control register to enable APROM update function. + * User needs to set APUEN bit before they can update APROM in APROM boot mode. + * + */ +#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */ + +/** + * @brief Disable APROM Update Function + * + * @param None + * + * @return None + * + * @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function. + * + */ +#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */ + +/** + * @brief Set Boot from APROM + * + * @param None + * + * @return None + * + * @details This function is select booting from APROM. + * + */ +#define FMC_SET_APROM_BOOT() (FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk) /*!< Select booting from APROM */ + +/** + * @brief Set Boot from LDROM + * + * @param None + * + * @return None + * + * @details This function is select booting from LDROM. + * + */ +#define FMC_SET_LDROM_BOOT() (FMC->ISPCTL |= FMC_ISPCTL_BS_Msk) /*!< Select booting from LDROM */ + +/** + * @brief Get ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to get ISP fail flag when do ISP actoin. + * + */ +#define FMC_GET_FAIL_FLAG() ((FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) ? 1UL : 0UL) /*!< Get ISP fail flag */ + +/** + * @brief Clear ISP Fail Flag + * + * @param None + * + * @return None + * + * @details This function is used to clear ISP fail flag when ISP fail flag set. + * + */ +#define FMC_CLR_FAIL_FLAG() (FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk) /*!< Clear ISP fail flag */ + +/** + * @brief Enable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable ISP action interrupt. + * + */ +#define FMC_ENABLE_ISP_INT() (FMC->ISPCTL |= FMC_ISPCTL_INTEN_Msk) /*!< Enable ISP interrupt */ + +/** + * @brief Disable ISP Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable ISP action interrupt. + * + */ +#define FMC_DISABLE_ISP_INT() (FMC->ISPCTL &= ~FMC_ISPCTL_INTEN_Msk) /*!< Disable ISP interrupt */ + + +/** + * @brief Get ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will get ISP action interrupt status + * + */ +#define FMC_GET_ISP_INT_FLAG() ((FMC->ISPSTS & FMC_ISPSTS_INTFLAG_Msk) ? 1UL : 0UL) /*!< Get ISP interrupt flag Status */ + + +/** + * @brief Clear ISP Interrupt Flag + * + * @param None + * + * @return None + * + * @details This function will clear ISP interrupt flag + * + */ +#define FMC_CLEAR_ISP_INT_FLAG() (FMC->ISPSTS = FMC_ISPSTS_INTFLAG_Msk) /*!< Clear ISP interrupt flag*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +__STATIC_INLINE uint32_t FMC_ReadCID(void); +__STATIC_INLINE uint32_t FMC_ReadPID(void); +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index); +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index); +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr); +__STATIC_INLINE uint32_t FMC_GetVECMAP(void); + + +/** + * @brief Get current vector mapping address. + * + * @param None + * + * @return The current vector mapping address. + * + * @details To get VECMAP value which is the page address for remapping to vector page (0x0). + * + */ +__STATIC_INLINE uint32_t FMC_GetVECMAP(void) +{ + return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk); +} + +/** + * @brief Read company ID + * + * @param None + * + * @return The company ID (32-bit) + * + * @details The company ID of Nuvoton is fixed to be 0xDA + */ +__STATIC_INLINE uint32_t FMC_ReadCID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x0u; /* Must keep 0x0 when read CID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read product ID + * + * @param None + * + * @return The product ID (32-bit) + * + * @details This function is used to read product ID. + */ +__STATIC_INLINE uint32_t FMC_ReadPID(void) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */ + FMC->ISPADDR = 0x04u; /* Must keep 0x4 when read PID */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Read Unique ID + * + * @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64] + * + * @return The 32-bit unique ID data of specified UID index. + * + * @details To read out 96-bit Unique ID. + */ +__STATIC_INLINE uint32_t FMC_ReadUID(uint8_t u8Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; + FMC->ISPADDR = ((uint32_t)u8Index << 2u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + return FMC->ISPDAT; +} + +/** + * @brief To read UCID + * + * @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3. + * + * @return The UCID of specified index + * + * @details This function is used to read unique chip ID (UCID). + */ +__STATIC_INLINE uint32_t FMC_ReadUCID(uint32_t u32Index) +{ + FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */ + FMC->ISPADDR = (0x04u * u32Index) + 0x10u; /* The UCID is at offset 0x10 with word alignment. */ + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} /* Waiting for ISP Done */ + + return FMC->ISPDAT; +} + +/** + * @brief Set vector mapping address + * + * @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment. + * + * @return To set VECMAP to remap specified page address to 0x0. + * + * @details This function is used to set VECMAP to map specified page to vector page (0x0). + */ +__STATIC_INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr) +{ + FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */ + FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */ + FMC->ISPTRG = 0x1u; /* Trigger to start ISP procedure */ +#if ISBEN + __ISB(); +#endif /* To make sure ISP/CPU be Synchronized */ + while(FMC->ISPTRG) {} /* Waiting for ISP Done */ +} + +/*---------------------------------------------------------------------------------------------------------*/ +/* Functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +extern uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count); +extern void FMC_Close(void); +extern int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page); +extern int32_t FMC_Erase(uint32_t u32PageAddr); +extern int32_t FMC_Erase_Bank(uint32_t u32BankAddr); +extern int32_t FMC_Erase_Block(uint32_t u32BlockAddr); +extern int32_t FMC_EraseXOM(uint32_t xom_num); +extern int32_t FMC_GetBootSource(void); +extern uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count); +extern int32_t FMC_Is_OTP_Locked(uint32_t otp_num); +extern int32_t FMC_GetXOMState(uint32_t xom_num); +extern int32_t FMC_Lock_OTP(uint32_t otp_num); +extern void FMC_Open(void); +extern uint32_t FMC_Read(uint32_t u32Addr); +extern int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1); +extern int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word); +extern int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count); +extern void FMC_SetBootSource(int32_t i32BootSrc); +extern int32_t FMC_CompareSPKey(uint32_t key[3]); +extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM); +extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); +extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); +extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count); +extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); +extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __FMC_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/inc/gpio.h b/arch/riscv32/fe310/src/StdDriver/inc/gpio.h new file mode 100644 index 00000000..40b121db --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/gpio.h @@ -0,0 +1,771 @@ +/**************************************************************************//** + * @file GPIO.h + * @version V3.0 + * @brief M2351 series General Purpose I/O (GPIO) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __GPIO_H__ +#define __GPIO_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants + @{ +*/ + +#define GPIO_PIN_MAX 16UL /*!< Specify Maximum Pins of Each GPIO Port */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_MODE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */ +#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */ +#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */ +#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Interrupt Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */ +#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */ +#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */ +#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */ +#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_INTTYPE Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */ +#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Slew Rate Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode */ +#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */ +#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO Pull-up And Pull-down Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */ +#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */ +#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* GPIO_DBCTL Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */ +#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */ + +#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */ +#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */ + +#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */ +#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */ +#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */ +#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */ +#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */ +#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */ +#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */ +#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */ +#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */ +#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */ +#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */ + + +/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping. + * Example 1: + * + * PA0 = 1; + * + * It is used to set PA.0 to high; + * + * Example 2: + * + * if (PA0) + * PA0 = 0; + * + * If PA.0 pin status is high, then set PA.0 data output to low. + */ +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT0 ) +# define PA_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PA_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PA0 PA_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1 PA_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2 PA_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3 PA_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4 PA_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5 PA_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6 PA_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7 PA_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8 PA_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9 PA_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10 PA_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11 PA_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12 PA_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13 PA_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14 PA_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15 PA_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT1 ) +# define PB_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PB_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PB0 PB_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1 PB_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2 PB_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3 PB_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4 PB_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5 PB_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6 PB_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7 PB_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8 PB_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9 PB_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10 PB_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11 PB_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12 PB_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13 PB_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14 PB_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15 PB_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT2 ) +# define PC_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PC_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PC0 PC_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1 PC_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2 PC_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3 PC_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4 PC_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5 PC_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6 PC_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7 PC_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8 PC_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9 PC_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10 PC_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11 PC_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12 PC_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13 PC_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT3 ) +# define PD_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PD_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PD0 PD_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1 PD_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2 PD_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3 PD_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4 PD_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5 PD_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6 PD_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7 PD_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8 PD_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9 PD_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10 PD_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11 PD_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12 PD_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD13 PD_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ +#define PD14 PD_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT4 ) +# define PE_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PE_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PE0 PE_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1 PE_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2 PE_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3 PE_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4 PE_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5 PE_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6 PE_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7 PE_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8 PE_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9 PE_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10 PE_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11 PE_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12 PE_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13 PE_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14 PE_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15 PE_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT5 ) +# define PF_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PF_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PF0 PF_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1 PF_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2 PF_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3 PF_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4 PF_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5 PF_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6 PF_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7 PF_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8 PF_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9 PF_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10 PF_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11 PF_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT6 ) +# define PG_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PG_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PG2 PG_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3 PG_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4 PG_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9 PG_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10 PG_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11 PG_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12 PG_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13 PG_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14 PG_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15 PG_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ + +#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT7 ) +# define PH_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#else +# define PH_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#endif +#define PH4 PH_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5 PH_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6 PH_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7 PH_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8 PH_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9 PH_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10 PH_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11 PH_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + +/* GPIO bit definitions for secure */ +#define GPIO_PIN_DATA_S(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) +#define PA0_S GPIO_PIN_DATA_S(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_S GPIO_PIN_DATA_S(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_S GPIO_PIN_DATA_S(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_S GPIO_PIN_DATA_S(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_S GPIO_PIN_DATA_S(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_S GPIO_PIN_DATA_S(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_S GPIO_PIN_DATA_S(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_S GPIO_PIN_DATA_S(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_S GPIO_PIN_DATA_S(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_S GPIO_PIN_DATA_S(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_S GPIO_PIN_DATA_S(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_S GPIO_PIN_DATA_S(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_S GPIO_PIN_DATA_S(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_S GPIO_PIN_DATA_S(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_S GPIO_PIN_DATA_S(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_S GPIO_PIN_DATA_S(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_S GPIO_PIN_DATA_S(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_S GPIO_PIN_DATA_S(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_S GPIO_PIN_DATA_S(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_S GPIO_PIN_DATA_S(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_S GPIO_PIN_DATA_S(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_S GPIO_PIN_DATA_S(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_S GPIO_PIN_DATA_S(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_S GPIO_PIN_DATA_S(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_S GPIO_PIN_DATA_S(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_S GPIO_PIN_DATA_S(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_S GPIO_PIN_DATA_S(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_S GPIO_PIN_DATA_S(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_S GPIO_PIN_DATA_S(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_S GPIO_PIN_DATA_S(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_S GPIO_PIN_DATA_S(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_S GPIO_PIN_DATA_S(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_S GPIO_PIN_DATA_S(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_S GPIO_PIN_DATA_S(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_S GPIO_PIN_DATA_S(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_S GPIO_PIN_DATA_S(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_S GPIO_PIN_DATA_S(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_S GPIO_PIN_DATA_S(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_S GPIO_PIN_DATA_S(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_S GPIO_PIN_DATA_S(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_S GPIO_PIN_DATA_S(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_S GPIO_PIN_DATA_S(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_S GPIO_PIN_DATA_S(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_S GPIO_PIN_DATA_S(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_S GPIO_PIN_DATA_S(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_S GPIO_PIN_DATA_S(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_S GPIO_PIN_DATA_S(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_S GPIO_PIN_DATA_S(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_S GPIO_PIN_DATA_S(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_S GPIO_PIN_DATA_S(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_S GPIO_PIN_DATA_S(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_S GPIO_PIN_DATA_S(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_S GPIO_PIN_DATA_S(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_S GPIO_PIN_DATA_S(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_S GPIO_PIN_DATA_S(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_S GPIO_PIN_DATA_S(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_S GPIO_PIN_DATA_S(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_S GPIO_PIN_DATA_S(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_S GPIO_PIN_DATA_S(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD13_S GPIO_PIN_DATA_S(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ +#define PD14_S GPIO_PIN_DATA_S(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_S GPIO_PIN_DATA_S(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_S GPIO_PIN_DATA_S(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_S GPIO_PIN_DATA_S(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_S GPIO_PIN_DATA_S(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_S GPIO_PIN_DATA_S(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_S GPIO_PIN_DATA_S(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_S GPIO_PIN_DATA_S(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_S GPIO_PIN_DATA_S(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_S GPIO_PIN_DATA_S(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_S GPIO_PIN_DATA_S(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_S GPIO_PIN_DATA_S(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_S GPIO_PIN_DATA_S(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_S GPIO_PIN_DATA_S(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_S GPIO_PIN_DATA_S(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_S GPIO_PIN_DATA_S(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_S GPIO_PIN_DATA_S(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_S GPIO_PIN_DATA_S(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_S GPIO_PIN_DATA_S(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_S GPIO_PIN_DATA_S(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_S GPIO_PIN_DATA_S(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_S GPIO_PIN_DATA_S(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_S GPIO_PIN_DATA_S(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_S GPIO_PIN_DATA_S(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_S GPIO_PIN_DATA_S(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_S GPIO_PIN_DATA_S(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_S GPIO_PIN_DATA_S(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_S GPIO_PIN_DATA_S(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_S GPIO_PIN_DATA_S(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_S GPIO_PIN_DATA_S(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_S GPIO_PIN_DATA_S(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_S GPIO_PIN_DATA_S(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_S GPIO_PIN_DATA_S(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_S GPIO_PIN_DATA_S(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_S GPIO_PIN_DATA_S(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_S GPIO_PIN_DATA_S(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_S GPIO_PIN_DATA_S(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_S GPIO_PIN_DATA_S(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_S GPIO_PIN_DATA_S(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_S GPIO_PIN_DATA_S(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_S GPIO_PIN_DATA_S(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_S GPIO_PIN_DATA_S(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_S GPIO_PIN_DATA_S(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_S GPIO_PIN_DATA_S(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_S GPIO_PIN_DATA_S(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_S GPIO_PIN_DATA_S(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_S GPIO_PIN_DATA_S(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + +/* GPIO bit definitions for non-secure */ +#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) +#define PA0_NS GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ +#define PA1_NS GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ +#define PA2_NS GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ +#define PA3_NS GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ +#define PA4_NS GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ +#define PA5_NS GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ +#define PA6_NS GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ +#define PA7_NS GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ +#define PA8_NS GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ +#define PA9_NS GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ +#define PA10_NS GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ +#define PA11_NS GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ +#define PA12_NS GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ +#define PA13_NS GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ +#define PA14_NS GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ +#define PA15_NS GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ +#define PB0_NS GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ +#define PB1_NS GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ +#define PB2_NS GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ +#define PB3_NS GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ +#define PB4_NS GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */ +#define PB5_NS GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ +#define PB6_NS GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ +#define PB7_NS GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ +#define PB8_NS GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ +#define PB9_NS GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ +#define PB10_NS GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ +#define PB11_NS GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ +#define PB12_NS GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ +#define PB13_NS GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ +#define PB14_NS GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ +#define PB15_NS GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ +#define PC0_NS GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ +#define PC1_NS GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ +#define PC2_NS GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ +#define PC3_NS GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ +#define PC4_NS GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ +#define PC5_NS GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ +#define PC6_NS GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ +#define PC7_NS GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ +#define PC8_NS GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ +#define PC9_NS GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ +#define PC10_NS GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */ +#define PC11_NS GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ +#define PC12_NS GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ +#define PC13_NS GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ +#define PD0_NS GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ +#define PD1_NS GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ +#define PD2_NS GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ +#define PD3_NS GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ +#define PD4_NS GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ +#define PD5_NS GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ +#define PD6_NS GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ +#define PD7_NS GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ +#define PD8_NS GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ +#define PD9_NS GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ +#define PD10_NS GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ +#define PD11_NS GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ +#define PD12_NS GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ +#define PD13_NS GPIO_PIN_DATA_NS(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ +#define PD14_NS GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ +#define PE0_NS GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ +#define PE1_NS GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */ +#define PE2_NS GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ +#define PE3_NS GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ +#define PE4_NS GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ +#define PE5_NS GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ +#define PE6_NS GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ +#define PE7_NS GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ +#define PE8_NS GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ +#define PE9_NS GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ +#define PE10_NS GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ +#define PE11_NS GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ +#define PE12_NS GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ +#define PE13_NS GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ +#define PE14_NS GPIO_PIN_DATA_NS(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ +#define PE15_NS GPIO_PIN_DATA_NS(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ +#define PF0_NS GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ +#define PF1_NS GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ +#define PF2_NS GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ +#define PF3_NS GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ +#define PF4_NS GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ +#define PF5_NS GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ +#define PF6_NS GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */ +#define PF7_NS GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ +#define PF8_NS GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ +#define PF9_NS GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ +#define PF10_NS GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ +#define PF11_NS GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ +#define PG2_NS GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ +#define PG3_NS GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ +#define PG4_NS GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ +#define PG9_NS GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ +#define PG10_NS GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ +#define PG11_NS GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ +#define PG12_NS GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ +#define PG13_NS GPIO_PIN_DATA_NS(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ +#define PG14_NS GPIO_PIN_DATA_NS(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ +#define PG15_NS GPIO_PIN_DATA_NS(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ +#define PH4_NS GPIO_PIN_DATA_NS(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ +#define PH5_NS GPIO_PIN_DATA_NS(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ +#define PH6_NS GPIO_PIN_DATA_NS(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ +#define PH7_NS GPIO_PIN_DATA_NS(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ +#define PH8_NS GPIO_PIN_DATA_NS(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ +#define PH9_NS GPIO_PIN_DATA_NS(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ +#define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ +#define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ + +/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ + + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Clear GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n + * It could be BIT0 ~ BIT13 for PE. \n + * It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG. + * + * @return None + * + * @details Clear the interrupt status of specified GPIO pin. + */ +#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask)) + +/** + * @brief Disable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask)) + +/** + * @brief Enable Pin De-bounce Function + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @return None + * + * @details Enable the interrupt de-bounce function of specified GPIO pin. + */ +#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask)) + +/** + * @brief Disable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O digital input path of specified GPIO pin. + */ +#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16)) + +/** + * @brief Enable I/O Digital Input Path + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O digital input path of specified GPIO pin. + */ +#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16)) + +/** + * @brief Disable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Disable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask)) + +/** + * @brief Enable I/O DOUT mask + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @return None + * + * @details Enable I/O DOUT mask of specified GPIO pin. + */ +#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask)) + +/** + * @brief Get GPIO Pin Interrupt Flag + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * + * @retval 0 No interrupt at specified GPIO pin + * @retval 1 The specified GPIO pin generate an interrupt + * + * @details Get the interrupt status of specified GPIO pin. + */ +#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask)) + +/** + * @brief Set De-bounce Sampling Cycle Time + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC. + * @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be + * - \ref GPIO_DBCTL_DBCLKSEL_1 + * - \ref GPIO_DBCTL_DBCLKSEL_2 + * - \ref GPIO_DBCTL_DBCLKSEL_4 + * - \ref GPIO_DBCTL_DBCLKSEL_8 + * - \ref GPIO_DBCTL_DBCLKSEL_16 + * - \ref GPIO_DBCTL_DBCLKSEL_32 + * - \ref GPIO_DBCTL_DBCLKSEL_64 + * - \ref GPIO_DBCTL_DBCLKSEL_128 + * - \ref GPIO_DBCTL_DBCLKSEL_256 + * - \ref GPIO_DBCTL_DBCLKSEL_512 + * - \ref GPIO_DBCTL_DBCLKSEL_1024 + * - \ref GPIO_DBCTL_DBCLKSEL_2048 + * - \ref GPIO_DBCTL_DBCLKSEL_4096 + * - \ref GPIO_DBCTL_DBCLKSEL_8192 + * - \ref GPIO_DBCTL_DBCLKSEL_16384 + * - \ref GPIO_DBCTL_DBCLKSEL_32768 + * + * @return None + * + * @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n + * Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n + * It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n + * Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us, + * and system will sampling interrupt input once per 400 us. + */ +#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel))) + +/** + * @brief Get GPIO Port IN Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * + * @return The specified port data + * + * @details Get the PIN register of specified GPIO port. + */ +#define GPIO_GET_IN_DATA(port) ((port)->PIN) + +/** + * @brief Set GPIO Port OUT Data + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Data GPIO port data. + * + * @return None + * + * @details Set the Data into specified GPIO port. + */ +#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data)) + +/** + * @brief Toggle Specified GPIO pin + * + * @param[in] u32Pin Pxy + * + * @return None + * + * @details Toggle the specified GPIO pint. + */ +#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1) + + +/** + * @brief Enable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_EnableEINT GPIO_EnableInt + +/** + * @brief Disable External GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +#define GPIO_DisableEINT GPIO_DisableInt + + +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs); +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin); +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode); + + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/hdiv.h b/arch/riscv32/fe310/src/StdDriver/inc/hdiv.h new file mode 100644 index 00000000..6637a17a --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/hdiv.h @@ -0,0 +1,90 @@ +/**************************************************************************//** + * @file hdiv.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M0564 series Hardware Divider(HDIV) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __HDIV_H__ +#define __HDIV_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup HDIV_Driver HDIV Driver + @{ +*/ + +/** @addtogroup HDIV_EXPORTED_FUNCTIONS HDIV Exported Functions + @{ +*/ + +/** + * @brief Division function to calculate (x/y) + * + * @param[in] x the dividend of the division + * @param[in] y the divisor of the division + * + * @return The result of (x/y) + * + * @details This is a division function to calculate x/y + * + */ +static __INLINE int32_t HDIV_Div(int32_t x, int16_t y) +{ + uint32_t *p32; + + p32 = (uint32_t *)HDIV_BASE; + *p32++ = (uint32_t)x; + *p32++ = (uint32_t)y; + return (int32_t) * p32; +} + + +/** + * @brief To calculate the remainder of x/y, i.e., the result of x mod y. + * + * @param[in] x the dividend of the division + * @param[in] y the divisor of the division + * + * @return The remainder of (x/y) + * + * @details This function is used to calculate the remainder of x/y. + */ +static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y) +{ + uint32_t *p32; + + p32 = (uint32_t *)HDIV_BASE; + *p32++ = (uint32_t)x; + *p32++ = (uint32_t)y; + return (int16_t)p32[1]; +} + +/*@}*/ /* end of group HDIV_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group HDIV_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif //__HDIV_H__ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + + diff --git a/arch/riscv32/fe310/src/StdDriver/inc/i2c.h b/arch/riscv32/fe310/src/StdDriver/inc/i2c.h new file mode 100644 index 00000000..75fab453 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/i2c.h @@ -0,0 +1,528 @@ +/**************************************************************************//** + * @file i2c.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2351 series I2C Serial Interface Controller(I2C) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __I2C_H__ +#define __I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + +/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_CTL_STA_SI (0x28U) /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */ +#define I2C_CTL_STA_SI_AA (0x2CU) /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */ +#define I2C_CTL_STO_SI (0x18U) /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */ +#define I2C_CTL_STO_SI_AA (0x1CU) /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */ +#define I2C_CTL_SI (0x08U) /*!< I2C_CTL setting for I2C control bits. It would set SI bit */ +#define I2C_CTL_SI_AA (0x0CU) /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */ +#define I2C_CTL_STA (0x20U) /*!< I2C_CTL setting for I2C control bits. It would set STA bit */ +#define I2C_CTL_STO (0x10U) /*!< I2C_CTL setting for I2C control bits. It would set STO bit */ +#define I2C_CTL_AA (0x04U) /*!< I2C_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_GCMODE_ENABLE (1U) /*!< Enable I2C GC Mode */ +#define I2C_GCMODE_DISABLE (0U) /*!< Disable I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* I2C SMBUS constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define I2C_SMBH_ENABLE (1U) /*!< Enable SMBus Host Mode enable */ +#define I2C_SMBD_ENABLE (0U) /*!< Enable SMBus Device Mode enable */ +#define I2C_PECTX_ENABLE (1U) /*!< Enable SMBus Packet Error Check Transmit function */ +#define I2C_PECTX_DISABLE (0U) /*!< Disable SMBus Packet Error Check Transmit function */ + +/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */ + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ +/** + * @brief The macro is used to set I2C bus condition at One Time + * + * @param[in] i2c Specify I2C port + * @param[in] u8Ctrl A byte writes to I2C control register + * + * @return None + * + * @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK. + */ +#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL0 = ((i2c)->CTL0 & ~0x3Cu) | (u8Ctrl)) + +/** + * @brief The macro is used to set START condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus START condition in I2C_CTL register. + */ +#define I2C_START(i2c) ((i2c)->CTL0 = ((i2c)->CTL0 | I2C_CTL0_SI_Msk) | I2C_CTL0_STA_Msk) + +/** + * @brief The macro is used to wait I2C bus status get ready + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register. + */ +#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL0 & I2C_CTL0_SI_Msk)) + +/** + * @brief The macro is used to Read I2C Bus Data Register + * + * @param[in] i2c Specify I2C port + * + * @return A byte of I2C data register + * + * @details I2C controller read data from bus and save it in I2CDAT register. + */ +#define I2C_GET_DATA(i2c) ((i2c)->DAT) + +/** + * @brief Write a Data to I2C Data Register + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data A byte that writes to data register + * + * @return None + * + * @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus. + */ +#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data)) + +/** + * @brief Get I2C Bus status code + * + * @param[in] i2c Specify I2C port + * + * @return I2C status code + * + * @details To get this status code to monitor I2C bus event. + */ +#define I2C_GET_STATUS(i2c) ((i2c)->STATUS0) + +/** + * @brief Get Time-out flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 I2C Bus time-out is not happened + * @retval 1 I2C Bus time-out is happened + * + * @details When I2C bus occurs time-out event, the time-out flag will be set. + */ +#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1u : 0u) + +/** + * @brief To get wake-up flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details I2C bus occurs wake-up event, wake-up flag will be set. + */ +#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1u : 0u) + +/** + * @brief To clear wake-up flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up flag is set, use this macro to clear it. + */ +#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk) + +/** + * @brief To get wake-up address frame ACK done flag from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @retval 0 The ACK bit cycle of address match frame is not done + * @retval 1 The ACK bit cycle of address match frame is done in power-down + * + * @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set. + * + * \hideinitializer + */ +#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1u : 0u) + +/** + * @brief To clear address frame ACK done flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details If wake-up done is set, use this macro to clear it. + * + * \hideinitializer + */ +#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk) + +/** + * @brief To get read/write status bit in address wakeup frame + * + * @param[in] i2c Specify I2C port + * + * @retval 0 Write command be record on the address match wakeup frame + * @retval 1 Read command be record on the address match wakeup frame. + * + * @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status. + * + * \hideinitializer +*/ +#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1u : 0u) + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS) + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return Packet error check byte value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC) + +/** + * @brief Set SMBus Bytes number of Transmission or reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize)) + +/** + * @brief Enable SMBus Alert function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Disable SMBus Alert pin function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host + * Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger) + * + */ +#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is output mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin is input mode + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode. + * + * + */ +#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk) + +/** + * @brief Set SMBus SUSCON pin output high state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state. + * + */ +#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk) + + +/** + * @brief Set SMBus SUSCON pin output low state + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state. + * + */ +#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk) + +/** + * @brief Enable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse. + * + */ +#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Disable SMBus Acknowledge control by manual + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable acknowledge response control by user. + * + */ +#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk) + +/** + * @brief Enable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Disable SMBus Acknowledge manual interrupt + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1 + * + */ +#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk) + +/** + * @brief Enable SMBus PEC clear at REPEAT START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to enable the condition of REAEAT START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Disable SMBus PEC clear at Repeat START + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details This function is used to disable the condition of Repeat START can clear the PEC calculation. + * + */ +#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk) + +/** + * @brief Enable RX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function. + */ +#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Enable TX PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function. + */ +#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function. + */ +#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function. + */ +#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk) + +/** + * @brief Enable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared. + */ +#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Disable PDMA stretch function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C wil send STOP after PDMA transfers done automatically. + */ +#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk) + +/** + * @brief Reset PDMA function. + * @param[in] i2c The pointer of the specified I2C module. + * @return None. + * @details I2C PDMA engine will be reset after this function is called. + */ +#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk) + +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +static __INLINE void I2C_STOP(I2C_T *i2c); + +/** + * @brief The macro is used to set STOP condition of I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Set the I2C bus STOP condition in I2C_CTL register. + */ +static __INLINE void I2C_STOP(I2C_T *i2c) +{ + + (i2c)->CTL0 |= (I2C_CTL0_SI_Msk | I2C_CTL0_STO_Msk); + CLK_SysTickDelay(10000); + while(i2c->CTL0 & I2C_CTL0_STO_Msk) {} +} + + +void I2C_ClearTimeoutFlag(I2C_T *i2c); +void I2C_Close(I2C_T *i2c); +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack); +void I2C_DisableInt(I2C_T *i2c); +void I2C_EnableInt(I2C_T *i2c); +uint32_t I2C_GetBusClockFreq(I2C_T *i2c); +uint32_t I2C_GetIntFlag(I2C_T *i2c); +uint32_t I2C_GetStatus(I2C_T *i2c); +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock); +uint8_t I2C_GetData(I2C_T *i2c); +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode); +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask); +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock); +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout); +void I2C_DisableTimeout(I2C_T *i2c); +void I2C_EnableWakeup(I2C_T *i2c); +void I2C_DisableWakeup(I2C_T *i2c); +void I2C_SetData(I2C_T *i2c, uint8_t u8Data); +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data); +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen); +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen); +uint32_t I2C_SMBusGetStatus(I2C_T *i2c); +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag); +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice); +void I2C_SMBusClose(I2C_T *i2c); +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk); +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/i2s.h b/arch/riscv32/fe310/src/StdDriver/inc/i2s.h new file mode 100644 index 00000000..12369ab0 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/i2s.h @@ -0,0 +1,363 @@ +/****************************************************************************//** + * @file i2s.h + * @version V3.00 + * @brief M2351 series I2S driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __I2S_H__ +#define __I2S_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants + @{ +*/ +#define I2S_DATABIT_8 (0UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */ +#define I2S_DATABIT_16 (1UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */ +#define I2S_DATABIT_24 (2UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */ +#define I2S_DATABIT_32 (3UL << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */ + +/* Audio Format */ +#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ +#define I2S_DISABLE_MONO (0UL) /*!< Stereo channel \hideinitializer */ +#define I2S_MONO I2S_ENABLE_MONO +#define I2S_STEREO I2S_DISABLE_MONO + + +/* I2S Data Format */ +#define I2S_FORMAT_I2S (0UL << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */ +#define I2S_FORMAT_I2S_MSB (1UL << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */ +#define I2S_FORMAT_I2S_LSB (2UL << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */ +#define I2S_FORMAT_PCM (4UL << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */ +#define I2S_FORMAT_PCM_MSB (5UL << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */ +#define I2S_FORMAT_PCM_LSB (6UL << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */ + +/* I2S Data Format */ +#define I2S_ORDER_AT_MSB 0UL /*!< Channel data is at MSB \hideinitializer */ +#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */ + +/* I2S TDM Channel Number */ +#define I2S_TDM_2CH 0UL /*!< Use TDM 2 channel \hideinitializer */ +#define I2S_TDM_4CH 1UL /*!< Use TDM 4 channel \hideinitializer */ +#define I2S_TDM_6CH 2UL /*!< Use TDM 6 channel \hideinitializer */ +#define I2S_TDM_8CH 3UL /*!< Use TDM 8 channel \hideinitializer */ + +/* I2S TDM Channel Width */ +#define I2S_TDM_WIDTH_8BIT 0UL /*!< TDM channel witch is 8-bit \hideinitializer */ +#define I2S_TDM_WIDTH_16BIT 1UL /*!< TDM channel witch is 16-bit \hideinitializer */ +#define I2S_TDM_WIDTH_24BIT 2UL /*!< TDM channel witch is 24-bit \hideinitializer */ +#define I2S_TDM_WIDTH_32BIT 3UL /*!< TDM channel witch is 32-bit \hideinitializer */ + +/* I2S TDM Sync Width */ +#define I2S_TDM_SYNC_ONE_BCLK 0UL /*!< TDM sync widht is one BLCK period \hideinitializer */ +#define I2S_TDM_SYNC_ONE_CHANNEL 1UL /*!< TDM sync widht is one channel period \hideinitializer */ + +/* I2S Operation mode */ +#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */ +#define I2S_MODE_MASTER 0UL /*!< As master mode \hideinitializer */ + +/* I2S FIFO Threshold */ +#define I2S_FIFO_TX_LEVEL_WORD_0 0UL /*!< TX threshold is 0 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_1 (1UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_2 (2UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_3 (3UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_4 (4UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_5 (5UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_6 (6UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_7 (7UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_8 (8UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_9 (9UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_10 (10UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_11 (11UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_12 (12UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_13 (13UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_14 (14UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_TX_LEVEL_WORD_15 (15UL << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 15 words \hideinitializer */ + +#define I2S_FIFO_RX_LEVEL_WORD_1 0UL /*!< RX threshold is 1 word \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_2 (1UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_3 (2UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_4 (3UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_5 (4UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_6 (5UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_7 (6UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_8 (7UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_9 (8UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 9 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_10 (9UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 10 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_11 (10UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 11 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_12 (11UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 12 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_13 (12UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 13 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_14 (13UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 14 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_15 (14UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 15 words \hideinitializer */ +#define I2S_FIFO_RX_LEVEL_WORD_16 (15UL << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 16 words \hideinitializer */ + +/* I2S Record Channel */ +#define I2S_MONO_RIGHT 0UL /*!< Record mono right channel \hideinitializer */ +#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */ + +/* I2S Channel */ +#define I2S_RIGHT 0UL /*!< Select right channel \hideinitializer */ +#define I2S_LEFT 1UL /*!< Select left channel \hideinitializer */ + +/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 |= (1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Disable zero cross detect function. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32ChMask is the mask for channel number (valid value is from (1~8). + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask) +{ + if((u32ChMask > 0UL) && (u32ChMask < 9UL)) + { + i2s->CTL1 &= ~(1UL << (u32ChMask - 1UL)); + } +} + +/** + * @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk ) + +/** + * @brief Disable I2S Tx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk ) + +/** + * @brief Enable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk ) + +/** + * @brief Disable I2S Rx function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk ) + +/** + * @brief Enable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk ) + +/** + * @brief Disable Tx Mute function . + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk ) + +/** + * @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk ) + +/** + * @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point. + * @param[in] i2s is the base address of I2S module. + * @return none + * \hideinitializer + */ +#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref I2S_MONO_LEFT + * - \ref I2S_MONO_RIGHT + * @return none + * \hideinitializer + */ +__STATIC_INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch) +{ + u32Ch == I2S_MONO_LEFT ? + (i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) : + (i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk); +} + +/** + * @brief Write data to I2S Tx FIFO. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Data: The data written to FIFO. + * @return none + * \hideinitializer + */ +#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = (u32Data) ) + +/** + * @brief Read Rx FIFO. + * @param[in] i2s is the base address of I2S module. + * @return Data in Rx FIFO. + * \hideinitializer + */ +#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO ) + +/** + * @brief This function gets the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) ) + +/** + * @brief This function clears the interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) ) + +/** + * @brief This function gets the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return The masked bit value of interrupt flag. + * \hideinitializer + */ +#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) ) + +/** + * @brief This function clears the zero crossing interrupt flag according to the mask parameter. + * @param[in] i2s is the base address of I2S module. + * @param[in] u32Mask is the mask for the all interrupt flags. + * @return none + * \hideinitializer + */ +#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s is the base address of I2S module. + * @return FIFO level + * \hideinitializer + */ +#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF ) + +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat); +void I2S_Close(I2S_T *i2s); +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask); +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask); +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock); +void I2S_DisableMCLK(I2S_T *i2s); +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth); + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __I2S_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/mkromlib.h b/arch/riscv32/fe310/src/StdDriver/inc/mkromlib.h new file mode 100644 index 00000000..718fdf4c --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/mkromlib.h @@ -0,0 +1,1137 @@ +/**************************************************************************//** + * @file MKROMLib.h + * @version V2.00 + * @brief MaskROM library header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __MKROM_LIB_H__ +#define __MKROM_LIB_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup MKROM_Driver MKROM Driver + @{ +*/ + +/** @addtogroup MKROM_EXPORTED_CONSTANTS MKROM Exported Constants + @{ +*/ +/*--------------------------------------------------------------------------------------------------*/ +/* Status and Error Code Constant Definitions */ +/*--------------------------------------------------------------------------------------------------*/ +#define BL_ERR_TT_CHECK 0xF0F00000UL /*!< Not a Non-secure parameter */ +#define BL_ERR_PARAMETER 0xF0F00001UL /*!< Invalid parameter */ +#define BL_PARAM_ALIGN 0xF0F00002UL /*!< Parameter alignment error */ +#define BL_NOT_FLASH_ADDR 0xF0F00003UL /*!< Invalid flash address */ +#define BL_NOT_SRAM_ADDR 0xF0F00004UL /*!< Invalid sram address */ +#define BL_XOM_NOT_CONFIG 0xF0F00005UL /*!< XOM is not configure yet */ +#define BL_XOM_HAS_CONFIG 0xF0F00006UL /*!< XOM has beeen configured */ +#define BL_XOM_HAS_ACTIVE 0xF0F00007UL /*!< XOM is actived */ +#define BL_XOM_BASE_ERROR 0xF0F00008UL /*!< Invalid XOM base address */ +#define BL_KPROM_NOT_ENABLE 0xF0F00009UL /*!< KPROM is not enabled yet */ +#define BL_KPROM_KEY_FORBID 0xF0F0000AUL /*!< KPROM comparison is forbidden */ +#define BL_KPROM_KEY_UNMATCH 0xF0F0000BUL /*!< KPROM comparison is unmatched */ +#define BL_KPROM_KEY_LOCKED 0xF0F0000CUL /*!< KPROM write-protect is enabled */ +#define BL_KPROM_SET_FAIL 0xF0F0000EUL /*!< Set KPROM key fail */ +#define BL_ISP_CMD_FAIL (-1) /*!< FMC command fail */ +#define BL_FLASH_ALLONE 0xA11FFFFFUL /*!< Check-all-one result is all one */ +#define BL_FLASH_NOT_ALLONE 0xA1100000UL /*!< Check-all-one result is not all one*/ + +/*--------------------------------------------------------------------------------------------------*/ +/* Random Number Generator Constant Definitions */ +/*--------------------------------------------------------------------------------------------------*/ +#define BL_RNG_PRNG (0UL) /*!CTL |= OTG_CTL_OTGEN_Msk):(OTG->CTL |= OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to disable OTG function + * @param None + * @return None + * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. + */ +#define OTG_DISABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk):(OTG->CTL &= ~OTG_CTL_OTGEN_Msk)) + +/** + * @brief This macro is used to enable USB PHY + * @param None + * @return None + * @details When the USB role is selected as OTG device, use this macro to enable USB PHY. + * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. + */ +#define OTG_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to disable USB PHY + * @param None + * @return None + * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. + */ +#define OTG_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)) + +/** + * @brief This macro is used to enable ID detection function + * @param None + * @return None + * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. + */ +#define OTG_ENABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to disable ID detection function + * @param None + * @return None + * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. + */ +#define OTG_DISABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)) + +/** + * @brief This macro is used to enable OTG wake-up function + * @param None + * @return None + * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. + */ +#define OTG_ENABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_WKEN_Msk):(OTG->CTL |= OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to disable OTG wake-up function + * @param None + * @return None + * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. + */ +#define OTG_DISABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk):(OTG->CTL &= ~OTG_CTL_WKEN_Msk)) + +/** + * @brief This macro is used to set the polarity of USB_VBUS_EN pin + * @param[in] u32Pol The polarity selection. Valid values are listed below. + * - \ref OTG_VBUS_EN_ACTIVE_HIGH + * - \ref OTG_VBUS_EN_ACTIVE_LOW + * @return None + * @details This macro is used to set the polarity of external USB VBUS power switch enable signal. + */ +#define OTG_SET_VBUS_EN_POL(u32Pol) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<INTEN |= (u32Mask)):(OTG->INTEN |= (u32Mask))) + +/** + * @brief This macro is used to disable OTG related interrupts + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTEN_ROLECHGIEN_Msk + * - \ref OTG_INTEN_VBEIEN_Msk + * - \ref OTG_INTEN_SRPFIEN_Msk + * - \ref OTG_INTEN_HNPFIEN_Msk + * - \ref OTG_INTEN_GOIDLEIEN_Msk + * - \ref OTG_INTEN_IDCHGIEN_Msk + * - \ref OTG_INTEN_PDEVIEN_Msk + * - \ref OTG_INTEN_HOSTIEN_Msk + * - \ref OTG_INTEN_BVLDCHGIEN_Msk + * - \ref OTG_INTEN_AVLDCHGIEN_Msk + * - \ref OTG_INTEN_VBCHGIEN_Msk + * - \ref OTG_INTEN_SECHGIEN_Msk + * - \ref OTG_INTEN_SRPDETIEN_Msk + * @return None + * @details This macro will disable OTG related interrupts specified by u32Mask parameter. + */ +#define OTG_DISABLE_INT(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN &= ~(u32Mask)):(OTG->INTEN &= ~(u32Mask))) + +/** + * @brief This macro is used to get OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return Interrupt flags of selected sources. + * @details This macro will return OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_GET_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS & (u32Mask)):(OTG->INTSTS & (u32Mask))) + +/** + * @brief This macro is used to clear OTG related interrupt flags + * @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref OTG_INTSTS_ROLECHGIF_Msk + * - \ref OTG_INTSTS_VBEIF_Msk + * - \ref OTG_INTSTS_SRPFIF_Msk + * - \ref OTG_INTSTS_HNPFIF_Msk + * - \ref OTG_INTSTS_GOIDLEIF_Msk + * - \ref OTG_INTSTS_IDCHGIF_Msk + * - \ref OTG_INTSTS_PDEVIF_Msk + * - \ref OTG_INTSTS_HOSTIF_Msk + * - \ref OTG_INTSTS_BVLDCHGIF_Msk + * - \ref OTG_INTSTS_AVLDCHGIF_Msk + * - \ref OTG_INTSTS_VBCHGIF_Msk + * - \ref OTG_INTSTS_SECHGIF_Msk + * - \ref OTG_INTSTS_SRPDETIF_Msk + * @return None + * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. + */ +#define OTG_CLR_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS = (u32Mask)):(OTG->INTSTS = (u32Mask))) + +/** + * @brief This macro is used to get OTG related status + * @param[in] u32Mask The combination of user specified source. Valid values are listed below. + * - \ref OTG_STATUS_OVERCUR_Msk + * - \ref OTG_STATUS_IDSTS_Msk + * - \ref OTG_STATUS_SESSEND_Msk + * - \ref OTG_STATUS_BVLD_Msk + * - \ref OTG_STATUS_AVLD_Msk + * - \ref OTG_STATUS_VBUSVLD_Msk + * @return The user specified status. + * @details This macro will return OTG related status specified by u32Mask parameter. + */ +#define OTG_GET_STATUS(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->STATUS & (u32Mask)):(OTG->STATUS & (u32Mask))) + + + +/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group OTG_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + + +#endif /* __OTG_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/pdma.h b/arch/riscv32/fe310/src/StdDriver/inc/pdma.h new file mode 100644 index 00000000..75f28ab0 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/pdma.h @@ -0,0 +1,380 @@ +/**************************************************************************//** + * @file pdma.h + * @version V3.00 + * @brief M2351 series PDMA driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __PDMA_H__ +#define __PDMA_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + +/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants + @{ +*/ +#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Operation Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA_OP_STOP 0x00000000UL /*!INTSTS)) + +/** + * @brief Get Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the transfer done Interrupt status. + */ +#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS)) + +/** + * @brief Clear Transfer Done Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the transfer done Interrupt status. + */ +#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask))) + +/** + * @brief Get Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the target abort Interrupt status. + */ +#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS)) + +/** + * @brief Clear Target Abort Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the target abort Interrupt status. + */ +#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask))) + +/** + * @brief Get PDMA Transfer Alignment Status + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details Get the PDMA transfer alignment status. + */ +#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN)) + +/** + * @brief Clear PDMA Transfer Alignment Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask The channel mask + * + * @return None + * + * @details Clear the PDMA transfer alignment Interrupt status. + */ +#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask))) + +/** + * @brief Clear Timeout Interrupt Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details Clear the selected channel timeout interrupt status. + * @note This function is only supported in channel 0 and channel 1. + */ +#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1UL << ((u32Ch) + 8UL)))) + +/** + * @brief Check Channel Status + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @retval 0 Idle state + * @retval 1 Busy state + * + * @details Check the selected channel is busy or not. + */ +#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1UL << (u32Ch)))? 1 : 0) + +/** + * @brief Set Source Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel source address. + */ +#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr))) + +/** + * @brief Set Destination Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The selected address + * + * @return None + * + * @details This macro set the selected channel destination address. + */ +#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr))) + +/** + * @brief Set Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32TransCount Transfer Count + * + * @return None + * + * @details This macro set the selected channel transfer count. + */ +#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1UL) << PDMA_DSCT_CTL_TXCNT_Pos))) + +/** + * @brief Set Scatter-gather descriptor Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Addr The descriptor address + * + * @return None + * + * @details This macro set the selected channel scatter-gather descriptor address. + */ +#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].NEXT = (u32Addr) - ((pdma)->SCATBA))) + +/** + * @brief Stop the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro stop the selected channel. + */ +#define PDMA_STOP(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Pause the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro pause the selected channel. + */ +#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1UL << (u32Ch)))) + +/** + * @brief Reset the channel + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This macro reset the selected channel. + */ +#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1UL << (u32Ch)))) + +/*---------------------------------------------------------------------------------------------------------*/ +/* Define PWM functions prototype */ +/*---------------------------------------------------------------------------------------------------------*/ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_Close(PDMA_T *pdma); +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount); +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount); +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl); +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr); +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize); +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask); +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt); +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch); +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask); + + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PDMA_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/qei.h b/arch/riscv32/fe310/src/StdDriver/inc/qei.h new file mode 100644 index 00000000..6adaec6e --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/qei.h @@ -0,0 +1,391 @@ +/**************************************************************************//** + * @file qei.h + * @version V3.00 + * @brief Quadrature Encoder Interface (QEI) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QEI_H__ +#define __QEI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* QEI counting mode selection constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<CTL &= (~QEI_CTL_CMPEN_Msk)) + +/** + * @brief Enable QEI compare function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI counter compare function. + * \hideinitializer + */ +#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk) + +/** + * @brief Disable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk)) + +/** + * @brief Enable QEI index latch function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter latch function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk) + +/** + * @brief Disable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk)) + +/** + * @brief Enable QEI index reload function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro enable QEI index trigger counter reload function. + * \hideinitializer + */ +#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk) + +/** + * @brief Disable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHAEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro disable specified QEI signal input. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable QEI input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAEN_Msk : QEA input + * - \ref QEI_CTL_CHBEN_Msk : QEB input + * - \ref QEI_CTL_IDXEN_Msk : IDX input + * @return None + * @details This macro enable specified QEI signal input. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type . + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro disable specified QEI signal inverted input polarity. + * \hideinitializer + */ +#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType)) + +/** + * @brief Enable inverted input polarity + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32InputType Input signal type. + * - \ref QEI_CTL_CHAINV_Msk : QEA Input + * - \ref QEI_CTL_CHBINV_Msk : QEB Input + * - \ref QEI_CTL_IDXINV_Msk : IDX Input + * @return None + * @details This macro inverse specified QEI signal input polarity. + * \hideinitializer + */ +#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType)) + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro disable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel)) + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This macro enable specified QEI interrupt. + * \hideinitializer + */ +#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel)) + +/** + * @brief Disable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This macro disable QEI noise filter function. + * \hideinitializer + */ +#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk) + +/** + * @brief Enable QEI noise filter + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32ClkSel The sampling frequency of the noise filter clock. + * - \ref QEI_CTL_NFCLKSEL_DIV1 + * - \ref QEI_CTL_NFCLKSEL_DIV2 + * - \ref QEI_CTL_NFCLKSEL_DIV4 + * - \ref QEI_CTL_NFCLKSEL_DIV16 + * - \ref QEI_CTL_NFCLKSEL_DIV32 + * - \ref QEI_CTL_NFCLKSEL_DIV64 + * @return None + * @details This macro enable QEI noise filter function and select noise filter clock. + * \hideinitializer + */ +#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel)) + +/** + * @brief Get QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter register value. + * @details This macro get QEI pulse counter value. + * \hideinitializer + */ +#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT) + +/** + * @brief Get QEI counting direction + * @param[in] qei The pointer of the specified QEI module. + * @retval 0 QEI counter is in down-counting. + * @retval 1 QEI counter is in up-counting. + * @details This macro get QEI counting direction. + * \hideinitializer + */ +#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0) + +/** + * @brief Get QEI counter hold value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter hold register value. + * @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control. + * \hideinitializer + */ +#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD) + +/** + * @brief Get QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @return QEI pulse counter index latch value + * @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH) + +/** + * @brief Set QEI counter index latch value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Val The latch value. + * @return QEI pulse counter index latch value + * @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected. + * \hideinitializer + */ +#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH = (u32Val)) + +/** + * @brief Get QEI interrupt flag status + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. +* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @retval 0 QEI specified interrupt flag is not set. + * @retval 1 QEI specified interrupt flag is set. + * @details This macro get QEI specified interrupt flag status. + * \hideinitializer + */ +#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0) + + +/** + * @brief Clear QEI interrupt flag + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag + * - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag + * - \ref QEI_STATUS_CMPF_Msk : Compare-match flag + * - \ref QEI_STATUS_IDXF_Msk : Index detected flag + * @return None + * @details This macro clear QEI specified interrupt flag. + * \hideinitializer + */ +#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel)) + +/** + * @brief Set QEI counter compare value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter compare value. + * \hideinitializer + */ +#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value)) + +/** + * @brief Set QEI counter value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter compare value. + * @return None + * @details This macro set QEI pulse counter value. + * \hideinitializer + */ +#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value)) + +/** + * @brief Enable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro enable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type)) + +/** + * @brief Disable QEI counter hold mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Type The triggered type. + * - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control + * - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0 + * - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1 + * - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2 + * - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3 + * @return None + * @details This macro disable QEI counter hold mode. + * \hideinitializer + */ +#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type)) + +/** + * @brief Set QEI maximum count value + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Value The counter maximum value. + * @return QEI maximum count value + * @details This macro set QEI maximum count value. + * \hideinitializer + */ +#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value)) + +/** + * @brief Set QEI counting mode + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @return None + * @details This macro set QEI counting mode. + * \hideinitializer + */ +#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode)) + + +void QEI_Close(QEI_T* qei); +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel); +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value); +void QEI_Start(QEI_T* qei); +void QEI_Stop(QEI_T* qei); + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QEI_H__*/ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/qspi.h b/arch/riscv32/fe310/src/StdDriver/inc/qspi.h new file mode 100644 index 00000000..aeda9da9 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/qspi.h @@ -0,0 +1,367 @@ +/****************************************************************************** + * @file qspi.h + * @version V3.00 + * @brief M2351 series QSPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __QSPI_H__ +#define __QSPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + +/** @addtogroup QSPI_EXPORTED_CONSTANTS QSPI Exported Constants + @{ +*/ + +#define QSPI_MODE_0 (QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define QSPI_MODE_1 (QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_2 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define QSPI_MODE_3 (QSPI_CTL_CLKPOL_Msk | QSPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define QSPI_SLAVE (QSPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define QSPI_MASTER (0x0UL) /*!< Set as master */ + +#define QSPI_SS (QSPI_SSCTL_SS_Msk) /*!< Set SS */ +#define QSPI_SS_ACTIVE_HIGH (QSPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define QSPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* QSPI Interrupt Mask */ +#define QSPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define QSPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define QSPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define QSPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define QSPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define QSPI_SLVTO_INT_MASK (0x020UL) /*!< Slave Mode Time-out interrupt mask */ +#define QSPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define QSPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define QSPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define QSPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define QSPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* QSPI Status Mask */ +#define QSPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define QSPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define QSPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define QSPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define QSPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define QSPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define QSPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define QSPI_SSLINE_STS_MASK (0x80UL) /*!< QSPIx_SS line status mask */ + +/*@}*/ /* end of group QSPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Write 1 to UNITIF bit of QSPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define QSPI_CLR_UNIT_TRANS_INT_FLAG(qspi) ( (qspi)->STATUS = QSPI_STATUS_UNITIF_Msk ) + +/** + * @brief Disable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TWOBIT bit of QSPI_CTL register to disable 2-bit Transfer mode. + */ +#define QSPI_DISABLE_2BIT_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Disable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SLV3WIRE bit of QSPI_SSCTL register to disable Slave 3-wire mode. + */ +#define QSPI_DISABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL &= ~QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Disable Dual I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DUALIOEN bit of QSPI_CTL register to disable Dual I/O mode. + */ +#define QSPI_DISABLE_DUAL_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Disable Quad I/O mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear QUADIOEN bit of QSPI_CTL register to disable Quad I/O mode. + */ +#define QSPI_DISABLE_QUAD_MODE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Enable 2-bit Transfer mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TWOBIT bit of QSPI_CTL register to enable 2-bit Transfer mode. + */ +#define QSPI_ENABLE_2BIT_MODE(qspi) ( (qspi)->CTL |= QSPI_CTL_TWOBIT_Msk ) + +/** + * @brief Enable Slave 3-wire mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SLV3WIRE bit of QSPI_SSCTL register to enable Slave 3-wire mode. + */ +#define QSPI_ENABLE_3WIRE_MODE(qspi) ( (qspi)->SSCTL |= QSPI_SSCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable Dual input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set DUALIOEN bit of QSPI_CTL register to enable Dual input mode. + */ +#define QSPI_ENABLE_DUAL_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_DUALIOEN_Msk ) + +/** + * @brief Enable Dual output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and DUALIOEN bit of QSPI_CTL register to enable Dual output mode. + */ +#define QSPI_ENABLE_DUAL_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_DUALIOEN_Msk) ) + +/** + * @brief Enable Quad input mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear DATDIR bit and set QUADIOEN bit of QSPI_CTL register to enable Quad input mode. + */ +#define QSPI_ENABLE_QUAD_INPUT_MODE(qspi) ( (qspi)->CTL = ((qspi)->CTL & (~QSPI_CTL_DATDIR_Msk)) | QSPI_CTL_QUADIOEN_Msk ) + +/** + * @brief Enable Quad output mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set DATDIR bit and QUADIOEN bit of QSPI_CTL register to enable Quad output mode. + */ +#define QSPI_ENABLE_QUAD_OUTPUT_MODE(qspi) ( (qspi)->CTL |= (QSPI_CTL_DATDIR_Msk | QSPI_CTL_QUADIOEN_Msk) ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set RXPDMAEN bit of QSPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define QSPI_TRIGGER_RX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set TXPDMAEN bit of QSPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define QSPI_TRIGGER_TX_PDMA(qspi) ( (qspi)->PDMACTL |= QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear RXPDMAEN bit of QSPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define QSPI_DISABLE_RX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear TXPDMAEN bit of QSPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define QSPI_DISABLE_TX_PDMA(qspi) ( (qspi)->PDMACTL &= ~QSPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] qspi The pointer of the specified QSPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (QSPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define QSPI_GET_RX_FIFO_COUNT(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXCNT_Msk) >> QSPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of QSPI_STATUS register to get the RX FIFO empty flag. + */ +#define QSPI_GET_RX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_RXEMPTY_Msk) >> QSPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of QSPI_STATUS register to get the TX FIFO empty flag. + */ +#define QSPI_GET_TX_FIFO_EMPTY_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXEMPTY_Msk) >> QSPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of QSPI_STATUS register to get the TX FIFO full flag. + */ +#define QSPI_GET_TX_FIFO_FULL_FLAG(qspi) ( ((qspi)->STATUS & QSPI_STATUS_TXFULL_Msk) >> QSPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Data in RX register. + * @details Read QSPI_RX register to get the received datum. + */ +#define QSPI_READ_RX(qspi) ( (qspi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxData The datum which user attempt to transfer through QSPI bus. + * @return None. + * @details Write u32TxData to QSPI_TX register. + */ +#define QSPI_WRITE_TX(qspi, u32TxData) ( (qspi)->TX = (u32TxData) ) + +/** + * @brief Set QSPIx_SS pin to high state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to high state. + */ +#define QSPI_SET_SS_HIGH(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~QSPI_SSCTL_AUTOSS_Msk)) | (QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk) ) + +/** + * @brief Set QSPIx_SS pin to low state. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Disable automatic slave selection function and set QSPIx_SS pin to low state. + */ +#define QSPI_SET_SS_LOW(qspi) ( (qspi)->SSCTL = ((qspi)->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk))) | QSPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (QSPI_CTL[7:4]). + */ +#define QSPI_ENABLE_BYTE_REORDER(qspi) ( (qspi)->CTL |= QSPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear REORDER bit field of QSPI_CTL register to disable Byte Reorder function. + */ +#define QSPI_DISABLE_BYTE_REORDER(qspi) ( (qspi)->CTL &= ~QSPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one QSPI bus clock cycle). + */ +#define QSPI_SET_SUSPEND_CYCLE(qspi, u32SuspCycle) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << QSPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the QSPI transfer sequence with LSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set LSB bit of QSPI_CTL register to set the QSPI transfer sequence with LSB first. + */ +#define QSPI_SET_LSB_FIRST(qspi) ( (qspi)->CTL |= QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the QSPI transfer sequence with MSB first. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear LSB bit of QSPI_CTL register to set the QSPI transfer sequence with MSB first. + */ +#define QSPI_SET_MSB_FIRST(qspi) ( (qspi)->CTL &= ~QSPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a QSPI transaction. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define QSPI_SET_DATA_WIDTH(qspi, u32Width) ( (qspi)->CTL = ((qspi)->CTL & ~QSPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << QSPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the QSPI busy state. + * @param[in] qspi The pointer of the specified QSPI module. + * @retval 0 QSPI controller is not busy. + * @retval 1 QSPI controller is busy. + * @details This macro will return the busy state of QSPI controller. + */ +#define QSPI_IS_BUSY(qspi) ( ((qspi)->STATUS & QSPI_STATUS_BUSY_Msk) >> QSPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Set SPIEN (QSPI_CTL[0]) to enable QSPI controller. + */ +#define QSPI_ENABLE(qspi) ( (qspi)->CTL |= QSPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None. + * @details Clear SPIEN (QSPI_CTL[0]) to disable QSPI controller. + */ +#define QSPI_DISABLE(qspi) ( (qspi)->CTL &= ~QSPI_CTL_SPIEN_Msk ) + + + +/* Function prototype declaration */ +uint32_t QSPI_Open(QSPI_T *qspi, uint32_t u32MasterSlave, uint32_t u32QSPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void QSPI_Close(QSPI_T *qspi); +void QSPI_ClearRxFIFO(QSPI_T *qspi); +void QSPI_ClearTxFIFO(QSPI_T *qspi); +void QSPI_DisableAutoSS(QSPI_T *qspi); +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock); +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t QSPI_GetBusClock(QSPI_T *qspi); +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask); +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask); +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask); + + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __QSPI_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/rtc.h b/arch/riscv32/fe310/src/StdDriver/inc/rtc.h new file mode 100644 index 00000000..e569ae62 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/rtc.h @@ -0,0 +1,355 @@ +/**************************************************************************//** + * @file rtc.h + * @version V3.00 + * @brief Real Time Clock(RTC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __RTC_H__ +#define __RTC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Initial Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state \hideinitializer */ +#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Time Attribute Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_CLOCK_12 0UL /*!< RTC as 12-hour time scale with AM and PM indication \hideinitializer */ +#define RTC_CLOCK_24 1UL /*!< RTC as 24-hour time scale \hideinitializer */ +#define RTC_AM 1UL /*!< RTC as AM indication \hideinitializer */ +#define RTC_PM 2UL /*!< RTC as PM indication \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Tick Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second \hideinitializer */ +#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second \hideinitializer */ +#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second \hideinitializer */ +#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second \hideinitializer */ +#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second \hideinitializer */ +#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second \hideinitializer */ +#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second \hideinitializer */ +#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Day of Week Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday \hideinitializer */ +#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday \hideinitializer */ +#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday \hideinitializer */ +#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday \hideinitializer */ +#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday \hideinitializer */ +#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday \hideinitializer */ +#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* RTC Miscellaneous Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_YEAR2000 2000UL /*!< RTC Reference for compute year data \hideinitializer */ + +#define RTC_TAMPER0_SELECT (0x1ul << 0) /*!< Select Tamper 0 \hideinitializer */ +#define RTC_TAMPER1_SELECT (0x1ul << 1) /*!< Select Tamper 1 \hideinitializer */ +#define RTC_TAMPER2_SELECT (0x1ul << 2) /*!< Select Tamper 2 \hideinitializer */ +#define RTC_TAMPER3_SELECT (0x1ul << 3) /*!< Select Tamper 3 \hideinitializer */ +#define RTC_TAMPER4_SELECT (0x1ul << 4) /*!< Select Tamper 4 \hideinitializer */ +#define RTC_TAMPER5_SELECT (0x1ul << 5) /*!< Select Tamper 5 \hideinitializer */ +#define MAX_TAMPER_PIN_NUM 6ul /*!< Tamper Pin number \hideinitializer */ + +#define RTC_TAMPER_HIGH_LEVEL_DETECT 1ul /*!< Tamper pin detect voltage level is high \hideinitializer */ +#define RTC_TAMPER_LOW_LEVEL_DETECT 0ul /*!< Tamper pin detect voltage level is low \hideinitializer */ + +#define RTC_TAMPER_DEBOUNCE_ENABLE 1ul /*!< Enable RTC tamper pin de-bounce function \hideinitializer */ +#define RTC_TAMPER_DEBOUNCE_DISABLE 0ul /*!< Disable RTC tamper pin de-bounce function \hideinitializer */ + +#define RTC_PAIR0_SELECT (0x1ul << 0) /*!< Select Pair 0 \hideinitializer */ +#define RTC_PAIR1_SELECT (0x1ul << 1) /*!< Select Pair 1 \hideinitializer */ +#define RTC_PAIR2_SELECT (0x1ul << 2) /*!< Select Pair 2 \hideinitializer */ +#define MAX_PAIR_NUM 3ul /*!< Pair number \hideinitializer */ + +#define RTC_2POW10_CLK (0x0ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles \hideinitializer */ +#define RTC_2POW11_CLK (0x1ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles \hideinitializer */ +#define RTC_2POW12_CLK (0x2ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles \hideinitializer */ +#define RTC_2POW13_CLK (0x3ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles \hideinitializer */ +#define RTC_2POW14_CLK (0x4ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles \hideinitializer */ +#define RTC_2POW15_CLK (0x5ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles \hideinitializer */ +#define RTC_2POW16_CLK (0x6ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles \hideinitializer */ +#define RTC_2POW17_CLK (0x7ul << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles \hideinitializer */ + +#define REF_RANDOM_PATTERN 0x0ul /*!< The new reference pattern is generated by random number generator when the reference pattern run out \hideinitializer */ +#define REF_PREVIOUS_PATTERN 0x1ul /*!< The new reference pattern is repeated previous random value when the reference pattern run out \hideinitializer */ +#define REF_SEED 0x3ul /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out \hideinitializer */ + +/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */ + + +/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs + @{ +*/ +/** + * @details RTC define Time Data Struct + */ +typedef struct +{ + uint32_t u32Year; /*!< Year value */ + uint32_t u32Month; /*!< Month value */ + uint32_t u32Day; /*!< Day value */ + uint32_t u32DayOfWeek; /*!< Day of week value */ + uint32_t u32Hour; /*!< Hour value */ + uint32_t u32Minute; /*!< Minute value */ + uint32_t u32Second; /*!< Second value */ + uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */ + uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */ +} S_RTC_TIME_DATA_T; + +/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */ + + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Indicate is Leap Year or not + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 This year is not a leap year + * @retval 1 This year is a leap year + * + * @details According to current date, return this year is leap year or not. + * \hideinitializer + */ +#define RTC_IS_LEAP_YEAR(rtc) ((rtc)->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0) + +/** + * @brief Clear RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC alarm interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_ALARM_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_ALMIF_Msk) + +/** + * @brief Clear RTC Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to clear RTC tick interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TICK_INT_FLAG(rtc) ((rtc)->INTSTS = RTC_INTSTS_TICKIF_Msk) + +/** + * @brief Clear RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32TamperFlag Tamper interrupt flag. It consists of: \n + * - \ref RTC_INTSTS_TAMP0IF_Msk \n + * - \ref RTC_INTSTS_TAMP1IF_Msk \n + * - \ref RTC_INTSTS_TAMP2IF_Msk \n + * - \ref RTC_INTSTS_TAMP3IF_Msk \n + * - \ref RTC_INTSTS_TAMP4IF_Msk \n + * - \ref RTC_INTSTS_TAMP5IF_Msk + * + * @return None + * + * @details This macro is used to clear RTC tamper pin interrupt flag. + * \hideinitializer + */ +#define RTC_CLEAR_TAMPER_INT_FLAG(rtc, u32TamperFlag) ((rtc)->INTSTS = (u32TamperFlag)) + +/** + * @brief Get RTC Alarm Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC alarm interrupt did not occur + * @retval 1 RTC alarm interrupt occurred + * + * @details This macro indicates RTC alarm interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_ALARM_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0) + +/** + * @brief Get RTC Time Tick Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC time tick interrupt did not occur + * @retval 1 RTC time tick interrupt occurred + * + * @details This macro indicates RTC time tick interrupt occurred or not. + * \hideinitializer + */ +#define RTC_GET_TICK_INT_FLAG(rtc) (((rtc)->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Flag + * + * @param[in] rtc The pointer of RTC module. + * + * @retval 0 RTC tamper event interrupt did not occur + * @retval 1 RTC tamper event interrupt occurred + * + * @details This macro indicates RTC tamper event occurred or not. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_FLAG(rtc) (((rtc)->INTSTS & (0x3F00))? 1:0) + +/** + * @brief Get RTC Tamper Interrupt Status + * + * @param[in] rtc The pointer of RTC module. + * + * @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated + * @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated + * @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated + * @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated + * @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated + * @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated + * + * @details This macro indicates RTC tamper interrupt status. + * \hideinitializer + */ +#define RTC_GET_TAMPER_INT_STATUS(rtc) (((rtc)->INTSTS & (0x3F00))) + +/** + * @brief Enable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to enable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_ENABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN |= RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Disable RTC Tick Wake-up Function + * + * @param[in] rtc The pointer of RTC module. + * + * @return None + * + * @details This macro is used to disable RTC tick interrupt wake-up function. + * \hideinitializer + */ +#define RTC_DISABLE_TICK_WAKEUP(rtc) ((rtc)->INTEN &= ~RTC_INTEN_TICKIEN_Msk); + +/** + * @brief Read Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * + * @return Spare register content + * + * @details Read the specify spare register content. + * @note The returned value is valid only when RWENF (RTC_RWEN[16]) bit is set. \n + * \hideinitializer + */ +#define RTC_READ_SPARE_REGISTER(rtc, u32RegNum) ((rtc)->SPR[(u32RegNum)]) + +/** + * @brief Write Spare Register + * + * @param[in] rtc The pointer of RTC module. + * @param[in] u32RegNum The spare register number, 0~19. + * @param[in] u32RegValue The spare register value. + * + * @return None + * + * @details Write specify data to spare register. + * @note This macro is effect only when RWENF (RTC_RWEN[16]) bit is set. \n + * \hideinitializer + */ +#define RTC_WRITE_SPARE_REGISTER(rtc, u32RegNum, u32RegValue) ((rtc)->SPR[(u32RegNum)] = (u32RegValue)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void RTC_WaitAccessEnable(void); + +/** + * @brief Wait RTC Access Enable + * + * @param None + * + * @return None + * + * @details This function is used to enable the maximum RTC read/write accessible time. + */ +__STATIC_INLINE void RTC_WaitAccessEnable(void) +{ + while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {} +} + +void RTC_Open(S_RTC_TIME_DATA_T *sPt); +void RTC_Close(void); +void RTC_32KCalibration(int32_t i32FrequencyX10000); +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt); +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek); +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day); +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm); +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk); +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk); +uint32_t RTC_GetDayOfWeek(void); +void RTC_SetTickPeriod(uint32_t u32TickSelection); +void RTC_EnableInt(uint32_t u32IntFlagMask); +void RTC_DisableInt(uint32_t u32IntFlagMask); +void RTC_EnableSpareAccess(void); +void RTC_DisableSpareRegister(void); +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn); +void RTC_StaticTamperDisable(uint32_t u32TamperSelect); +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source); +void RTC_DynamicTamperDisable(uint32_t u32PairSel); +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed); + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __RTC_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/sc.h b/arch/riscv32/fe310/src/StdDriver/inc/sc.h new file mode 100644 index 00000000..b9931ccf --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/sc.h @@ -0,0 +1,308 @@ +/**************************************************************************//** + * @file sc.h + * @version V3.00 + * @brief Smartcard(SC) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SC_H__ +#define __SC_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants + @{ +*/ +#define SC_INTERFACE_NUM (3ul) /*!< Smartcard interface numbers \hideinitializer */ +#define SC_PIN_STATE_HIGH (1ul) /*!< Smartcard pin status high \hideinitializer */ +#define SC_PIN_STATE_LOW (0ul) /*!< Smartcard pin status low \hideinitializer */ +#define SC_PIN_STATE_IGNORE (0xFFFFFFFFul) /*!< Ignore pin status \hideinitializer */ +#define SC_CLK_ON (1ul) /*!< Smartcard clock on \hideinitializer */ +#define SC_CLK_OFF (0ul) /*!< Smartcard clock off \hideinitializer */ + +#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!INTEN |= (u32Mask)) + +/** + * @brief This macro disable smartcard interrupt + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt mask to be disabled. A combination of + * - \ref SC_INTEN_ACERRIEN_Msk + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_INITIEN_Msk + * - \ref SC_INTEN_CDIEN_Msk + * - \ref SC_INTEN_BGTIEN_Msk + * - \ref SC_INTEN_TMR2IEN_Msk + * - \ref SC_INTEN_TMR1IEN_Msk + * - \ref SC_INTEN_TMR0IEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt, + * Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt, + * Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief This macro set VCC pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of VCC pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level. + * \hideinitializer + */ +#define SC_SET_VCC_PIN(sc, u32State) \ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\ + }while(0) + + +/** + * @brief This macro turns CLK output on or off + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32OnOff Clock on or off for selected smartcard module, valid values are \ref SC_CLK_ON and \ref SC_CLK_OFF. + * + * @return None + * + * @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not. + * \hideinitializer + */ +#define SC_SET_CLK_PIN(sc, u32OnOff)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32OnOff)\ + (sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\ + else\ + (sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\ + }while(0) + +/** + * @brief This macro set I/O pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of I/O pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low. + * \hideinitializer + */ +#define SC_SET_IO_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\ + }while(0) + +/** + * @brief This macro set RST pin state of smartcard interface + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32State Pin state of RST pin, valid parameters are \ref SC_PIN_STATE_HIGH and \ref SC_PIN_STATE_LOW. + * + * @return None + * + * @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low. + * \hideinitializer + */ +#define SC_SET_RST_PIN(sc, u32State)\ + do {\ + while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\ + if(u32State)\ + (sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\ + else\ + (sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\ + }while(0) + +/** + * @brief This macro read one byte from smartcard module receive FIFO + * + * @param[in] sc The pointer of smartcard module. + * + * @return One byte read from receive FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SC_READ(sc) ((char)((sc)->DAT)) + +/** + * @brief This macro write one byte to smartcard module transmit FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data to write to transmit FIFO. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief This macro set smartcard stop bit length + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Len Stop bit length, ether 1 or 2. + * + * @return None + * + * @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol. + * \hideinitializer + */ +#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count); +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count); + + +/** + * @brief Enable/Disable Tx error retry, and set Tx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Tx error retry count, between 0~8. 0 means disable Tx error retry. + * + * @return None + * + * @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) {} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk; + } +} + +/** + * @brief Enable/Disable Rx error retry, and set Rx error retry count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Count The number of times of Rx error retry count, between 0~8. 0 means disable Rx error retry. + * + * @return None + * + * @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count. + */ +__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count) +{ + while((sc)->CTL & SC_CTL_SYNC_Msk) {} + + /* Retry count must set while enable bit disabled, so disable it first */ + (sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk); + + if((u32Count) != 0UL) + { + while((sc)->CTL & SC_CTL_SYNC_Msk) {} + (sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk; + } +} + + +uint32_t SC_IsCardInserted(SC_T *sc); +void SC_ClearFIFO(SC_T *sc); +void SC_Close(SC_T *sc); +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR); +void SC_ResetReader(SC_T *sc); +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT); +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT); +void SC_StopAllTimer(SC_T *sc); +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount); +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum); +uint32_t SC_GetInterfaceClock(SC_T *sc); + + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SC_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/scu.h b/arch/riscv32/fe310/src/StdDriver/inc/scu.h new file mode 100644 index 00000000..474e08b5 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/scu.h @@ -0,0 +1,371 @@ +/**************************************************************************//** + * @file scu.h + * @version V1.00 + * @brief Secure Configuration Unit Driver Header + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCU_H__ +#define __SCU_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCU_Driver SCU Driver + @{ +*/ + +/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants + @{ +*/ + + + + +/** + * @details Non-secure Attribution Definition. + */ +typedef enum NSATTR +{ + /****** PNNSET0 **********************************************************************************/ + USBH_Attr = 9, + SDH0_Attr = 13, + EBI_Attr = 16, + PDMA1_Attr = 24, + + /****** PNNSET1 **********************************************************************************/ + CRC_Attr = 32 + 17, + CRPT_Attr = 32 + 18, + + /****** PNNSET2 **********************************************************************************/ + RTC_Attr = 64 + 1, + EADC_Attr = 64 + 3, + ACMP01_Attr = 64 + 5, + DAC_Attr = 64 + 7, + I2S0_Attr = 64 + 8, + OTG_Attr = 64 + 13, + TMR23_Attr = 64 + 17, + EPWM0_Attr = 64 + 24, + EPWM1_Attr = 64 + 25, + BPWM0_Attr = 64 + 26, + BPWM1_Attr = 64 + 27, + /****** PNNSET3 **********************************************************************************/ + QSPI0_Attr = 96 + 0, + SPI0_Attr = 96 + 1, + SPI1_Attr = 96 + 2, + SPI2_Attr = 96 + 3, + SPI3_Attr = 96 + 4, + UART0_Attr = 96 + 16, + UART1_Attr = 96 + 17, + UART2_Attr = 96 + 18, + UART3_Attr = 96 + 19, + UART4_Attr = 96 + 20, + UART5_Attr = 96 + 21, + /****** PNNSET4 **********************************************************************************/ + I2C0_Attr = 128 + 0, + I2C1_Attr = 128 + 1, + I2C2_Attr = 128 + 2, + SC0_Attr = 128 + 16, + SC1_Attr = 128 + 17, + SC2_Attr = 128 + 18, + + + /****** PNNSET5 **********************************************************************************/ + CAN0_Attr = 160 + 0, + QEI0_Attr = 160 + 16, + QEI1_Attr = 160 + 17, + ECAP0_Attr = 160 + 20, + ECAP1_Attr = 160 + 21, + TRNG_Attr = 160 + 25, + + /****** PNNSET6 **********************************************************************************/ + USBD_Attr = 192 + 0, + USCI0_Attr = 192 + 16, + USCI1_Attr = 192 + 17 + + +} NSATTR_T; + + +/*@}*/ /* end of group SCU_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCU_EXPORTED_FUNCTIONS SCU Exported Functions + @{ +*/ + +/** + * @brief Set peripheral non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return None + * + * @details This macro is used to set a peripheral to be non-secure peripheral. + * + */ +#define SCU_SET_PNSSET(nsattr) { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); } + +/** + * @brief Get peripheral secure/non-secure attribution + * + * @param[in] nsattr The secure/non-secure attribution of specified module. + The possible value could be refer to \ref NSATTR. + * + * @return The secure/non-secure attribution of specified peripheral. + * @retval 0 The peripheral is secure + * @retval 1 The peripheral is non-secure + * + * @details This macro gets the peripheral secure/non-secure attribution. + */ +#define SCU_GET_PNSSET(nsattr) ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul) + + +/** + * @brief Set secure/non-secure attribution of specified GPIO ports + * + * @param[in] mask The port mask of each GPIO port + * - \ref SCU_IONSSET_PA_Msk + * - \ref SCU_IONSSET_PB_Msk + * - \ref SCU_IONSSET_PC_Msk + * - \ref SCU_IONSSET_PD_Msk + * - \ref SCU_IONSSET_PE_Msk + * - \ref SCU_IONSSET_PF_Msk + * - \ref SCU_IONSSET_PG_Msk + * + * @return None + * + * @details This macro gets the peripheral secure/non-secure attribution. + */ +#define SCU_SET_IONSSET(mask) (SCU->IONSSET |= (mask)) + + +/** + * @brief Get secure/non-secure attribution of specified GPIO ports + * + * @param[in] port The port mask of each GPIO port + * - \ref SCU_IONSSET_PA_Msk + * - \ref SCU_IONSSET_PB_Msk + * - \ref SCU_IONSSET_PC_Msk + * - \ref SCU_IONSSET_PD_Msk + * - \ref SCU_IONSSET_PE_Msk + * - \ref SCU_IONSSET_PF_Msk + * - \ref SCU_IONSSET_PG_Msk + * + * @return The secure/non-secure attribution of specified peripheral. + * @retval 0 The specified IO port is secure + * @retval 1 The specified IO port is non-secure + * + * @details This macro gets GPIO port secure/non-secure attribution. + */ +#define SCU_GET_IONSSET(port) ((SCU->IONSSET&(port))?1:0) + + +/** + * @brief Enable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to enable secure violation interrupt of SCU. + * The secure violation interrupt could be used to detect attack of secure elements. + */ +#define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask)) + + +/** + * @brief Disable sercure violation interrupts + * + * @param[in] mask The mask of each secure violation interrupt source + * - \ref SCU_SVIOIEN_APB0IEN_Msk + * - \ref SCU_SVIOIEN_APB1IEN_Msk + * - \ref SCU_SVIOIEN_GPIOIEN_Msk + * - \ref SCU_SVIOIEN_EBIIEN_Msk + * - \ref SCU_SVIOIEN_USBHIEN_Msk + * - \ref SCU_SVIOIEN_CRCIEN_Msk + * - \ref SCU_SVIOIEN_SDH0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA0IEN_Msk + * - \ref SCU_SVIOIEN_PDMA1IEN_Msk + * - \ref SCU_SVIOIEN_SRAM0IEN_Msk + * - \ref SCU_SVIOIEN_SRAM1IEN_Msk + * - \ref SCU_SVIOIEN_FMCIEN_Msk + * - \ref SCU_SVIOIEN_FLASHIEN_Msk + * - \ref SCU_SVIOIEN_SCUIEN_Msk + * - \ref SCU_SVIOIEN_SYSIEN_Msk + * - \ref SCU_SVIOIEN_CRPTIEN_Msk + * + * @return None + * + * @details This macro is used to disable secure violation interrupt of SCU. + * + */ +#define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask))) + + +/** + * @brief Get secure violation interrupt status + * + * @param mask The interrupt flag mask bit + * + * @return The value of SCU_SVINTSTS register + * + * @details Return interrupt flag of SCU_SVINTSTS register. + * + */ +#define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask)) + +/** + * @brief Clear secure violation interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * - \ref SCU_SVINTSTS_APB0IF_Msk + * - \ref SCU_SVINTSTS_APB1IF_Msk + * - \ref SCU_SVINTSTS_GPIOIF_Msk + * - \ref SCU_SVINTSTS_EBIIF_Msk + * - \ref SCU_SVINTSTS_USBHIF_Msk + * - \ref SCU_SVINTSTS_CRCIF_Msk + * - \ref SCU_SVINTSTS_SDH0IF_Msk + * - \ref SCU_SVINTSTS_PDMA0IF_Msk + * - \ref SCU_SVINTSTS_PDMA1IF_Msk + * - \ref SCU_SVINTSTS_SRAM0IF_Msk + * - \ref SCU_SVINTSTS_SRAM1IF_Msk + * - \ref SCU_SVINTSTS_FMCIF_Msk + * - \ref SCU_SVINTSTS_FLASHIF_Msk + * - \ref SCU_SVINTSTS_SCUIF_Msk + * - \ref SCU_SVINTSTS_SYSIF_Msk + * - \ref SCU_SVINTSTS_CRPTIF_Msk + * + * @return None + * + * @details Clear SCU related interrupt flags specified by flag parameter. + * + */ +#define SCU_CLR_INT_FLAG(flag) (SCU->SVINTSTS = (flag)) + + + +/** + * @brief Control the behavior of non-secure monitor when CPU is in idle state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in idle. + * - true The counter keeps counting when CPU is in idle. + - false The counter will stop when CPU is in idle. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in idle. + * + */ +#define SCU_NSM_IDLE_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk)) + +/** + * @brief Control the behavior of non-secure monitor when CPU is in debug state. + * + * @param[in] opt Option for behavior control of non-secure monitor when CPU in debug. + * - true The counter keeps counting when CPU is in debug. + - false The counter will stop when CPU is in debug. + * + * @return None + * + * @details To control non-secure monitor counter when CPU is in debug. + * + */ +#define SCU_NSM_DBG_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk)) + + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale); +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale); + + +/** + * @brief Config non-secure monitor to detect timeout in non-secure state. + * + * @param[in] u32Ticks A specified period for timeout in non-secure state + * @param[in] u32Prescale A pre-scale divider to non-secure monitor clock + + * + * @return None + * + * @details This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for + * a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the + * non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid + * CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt + * is necessary. + * + */ +__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful); +} + + +/** + * @brief Config non-secure monitor to be a timer. + * + * @param[in] u32Ticks A specified period for timer interrupt. + * @param[in] u32Prescale A pre-scale divider to timer clock source. + + * + * @return None + * + * @details This function is used to configure non-secure monitor as a timer. In other words, the timer counter + * keeps counting even CPU is in secure state. + * + */ +__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale) +{ + + SCU->NSMLOAD = u32Ticks; + SCU->NSMVAL = 0ul; + SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful); +} + + + + +/*@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCU_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCU_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/scuart.h b/arch/riscv32/fe310/src/StdDriver/inc/scuart.h new file mode 100644 index 00000000..58c0d8bd --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/scuart.h @@ -0,0 +1,355 @@ +/**************************************************************************//** + * @file scuart.h + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __SCUART_H__ +#define __SCUART_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants + @{ +*/ +#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */ +#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */ +#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */ +#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */ + +#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */ +#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */ +#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */ + +#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */ +#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */ + +/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */ + + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/* TX Macros */ +/** + * @brief Write Data to Tx data register + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details By writing data to DAT register, the SC will send out an 8-bit data. + * \hideinitializer + */ +#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data)) + +/** + * @brief Get Tx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty + * + * @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high. + * It will be cleared when writing data into DAT (SC_DAT[7:0]). + * \hideinitializer + */ +#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk) + +/** + * @brief Get Tx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk) + +/** + * @brief Wait specified smartcard port transmission complete + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed. + * + * @note This macro blocks until transmit complete. + * \hideinitializer + */ +#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk) + +/** + * @brief Check specified smartcard port transmit FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO full status + * @retval 0 Transmit FIFO is not full + * @retval 1 Transmit FIFO is full + * + * @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not. + * This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port transmission is over + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit complete status + * @retval 0 Transmit is not complete + * @retval 1 Transmit complete + * + * @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not. + * \hideinitializer + */ +#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1) + +/** + * @brief Check specified smartcard port transmit FIFO empty status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Transmit FIFO empty status + * @retval 0 Transmit FIFO is not empty + * @retval 1 Transmit FIFO is empty + * + * @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register. + * \hideinitializer + */ +#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0) + +/** + * @brief Check specified Smartcard port Transmission Status + * + * @param[in] sc The pointer of smartcard module. + * + * @retval 0 Transmit is completed + * @retval 1 Transmit is active + * + * @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted. + * \hideinitializer + */ +#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0) + + +/* RX Macros */ +/** + * @brief Read Rx data register + * + * @param[in] sc The pointer of smartcard module. + * + * @return The oldest data byte in RX FIFO + * + * @details By reading DAT register, the SC will return an 8-bit received data. + * \hideinitializer + */ +#define SCUART_READ(sc) ((sc)->DAT) + +/** + * @brief Get Rx FIFO empty flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO empty status + * @retval 0 Receive FIFO is not empty + * @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty + * + * @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high. + * It will be cleared when SC receives any new data. + * \hideinitializer + */ +#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk) + +/** + * @brief Get Rx FIFO full flag status from register + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval SC_STATUS_TXFULL_Msk Receive FIFO is full + * + * @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk) + +/** + * @brief Check if receive data number in FIFO reach FIFO trigger level or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO data status + * @retval 0 The number of bytes in receive FIFO is less than trigger level + * @retval 1 The number of bytes in receive FIFO equals or larger than trigger level + * + * @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag. + * + * @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO. + * \hideinitializer + */ +#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0) + +/** + * @brief Check specified smartcard port receive FIFO is full or not + * + * @param[in] sc The pointer of smartcard module. + * + * @return Receive FIFO full status + * @retval 0 Receive FIFO is not full + * @retval 1 Receive FIFO is full + * + * @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware. + * \hideinitializer + */ +#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0) + + +/* Interrupt Macros */ +/** + * @brief Enable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to enable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask)) + +/** + * @brief Disable specified interrupts + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Interrupt masks to disable, a combination of following bits, + * - \ref SC_INTEN_RXTOIEN_Msk + * - \ref SC_INTEN_TERRIEN_Msk + * - \ref SC_INTEN_TBEIEN_Msk + * - \ref SC_INTEN_RDAIEN_Msk + * + * @return None + * + * @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt, + * transmit buffer empty interrupt or receive data reach trigger level interrupt. + * \hideinitializer + */ +#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask)) + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to check, could be one of following value + * - \ref SC_INTSTS_RXTOIF_Msk + * - \ref SC_INTSTS_TERRIF_Msk + * - \ref SC_INTSTS_TBEIF_Msk + * - \ref SC_INTSTS_RDAIF_Msk + * + * @return The status of specified interrupt + * @retval 0 Specified interrupt does not happened + * @retval 1 Specified interrupt happened + * + * @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status, + * transmit buffer empty interrupt status or receive data reach interrupt status. + * \hideinitializer + */ +#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0) + +/** + * @brief Clear specified interrupt flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Type Interrupt flag/status to clear, only \ref SC_INTSTS_TERRIF_Msk valid for this macro. + * + * @return None + * + * @details The macro is used to clear transfer error interrupt flag. + * \hideinitializer + */ +#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type)) + +/** + * @brief Get receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Current receive error status, could one of following errors: + * @retval SC_STATUS_PEF_Msk Parity error + * @retval SC_STATUS_FEF_Msk Frame error + * @retval SC_STATUS_BEF_Msk Break error + * + * @details The macro is used to get receiver parity error status, frame error status or break error status. + * \hideinitializer + */ +#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk)) + +/** + * @brief Clear specified receive error flag/status + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Mask Receive error flag/status to clear, combination following values + * - \ref SC_STATUS_PEF_Msk + * - \ref SC_STATUS_FEF_Msk + * - \ref SC_STATUS_BEF_Msk + * + * @return None + * + * @details The macro is used to clear receiver parity error flag, frame error flag or break error flag. + * \hideinitializer + */ +#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask)) + +void SCUART_Close(SC_T* sc); +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate); +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits); +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC); +void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SCUART_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/sdh.h b/arch/riscv32/fe310/src/StdDriver/inc/sdh.h new file mode 100644 index 00000000..48e3514c --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/sdh.h @@ -0,0 +1,201 @@ +/**************************************************************************//** + * @file sdh.h + * @version V1.00 + * @brief M2351 SDH driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SDH_H__ +#define __SDH_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + + +/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants + @{ +*/ + +#define SDH_ERR_ID 0xFFFF0100UL /*!< SDH error ID \hideinitializer */ + +#define SDH_TIMEOUT (SDH_ERR_ID|0x01UL) /*!< Timeout \hideinitializer */ +#define SDH_NO_MEMORY (SDH_ERR_ID|0x02UL) /*!< OOM \hideinitializer */ + +/* -- function return value */ +#define Successful 0U /*!< Success \hideinitializer */ +#define Fail 1U /*!< Failed \hideinitializer */ + +/* --- define type of SD card or MMC */ +#define SDH_TYPE_UNKNOWN 0UL /*!< Unknown card type \hideinitializer */ +#define SDH_TYPE_SD_HIGH 1UL /*!< SDHC card \hideinitializer */ +#define SDH_TYPE_SD_LOW 2UL /*!< SD card \hideinitializer */ +#define SDH_TYPE_MMC 3UL /*!< MMC card \hideinitializer */ +#define SDH_TYPE_EMMC 4UL /*!< eMMC card \hideinitializer */ + +/* SD error */ +#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10UL) /*!< Card removed \hideinitializer */ +#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11UL) /*!< Device error \hideinitializer */ +#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12UL) /*!< Card init timeout \hideinitializer */ +#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13UL) /*!< Card select error \hideinitializer */ +#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14UL) /*!< Card write protect \hideinitializer */ +#define SDH_INIT_ERROR (SDH_ERR_ID|0x15UL) /*!< Card init error \hideinitializer */ +#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16UL) /*!< CRC 7 error \hideinitializer */ +#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17UL) /*!< CRC 16 error \hideinitializer */ +#define SDH_CRC_ERROR (SDH_ERR_ID|0x18UL) /*!< CRC error \hideinitializer */ +#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19UL) /*!< Command 8 error \hideinitializer */ + +#define MMC_FREQ 20000UL /*!< output 20MHz to MMC \hideinitializer */ +#define SD_FREQ 25000UL /*!< output 25MHz to SD \hideinitializer */ +#define SDHC_FREQ 50000UL /*!< output 50MHz to SDH \hideinitializer */ + +#define CardDetect_From_GPIO (1UL << 8) /*!< Card detection pin is GPIO \hideinitializer */ +#define CardDetect_From_DAT3 (1UL << 9) /*!< Card detection pin is DAT3 \hideinitializer */ + +/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */ + +/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines + @{ +*/ +#pragma pack(push) +#pragma pack(1) +typedef struct SDH_info_t +{ + unsigned int CardType; /*!< SDHC, SD, or MMC */ + unsigned int RCA; /*!< Relative card address */ + unsigned char IsCardInsert; /*!< Card insert state */ + unsigned int totalSectorN; /*!< Total sector number */ + unsigned int diskSize; /*!< Disk size in K bytes */ + int sectorSize; /*!< Sector size in bytes */ +} SDH_INFO_T; /*!< Structure holds SD card info */ +#pragma pack(pop) + +/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */ + +/** @cond HIDDEN_SYMBOLS */ +extern SDH_INFO_T SD0; +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +/** + * @brief Enable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / + * \ref SDH_INTEN_WKIEN_Msk + * + * @return None. + * \hideinitializer + */ +#define SDH_ENABLE_INT(sdh, u32IntMask) ((sdh)->INTEN |= (u32IntMask)) + +/** + * @brief Disable specified interrupt. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk / + * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk / + * + * @return None. + * \hideinitializer + */ +#define SDH_DISABLE_INT(sdh, u32IntMask) ((sdh)->INTEN &= ~(u32IntMask)) + +/** + * @brief Get specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / + * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / + * \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk / + * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk / + * \ref SDH_INTSTS_DAT1STS_Msk + * + * + * @return 0 = The specified interrupt is not happened. + * 1 = The specified interrupt is happened. + * \hideinitializer + */ +#define SDH_GET_INT_FLAG(sdh, u32IntMask) (((sdh)->INTSTS & (u32IntMask))?1:0) + + +/** + * @brief Clear specified interrupt flag/status. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32IntMask Interrupt type mask: + * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk / + * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk + * + * + * @return None. + * \hideinitializer + */ +#define SDH_CLR_INT_FLAG(sdh, u32IntMask) ((sdh)->INTSTS = (u32IntMask)) + + +/** + * @brief Check SD Card inserted or removed. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return 1: Card inserted. + * 0: Card removed. + * \hideinitializer + */ +#define SDH_IS_CARD_PRESENT(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.IsCardInsert : 0) + +/** + * @brief Get SD Card capacity. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return SD Card capacity. (unit: KByte) + * \hideinitializer + */ +#define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0) + +extern uint8_t g_u8R3Flag; +extern uint8_t volatile g_u8SDDataReadyFlag; +extern int SDH_ok; + +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); +uint32_t SDH_Probe(SDH_T *sdh); +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount); + +uint32_t SDH_CardDetection(SDH_T *sdh); +void SDH_Open_Disk(SDH_T *sdh, uint32_t u32CardDetSrc); +void SDH_Close_Disk(SDH_T *sdh); + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* end of __SDH_H__ */ +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/spi.h b/arch/riscv32/fe310/src/StdDriver/inc/spi.h new file mode 100644 index 00000000..27141592 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/spi.h @@ -0,0 +1,554 @@ +/****************************************************************************** + * @file spi.h + * @version V3.00 + * @brief M2351 series SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __SPI_H__ +#define __SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + +/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants + @{ +*/ + +#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */ +#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */ +#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */ + +#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */ +#define SPI_MASTER (0x0UL) /*!< Set as master */ + +#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */ +#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */ +#define SPI_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */ + +/* SPI Interrupt Mask */ +#define SPI_UNIT_INT_MASK (0x001UL) /*!< Unit transfer interrupt mask */ +#define SPI_SSACT_INT_MASK (0x002UL) /*!< Slave selection signal active interrupt mask */ +#define SPI_SSINACT_INT_MASK (0x004UL) /*!< Slave selection signal inactive interrupt mask */ +#define SPI_SLVUR_INT_MASK (0x008UL) /*!< Slave under run interrupt mask */ +#define SPI_SLVBE_INT_MASK (0x010UL) /*!< Slave bit count error interrupt mask */ +#define SPI_TXUF_INT_MASK (0x040UL) /*!< Slave TX underflow interrupt mask */ +#define SPI_FIFO_TXTH_INT_MASK (0x080UL) /*!< FIFO TX threshold interrupt mask */ +#define SPI_FIFO_RXTH_INT_MASK (0x100UL) /*!< FIFO RX threshold interrupt mask */ +#define SPI_FIFO_RXOV_INT_MASK (0x200UL) /*!< FIFO RX overrun interrupt mask */ +#define SPI_FIFO_RXTO_INT_MASK (0x400UL) /*!< FIFO RX time-out interrupt mask */ + +/* SPI Status Mask */ +#define SPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define SPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define SPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define SPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define SPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define SPI_TXRX_RESET_MASK (0x20UL) /*!< TX or RX reset status mask */ +#define SPI_SPIEN_STS_MASK (0x40UL) /*!< SPIEN status mask */ +#define SPI_SSLINE_STS_MASK (0x80UL) /*!< SPIx_SS line status mask */ + + +/* I2S Data Width */ +#define SPII2S_DATABIT_8 (0UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */ +#define SPII2S_DATABIT_16 (1UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */ +#define SPII2S_DATABIT_24 (2UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */ +#define SPII2S_DATABIT_32 (3UL << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */ + +/* I2S Audio Format */ +#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */ +#define SPII2S_STEREO (0UL) /*!< Stereo channel */ + +/* I2S Data Format */ +#define SPII2S_FORMAT_I2S (0UL << SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */ +#define SPII2S_FORMAT_MSB (1UL << SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */ +#define SPII2S_FORMAT_PCMA (2UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */ +#define SPII2S_FORMAT_PCMB (3UL << SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */ + +/* I2S Operation mode */ +#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */ +#define SPII2S_MODE_MASTER (0UL) /*!< As master mode */ + +/* I2S TX FIFO Threshold */ +#define SPII2S_FIFO_TX_LEVEL_WORD_0 (0UL) /*!< TX threshold is 0 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */ +#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */ +#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3UL << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */ +/* I2S RX FIFO Threshold */ +#define SPII2S_FIFO_RX_LEVEL_WORD_1 (0UL) /*!< RX threshold is 1 word */ +#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */ +#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3UL << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */ + +/* I2S Record Channel */ +#define SPII2S_MONO_RIGHT (0UL) /*!< Record mono right channel */ +#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */ + +/* I2S Channel */ +#define SPII2S_RIGHT (0UL) /*!< Select right channel */ +#define SPII2S_LEFT (1UL) /*!< Select left channel */ + +/* I2S Interrupt Mask */ +#define SPII2S_FIFO_TXTH_INT_MASK (0x01UL) /*!< TX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXTH_INT_MASK (0x02UL) /*!< RX FIFO threshold interrupt mask */ +#define SPII2S_FIFO_RXOV_INT_MASK (0x04UL) /*!< RX FIFO overrun interrupt mask */ +#define SPII2S_FIFO_RXTO_INT_MASK (0x08UL) /*!< RX FIFO time-out interrupt mask */ +#define SPII2S_TXUF_INT_MASK (0x10UL) /*!< TX FIFO underflow interrupt mask */ +#define SPII2S_RIGHT_ZC_INT_MASK (0x20UL) /*!< Right channel zero cross interrupt mask */ +#define SPII2S_LEFT_ZC_INT_MASK (0x40UL) /*!< Left channel zero cross interrupt mask */ + +/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +/** + * @brief Clear the unit transfer interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag. + */ +#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI_STATUS_UNITIF_Msk ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define SPI_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define SPI_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Get the count of available data in RX FIFO. + * @param[in] spi The pointer of the specified SPI module. + * @return The count of available data in RX FIFO. + * @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO. + */ +#define SPI_GET_RX_FIFO_COUNT(spi) ( ((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos ) + +/** + * @brief Get the RX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 RX FIFO is not empty. + * @retval 1 RX FIFO is empty. + * @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag. + */ +#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk) >> SPI_STATUS_RXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO empty flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not empty. + * @retval 1 TX FIFO is empty. + * @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag. + */ +#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk) >> SPI_STATUS_TXEMPTY_Pos ) + +/** + * @brief Get the TX FIFO full flag. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 TX FIFO is not full. + * @retval 1 TX FIFO is full. + * @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag. + */ +#define SPI_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI_STATUS_TXFULL_Msk) >> SPI_STATUS_TXFULL_Pos ) + +/** + * @brief Get the datum read from RX register. + * @param[in] spi The pointer of the specified SPI module. + * @return Data in RX register. + * @details Read SPI_RX register to get the received datum. + */ +#define SPI_READ_RX(spi) ( (spi)->RX ) + +/** + * @brief Write datum to TX register. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through SPI bus. + * @return None. + * @details Write u32TxData to SPI_TX register. + */ +#define SPI_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) ) + +/** + * @brief Set SPIx_SS pin to high state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to high state. + */ +#define SPI_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk) ) + +/** + * @brief Set SPIx_SS pin to low state. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Disable automatic slave selection function and set SPIx_SS pin to low state. + */ +#define SPI_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk ) + +/** + * @brief Enable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]). + */ +#define SPI_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI_CTL_REORDER_Msk ) + +/** + * @brief Disable Byte Reorder function. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function. + */ +#define SPI_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI_CTL_REORDER_Msk ) + +/** + * @brief Set the length of suspend interval. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15. + * @return None. + * @details Set the length of suspend interval according to u32SuspCycle. + * The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle). + */ +#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos) ) + +/** + * @brief Set the SPI transfer sequence with LSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first. + */ +#define SPI_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI_CTL_LSB_Msk ) + +/** + * @brief Set the SPI transfer sequence with MSB first. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first. + */ +#define SPI_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI_CTL_LSB_Msk ) + +/** + * @brief Set the data width of a SPI transaction. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Width The bit width of one transaction. + * @return None. + * @details The data width can be 8 ~ 32 bits. + */ +#define SPI_SET_DATA_WIDTH(spi, u32Width) ( (spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width) & 0x1F) << SPI_CTL_DWIDTH_Pos) ) + +/** + * @brief Get the SPI busy state. + * @param[in] spi The pointer of the specified SPI module. + * @retval 0 SPI controller is not busy. + * @retval 1 SPI controller is busy. + * @details This macro will return the busy state of SPI controller. + */ +#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk) >> SPI_STATUS_BUSY_Pos ) + +/** + * @brief Enable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Set SPIEN (SPI_CTL[0]) to enable SPI controller. + */ +#define SPI_ENABLE(spi) ( (spi)->CTL |= SPI_CTL_SPIEN_Msk ) + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None. + * @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller. + */ +#define SPI_DISABLE(spi) ( (spi)->CTL &= ~SPI_CTL_SPIEN_Msk ) + +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask); +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch); + +/** + * @brief Enable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Disable zero cross detection function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChMask The mask for left or right channel. Valid values are: + * - \ref SPII2S_RIGHT + * - \ref SPII2S_LEFT + * @return None + * @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function. + */ +__STATIC_INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask) +{ + if(u32ChMask == SPII2S_RIGHT) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk; + } + else + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk; + } +} + +/** + * @brief Enable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA. + */ +#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Disable I2S TX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function. + */ +#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk ) + +/** + * @brief Enable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA. + */ +#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable I2S RX DMA function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function. + */ +#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Enable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function. + */ +#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Disable I2S TX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function. + */ +#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk ) + +/** + * @brief Enable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function. + */ +#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Disable I2S RX function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function. + */ +#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk ) + +/** + * @brief Enable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function. + */ +#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Disable TX Mute function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function. + */ +#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk ) + +/** + * @brief Clear TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk ) + +/** + * @brief Clear RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point. + */ +#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk ) + +/** + * @brief This function sets the recording source channel when mono mode is used. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Ch left or right channel. Valid values are: + * - \ref SPII2S_MONO_LEFT + * - \ref SPII2S_MONO_RIGHT + * @return None + * @details This function selects the recording source channel of monaural mode. + */ +__STATIC_INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch) +{ + u32Ch == SPII2S_MONO_LEFT ? + (i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) : + (i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk); +} + +/** + * @brief Write data to I2S TX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Data The value written to TX FIFO. + * @return None + * @details This macro will write a value to TX FIFO. + */ +#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) ) + +/** + * @brief Read RX FIFO. + * @param[in] i2s The pointer of the specified I2S module. + * @return The value read from RX FIFO. + * @details This function will return a value read from RX FIFO. + */ +#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX ) + +/** + * @brief Get the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return The interrupt flags specified by the u32mask parameter. + * @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter. + */ +#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) ) + +/** + * @brief Clear the interrupt flag. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The mask value for all interrupt flags. + * @return None + * @details This macro will clear the interrupt flags specified by the u32mask parameter. + * @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself. + */ +#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) ) + +/** + * @brief Get transmit FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return TX FIFO level + * @details This macro will return the number of available words in TX FIFO. + */ +#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos ) + +/** + * @brief Get receive FIFO level + * @param[in] i2s The pointer of the specified I2S module. + * @return RX FIFO level + * @details This macro will return the number of available words in RX FIFO. + */ +#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos ) + + + +/* Function prototype declaration */ +uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void SPI_Close(SPI_T *spi); +void SPI_ClearRxFIFO(SPI_T *spi); +void SPI_ClearTxFIFO(SPI_T *spi); +void SPI_DisableAutoSS(SPI_T *spi); +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock); +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold); +uint32_t SPI_GetBusClock(SPI_T *spi); +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask); +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask); +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask); +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask); + +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat); +void SPII2S_Close(SPI_T *i2s); +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask); +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask); +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock); +void SPII2S_DisableMCLK(SPI_T *i2s); +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold); + + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SPI_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/sys.h b/arch/riscv32/fe310/src/StdDriver/inc/sys.h new file mode 100644 index 00000000..d809cf66 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/sys.h @@ -0,0 +1,3096 @@ +/**************************************************************************//** + * @file SYS.h + * @version V3 + * @brief M2351 series System Manager (SYS) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __SYS_H__ +#define __SYS_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + +/** @addtogroup SYS_EXPORTED_CONSTANTS SYS Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Module Reset Control Resister constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define PDMA0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA0RST_Pos) /*!< PDMA0 reset is one of the SYS_ResetModule parameter */ +#define EBI_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_EBIRST_Pos) /*!< EBI reset is one of the SYS_ResetModule parameter */ +#define USBH_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_USBHRST_Pos) /*!< USBH reset is one of the SYS_ResetModule parameter */ +#define SDH0_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_SDH0RST_Pos) /*!< SDH0 reset is one of the SYS_ResetModule parameter */ +#define CRC_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRCRST_Pos) /*!< CRC reset is one of the SYS_ResetModule parameter */ +#define CRPT_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_CRPTRST_Pos) /*!< CRPT reset is one of the SYS_ResetModule parameter */ +#define PDMA1_RST ((0x0UL<<24)|(uint32_t)SYS_IPRST0_PDMA1RST_Pos) /*!< PDMA1 reset is one of the SYS_ResetModule parameter */ + +#define GPIO_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_GPIORST_Pos) /*!< GPIO reset is one of the SYS_ResetModule parameter */ +#define TMR0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR0RST_Pos) /*!< TMR0 reset is one of the SYS_ResetModule parameter */ +#define TMR1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR1RST_Pos) /*!< TMR1 reset is one of the SYS_ResetModule parameter */ +#define TMR2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR2RST_Pos) /*!< TMR2 reset is one of the SYS_ResetModule parameter */ +#define TMR3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TMR3RST_Pos) /*!< TMR3 reset is one of the SYS_ResetModule parameter */ +#define ACMP01_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_ACMP01RST_Pos) /*!< ACMP01 reset is one of the SYS_ResetModule parameter */ +#define I2C0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C0RST_Pos) /*!< I2C0 reset is one of the SYS_ResetModule parameter */ +#define I2C1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C1RST_Pos) /*!< I2C1 reset is one of the SYS_ResetModule parameter */ +#define I2C2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2C2RST_Pos) /*!< I2C2 reset is one of the SYS_ResetModule parameter */ +#define QSPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_QSPI0RST_Pos) /*!< QSPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI0RST_Pos) /*!< SPI0 reset is one of the SYS_ResetModule parameter */ +#define SPI1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI1RST_Pos) /*!< SPI1 reset is one of the SYS_ResetModule parameter */ +#define SPI2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_SPI2RST_Pos) /*!< SPI2 reset is one of the SYS_ResetModule parameter */ +#define UART0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART0RST_Pos) /*!< UART0 reset is one of the SYS_ResetModule parameter */ +#define UART1_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART1RST_Pos) /*!< UART1 reset is one of the SYS_ResetModule parameter */ +#define UART2_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART2RST_Pos) /*!< UART2 reset is one of the SYS_ResetModule parameter */ +#define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */ +#define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */ +#define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */ +#define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */ +#define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */ +#define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ +#define EADC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_EADCRST_Pos) /*!< EADC reset is one of the SYS_ResetModule parameter */ +#define I2S0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_I2S0RST_Pos) /*!< I2S0 reset is one of the SYS_ResetModule parameter */ +#define TRNG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_TRNGRST_Pos) /*!< TRNG reset is one of the SYS_ResetModule parameter */ + +#define SC0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC0RST_Pos) /*!< SC0 reset is one of the SYS_ResetModule parameter */ +#define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */ +#define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */ +#define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ +#define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ +#define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ +#define USCI2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */ +#define DAC_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_DACRST_Pos) /*!< DAC reset is one of the SYS_ResetModule parameter */ +#define EPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM0RST_Pos) /*!< EPWM0 reset is one of the SYS_ResetModule parameter */ +#define EPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_EPWM1RST_Pos) /*!< EPWM1 reset is one of the SYS_ResetModule parameter */ +#define BPWM0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM0RST_Pos) /*!< BPWM0 reset is one of the SYS_ResetModule parameter */ +#define BPWM1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_BPWM1RST_Pos) /*!< BPWM1 reset is one of the SYS_ResetModule parameter */ +#define QEI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI0RST_Pos) /*!< QEI0 reset is one of the SYS_ResetModule parameter */ +#define QEI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_QEI1RST_Pos) /*!< QEI1 reset is one of the SYS_ResetModule parameter */ +#define ECAP0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP0RST_Pos) /*!< ECAP0 reset is one of the SYS_ResetModule parameter */ +#define ECAP1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_ECAP1RST_Pos) /*!< ECAP1 reset is one of the SYS_ResetModule parameter */ + + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brown Out Detector Threshold Voltage Selection constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define SYS_BODCTL_BOD_RST_EN (1UL<GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk)) | SYS_GPA_MFPL_PA0MFP_UART0_RXD; + SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA1MFP_Msk)) | SYS_GPA_MFPL_PA1MFP_UART0_TXD; +*/ + +/* PA.0 MFP */ +#define SYS_GPA_MFPL_PA0MFP_GPIO (0x00UL<BODCTL |= SYS_BODCTL_BODIF_Msk) + +/** + * @brief Set Brown-out detector function to normal mode + * @param None + * @return None + * @details This macro set Brown-out detector to normal mode. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_CLEAR_BOD_LPM() (SYS->BODCTL &= ~SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This macro disable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD() (SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk) + +/** + * @brief Enable Brown-out detector function + * @param None + * @return None + * @details This macro enable Brown-out detector function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD() (SYS->BODCTL |= SYS_BODCTL_BODEN_Msk) + +/** + * @brief Get Brown-out detector interrupt flag + * @param None + * @retval 0 Brown-out detect interrupt flag is not set. + * @retval >=1 Brown-out detect interrupt flag is set. + * @details This macro get Brown-out detector interrupt flag. + */ +#define SYS_GET_BOD_INT_FLAG() (SYS->BODCTL & SYS_BODCTL_BODIF_Msk) + +/** + * @brief Get Brown-out detector status + * @param None + * @retval 0 System voltage is higher than BOD threshold voltage setting or BOD function is disabled. + * @retval >=1 System voltage is lower than BOD threshold voltage setting. + * @details This macro get Brown-out detector output status. + * If the BOD function is disabled, this function always return 0. + */ +#define SYS_GET_BOD_OUTPUT() (SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) + +/** + * @brief Enable Brown-out detector interrupt function + * @param None + * @return None + * @details This macro enable Brown-out detector interrupt function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_BOD_RST() (SYS->BODCTL &= ~SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Enable Brown-out detector reset function + * @param None + * @return None + * @details This macro enable Brown-out detect reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_BOD_RST() (SYS->BODCTL |= SYS_BODCTL_BODRSTEN_Msk) + +/** + * @brief Set Brown-out detector function low power mode + * @param None + * @return None + * @details This macro set Brown-out detector to low power mode. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_SET_BOD_LPM() (SYS->BODCTL |= SYS_BODCTL_BODLPM_Msk) + +/** + * @brief Set Brown-out detector voltage level + * @param[in] u32Level is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_1_6V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_3_0V + * @return None + * @details This macro set Brown-out detector voltage level. + * The write-protection function should be disabled before using this macro. + */ +#define SYS_SET_BOD_LEVEL(u32Level) (SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | (u32Level)) + +/** + * @brief Get reset source is from Brown-out detector reset + * @param None + * @retval 0 Previous reset source is not from Brown-out detector reset + * @retval >=1 Previous reset source is from Brown-out detector reset + * @details This macro get previous reset source is from Brown-out detect reset or not. + */ +#define SYS_IS_BOD_RST() (SYS->RSTSTS & SYS_RSTSTS_BODRF_Msk) + +/** + * @brief Get reset source is from CPU reset + * @param None + * @retval 0 Previous reset source is not from CPU reset + * @retval >=1 Previous reset source is from CPU reset + * @details This macro get previous reset source is from CPU reset. + */ +#define SYS_IS_CPU_RST() (SYS->RSTSTS & SYS_RSTSTS_CPURF_Msk) + +/** + * @brief Get reset source is from LVR Reset + * @param None + * @retval 0 Previous reset source is not from Low-Voltage-Reset + * @retval >=1 Previous reset source is from Low-Voltage-Reset + * @details This macro get previous reset source is from Low-Voltage-Reset. + */ +#define SYS_IS_LVR_RST() (SYS->RSTSTS & SYS_RSTSTS_LVRF_Msk) + +/** + * @brief Get reset source is from Power-on Reset + * @param None + * @retval 0 Previous reset source is not from Power-on Reset + * @retval >=1 Previous reset source is from Power-on Reset + * @details This macro get previous reset source is from Power-on Reset. + */ +#define SYS_IS_POR_RST() (SYS->RSTSTS & SYS_RSTSTS_PORF_Msk) + +/** + * @brief Get reset source is from reset pin reset + * @param None + * @retval 0 Previous reset source is not from reset pin reset + * @retval >=1 Previous reset source is from reset pin reset + * @details This macro get previous reset source is from reset pin reset. + */ +#define SYS_IS_RSTPIN_RST() (SYS->RSTSTS & SYS_RSTSTS_PINRF_Msk) + +/** + * @brief Get reset source is from system reset + * @param None + * @retval 0 Previous reset source is not from system reset + * @retval >=1 Previous reset source is from system reset + * @details This macro get previous reset source is from system reset. + */ +#define SYS_IS_SYSTEM_RST() (SYS->RSTSTS & SYS_RSTSTS_SYSRF_Msk) + +/** + * @brief Get reset source is from window watch dog reset + * @param None + * @retval 0 Previous reset source is not from window watch dog reset + * @retval >=1 Previous reset source is from window watch dog reset + * @details This macro get previous reset source is from window watch dog reset. + */ +#define SYS_IS_WDT_RST() (SYS->RSTSTS & SYS_RSTSTS_WDTRF_Msk) + +/** + * @brief Disable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro disable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_LVR() (SYS->BODCTL &= ~SYS_BODCTL_LVREN_Msk) + +/** + * @brief Enable Low-Voltage-Reset function + * @param None + * @return None + * @details This macro enable Low-Voltage-Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_LVR() (SYS->BODCTL |= SYS_BODCTL_LVREN_Msk) + +/** + * @brief Disable Power-on Reset function + * @param None + * @return None + * @details This macro disable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_DISABLE_POR() (SYS->PORCTL0 = 0x5AA5) + +/** + * @brief Enable Power-on Reset function + * @param None + * @return None + * @details This macro enable Power-on Reset function. + * The register write-protection function should be disabled before using this macro. + */ +#define SYS_ENABLE_POR() (SYS->PORCTL0 = 0) + +/** + * @brief Clear reset source flag + * @param[in] u32RstSrc is reset source. Including : + * - \ref SYS_RSTSTS_PORF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_CPULKRF_Msk + * @return None + * @details This macro clear reset source flag. + */ +#define SYS_CLEAR_RST_SOURCE(u32RstSrc) ((SYS->RSTSTS) = (u32RstSrc) ) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void SYS_UnlockReg(void); +__STATIC_INLINE void SYS_LockReg(void); + + +/** + * @brief Disable register write-protection function + * @param None + * @return None + * @details This function disable register write-protection function. + * To unlock the protected register to allow write access. + */ +__STATIC_INLINE void SYS_UnlockReg(void) +{ + do + { + SYS->REGLCTL = 0x59UL; + SYS->REGLCTL = 0x16UL; + SYS->REGLCTL = 0x88UL; + } + while(SYS->REGLCTL == 0UL); +} + +/** + * @brief Enable register write-protection function + * @param None + * @return None + * @details This function is used to enable register write-protection function. + * To lock the protected register to forbid write access. + */ +__STATIC_INLINE void SYS_LockReg(void) +{ + SYS->REGLCTL = 0UL; +} + + +void SYS_ClearResetSrc(uint32_t u32Src); +uint32_t SYS_GetBODStatus(void); +uint32_t SYS_GetResetSrc(void); +uint32_t SYS_IsRegLocked(void); +uint32_t SYS_ReadPDID(void); +void SYS_ResetChip(void); +void SYS_ResetCPU(void); +void SYS_ResetModule(uint32_t u32ModuleIndex); +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel); +void SYS_DisableBOD(void); +void SYS_SetPowerLevel(uint32_t u32PowerLevel); +uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator); +void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); +void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode); + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __SYS_H__ */ + + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/timer.h b/arch/riscv32/fe310/src/StdDriver/inc/timer.h new file mode 100644 index 00000000..f95039e1 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/timer.h @@ -0,0 +1,507 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer Controller(Timer) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_H__ +#define __TIMER_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode \hideinitializer */ +#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode \hideinitializer */ +#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode \hideinitializer */ +#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx pin \hideinitializer */ +#define TIMER_TOUT_PIN_FROM_TMX_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from TMx_EXT pin \hideinitializer */ + +#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection \hideinitializer */ +#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection \hideinitializer */ +#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value \hideinitializer */ +#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter \hideinitializer */ + +#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event \hideinitializer */ +#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge \hideinitializer */ +#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge \hideinitializer */ + +#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event \hideinitializer */ +#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event \hideinitializer */ +#define TIMER_TRG_TO_EPWM (TIMER_TRGCTL_TRGEPWM_Msk) /*!< Each timer event as EPWM counter clock source \hideinitializer */ +#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion \hideinitializer */ +#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion \hideinitializer */ +#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer \hideinitializer */ + +/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */ + + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Set Timer Compared Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF. + * + * @return None + * + * @details This macro is used to set timer compared value to adjust timer time-out interval. + * @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n + * 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n + * But if timer is operating at other modes, the timer up counter will restart counting and start from 0. + * \hideinitializer + */ +#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value)) + +/** + * @brief Set Timer Prescale Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF. + * + * @return None + * + * @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n + * before it is fed into timer. + * \hideinitializer + */ +#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value)) + +/** + * @brief Check specify Timer Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer 24-bit up counter is inactive + * @retval 1 Timer 24-bit up counter is active + * + * @details This macro is used to check if specify Timer counter is inactive or active. + * \hideinitializer + */ +#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0) + +/** + * @brief Select Toggle-output Pin + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32ToutSel Toggle-output pin selection, valid values are: + * - \ref TIMER_TOUT_PIN_FROM_TMX + * - \ref TIMER_TOUT_PIN_FROM_TMX_EXT + * + * @return None + * + * @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin. + * \hideinitializer + */ +#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel)) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer); +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer); +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer); +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer); +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer); +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer); +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer); + + +/** + * @brief Start Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer counting. + */ +__STATIC_INLINE void TIMER_Start(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop/suspend Timer counting. + */ +__STATIC_INLINE void TIMER_Stop(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_CNTEN_Msk; +} + +/** + * @brief Enable Timer Interrupt Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n + * counter event interrupt or capture trigger interrupt. + * @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC. + */ +__STATIC_INLINE void TIMER_EnableWakeup(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Disable Timer Wake-up Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer interrupt wake-up function. + */ +__STATIC_INLINE void TIMER_DisableWakeup(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_WKEN_Msk; +} + +/** + * @brief Start Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to start Timer capture function. + */ +__STATIC_INLINE void TIMER_StartCapture(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Stop Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to stop Timer capture function. + */ +__STATIC_INLINE void TIMER_StopCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Disable Capture Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of capture pin. + */ +__STATIC_INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk; +} + +/** + * @brief Enable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Disable Counter Pin De-bounce + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the detect de-bounce function of counter pin. + */ +__STATIC_INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk; +} + +/** + * @brief Enable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_EnableInt(TIMER_T *timer) +{ + timer->CTL |= TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Disable Timer Time-out Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer time-out interrupt function. + */ +__STATIC_INLINE void TIMER_DisableInt(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTEN_Msk; +} + +/** + * @brief Enable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_EnableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Disable Capture Trigger Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable the timer capture trigger interrupt function. + */ +__STATIC_INLINE void TIMER_DisableCaptureInt(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk; +} + +/** + * @brief Get Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer time-out interrupt did not occur + * @retval 1 Timer time-out interrupt occurred + * + * @details This function indicates timer time-out interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer) +{ + return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Time-out Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer time-out interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearIntFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TIF_Msk; +} + +/** + * @brief Get Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer capture interrupt did not occur + * @retval 1 Timer capture interrupt occurred + * + * @details This function indicates timer capture trigger interrupt occurred or not. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer) +{ + return timer->EINTSTS; +} + +/** + * @brief Clear Timer Capture Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears timer capture trigger interrupt flag to 0. + */ +__STATIC_INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer) +{ + timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk; +} + +/** + * @brief Get Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer does not cause CPU wake-up + * @retval 1 Timer interrupt event cause CPU wake-up + * + * @details This function indicates timer interrupt event has waked up system or not. + */ +__STATIC_INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer) +{ + return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL); +} + +/** + * @brief Clear Timer Wake-up Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function clears the timer wake-up system flag to 0. + */ +__STATIC_INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer) +{ + timer->INTSTS = TIMER_INTSTS_TWKF_Msk; +} + +/** + * @brief Get Capture value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Capture Value + * + * @details This function reports the current 24-bit timer capture value. + */ +__STATIC_INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer) +{ + return timer->CAP; +} + +/** + * @brief Get Counter value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return 24-bit Counter Value + * + * @details This function reports the current 24-bit timer counter value. + */ +__STATIC_INLINE uint32_t TIMER_GetCounter(TIMER_T *timer) +{ + return timer->CNT; +} + +/** + * @brief Reset Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to reset current counter value and internal prescale counter value. + */ +__STATIC_INLINE void TIMER_ResetCounter(TIMER_T *timer) +{ + timer->CNT = 0UL; + while((timer->CNT & TIMER_CNT_RSTACT_Msk) == TIMER_CNT_RSTACT_Msk) {} +} + + +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq); +void TIMER_Close(TIMER_T *timer); +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec); +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge); +void TIMER_DisableCapture(TIMER_T *timer); +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge); +void TIMER_DisableEventCounter(TIMER_T *timer); +uint32_t TIMER_GetModuleClock(TIMER_T *timer); +void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt); +void TIMER_DisableFreqCounter(TIMER_T *timer); +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src); +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask); + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __TIMER_H__ */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/timer_pwm.h b/arch/riscv32/fe310/src/StdDriver/inc/timer_pwm.h new file mode 100644 index 00000000..bda5cccc --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/timer_pwm.h @@ -0,0 +1,746 @@ +/**************************************************************************//** + * @file timer.h + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __TIMER_PWM_H__ +#define __TIMER_PWM_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Channel Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 \hideinitializer */ +#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Type Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_UP_COUNT (0UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up count type \hideinitializer */ +#define TPWM_DOWN_COUNT (1UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Down count type \hideinitializer */ +#define TPWM_UP_DOWN_COUNT (2UL << TIMER_PWMCTL_CNTTYPE_Pos) /*!< Up-Down count type \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode \hideinitializer */ +#define TPWM_ONE_SHOT_MODE (TIMER_PWMCTL_CNTMODE_Msk) /*!< One-shot mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Output Level Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle \hideinitializer */ +#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing \hideinitializer */ +#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low \hideinitializer */ +#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Trigger ADC Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TRIGGER_ADC_AT_ZERO_POINT (0UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_PERIOD_POINT (1UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT (2UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter zero or period point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT (3UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter up count compare point event occurred \hideinitializer */ +#define TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT (4UL << TIMER_PWMEADCTS_TRGSEL_Pos) /*!< Timer PWM trigger ADC while counter down count compare point event occurred \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Control Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source \hideinitializer */ +#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source \hideinitializer */ + +#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake \hideinitializer */ +#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Load Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */ +#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */ +#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin De-bounce Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */ +#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Brake Pin Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */ +#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */ +#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */ +#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Clock Source Select Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */ +#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Counter Synchronous Mode Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */ +#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Disable PWM Counter Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available. + * @note All registers about PWM counter function will be cleared to 0 after executing this macro. + * \hideinitializer + */ +#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos)) + +/** + * @brief Enable Independent Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1ul << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Enable Complementary Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled. + * \hideinitializer + */ +#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos)) + +/** + * @brief Set Counter Type + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] type Timer PWM count type, could be one of the following type + * - \ref TPWM_UP_COUNT + * - \ref TPWM_DOWN_COUNT + * - \ref TPWM_UP_DOWN_COUNT + * + * @return None + * + * @details This macro is used to set Timer PWM counter type. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (type)) + +/** + * @brief Start PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable PWM generator and start counter counting. + * \hideinitializer + */ +#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk) + +/** + * @brief Stop PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to stop PWM counter after current period is completed. + * \hideinitializer + */ +#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0) + +/** + * @brief Set Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF. + * + * @return None + * + * @details This macro is used to set the prescaler of specified TIMER PWM. + * @note If prescaler is 0, then there is no scaling in counter clock source. + * \hideinitializer + */ +#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler)) + +/** + * @brief Get Counter Clock Prescaler + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0]) + * + * @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1). + * \hideinitializer + */ +#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC) + +/** + * @brief Set Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period)) + +/** + * @brief Get Couner Period + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0]) + * + * @details This macro is used to get the period of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD) + +/** + * @brief Set Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF. + * + * @return None + * + * @details This macro is used to set the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp)) + +/** + * @brief Get Comparator Value + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0]) + * + * @details This macro is used to get the comparator value of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT) + +/** + * @brief Clear Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear counter of specified TIMER PWM. + * \hideinitializer + */ +#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk) + +/** + * @brief Software Trigger Brake Event + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] type Type of brake trigger. Valid values are: + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This macro is used to trigger brake event by writing PWMSWBRK register. + * \hideinitializer + */ +#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel. + * \hideinitializer + */ +#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch)) + +/** + * @brief Set Output Inverse + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Set specified channel output is inversed or not. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @return None + * + * @details This macro is used to enable output inverse of specified output pins. + * @note If u32ChMask parameter is 0, then output inverse function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch)) + +/** + * @brief Enable Output Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] ch Enable specified channel output mask function. Valid values are: + * - \ref TPWM_CH0 + * - \ref TPWM_CH1 + * + * @param[in] level Output to high or low on specified mask channel. + * + * @return None + * + * @details This macro is used to enable output function of specified output pins. + * @note If u32ChMask parameter is 0, then output mask function will be disabled. + * \hideinitializer + */ +#define TPWM_SET_MASK_OUTPUT(timer, ch, level) do {(timer)->PWMMSKEN = (ch); (timer)->PWMMSK = (level); }while(0) + +/** + * @brief Set Counter Synchronous Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @param[in] mode Synchronous mode. Possible options are: + * - \ref TPWM_CNTR_SYNC_DISABLE + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 + * - \ref TPWM_CNTR_SYNC_START_BY_TIMER2 + * - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 + * + * @return None + * + * @details This macro is used to set counter synchronous mode of specified Timer PWM module. + * @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and + * TIMER2~3 PWM counter synchronous by TIMER2 PWM. + * \hideinitializer + */ +#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode)) + +/** + * @brief Trigger Counter Synchronous + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to trigger synchronous event by specified TIMER PWM. + * @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n + * 2. STRGEN (PWMSTRG[0]) is write only and always read as 0. + * \hideinitializer + */ +#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk) + +/** + * @brief Enable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Disable Zero Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the zero event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk) + +/** + * @brief Get Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Zero event interrupt did not occur + * @retval 1 Zero event interrupt occurred + * + * @details This macro indicates zero event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0) + +/** + * @brief Clear Zero Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears zero event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk) + +/** + * @brief Enable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Disable Period Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the period event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk) + +/** + * @brief Get Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Period event interrupt did not occur + * @retval 1 Period event interrupt occurred + * + * @details This macro indicates period event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0) + +/** + * @brief Clear Period Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears period event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk) + +/** + * @brief Enable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Disable Compare Up Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare up event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk) + +/** + * @brief Get Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare up event interrupt did not occur + * @retval 1 Compare up event interrupt occurred + * + * @details This macro indicates compare up event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Up Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare up event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk) + +/** + * @brief Enable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to enable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Disable Compare Down Event Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to disable the compare down event interrupt function. + * \hideinitializer + */ +#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk) + +/** + * @brief Get Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Compare down event interrupt did not occur + * @retval 1 Compare down event interrupt occurred + * + * @details This macro indicates compare down event occurred or not. + * \hideinitializer + */ +#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0) + +/** + * @brief Clear Compare Down Event Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears compare down event interrupt flag. + * \hideinitializer + */ +#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk) + +/** + * @brief Get Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Timer PWM counter never counts to maximum value + * @retval 1 Timer PWM counter counts to maximum value, 0xFFFF + * + * @details This macro indicates Timer PWM counter has count to 0xFFFF or not. + * \hideinitializer + */ +#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0) + +/** + * @brief Clear Counter Reach Maximum Count Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro clears reach maximum count status. + * \hideinitializer + */ +#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk) + +/** + * @brief Get Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @retval 0 Trigger ADC start conversion is not occur + * @retval 1 Specified counter compare event has trigger ADC start conversion + * + * @details This macro is used to indicate PWM counter compare event has triggered ADC start conversion. + * \hideinitializer + */ +#define TPWM_GET_TRG_ADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0) + +/** + * @brief Clear Trigger ADC Status + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to clear PWM counter compare event trigger ADC status. + * \hideinitializer + */ +#define TPWM_CLEAR_TRG_ADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk) + +/** + * @brief Set Brake Event at Brake Pin High or Low-to-High + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * @note The default brake pin detection is high level or from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set Brake Event at Brake Pin Low or High-to-Low + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk) + +/** + * @brief Set External Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] pin The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high. + * \hideinitializer + */ +#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<> 4ul)-2ul) + + +/** + * @brief Calculate UART baudrate mode2 divider + * + * @param[in] u32SrcFreq UART clock frequency + * @param[in] u32BaudRate Baudrate of UART module + * + * @return UART baudrate mode2 divider + * + * @details This macro calculate UART baudrate mode2 divider. + */ +#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2ul)) / (u32BaudRate))-2ul) + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data)) + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module + * + * @return The oldest data byte in RX FIFO. + * + * @details This macro read Rx data register. + */ +#define UART_READ(uart) ((uart)->DAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not empty + * @retval >=1 Tx FIFO is empty + * + * @details This macro get Transmitter FIFO empty register value. + */ +#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not empty + * @retval >=1 Rx FIFO is empty + * + * @details This macro get Receiver FIFO empty register value. + */ +#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified uart port transmission is over. + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. + * It indicates if specified uart port transmission is over nor not. + */ +#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos) + + +/** + * @brief Wait specified uart port transmission is over + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro wait specified uart port transmission is over. + */ +#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)) + + +/** + * @brief Check RX is ready or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 The number of bytes in the RX FIFO is less than the RFITL + * @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL + * + * @details This macro check receive data available interrupt flag is set or not. + */ +#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos) + + +/** + * @brief Check TX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 TX FIFO is full + * @retval 0 TX FIFO is not full + * + * @details This macro check TX FIFO is full or not. + */ +#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos) + + +/** + * @brief Check RX FIFO is full or not + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 1 RX FIFO is full + * @retval 0 RX FIFO is not full + * + * @details This macro check RX FIFO is full or not. + */ +#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Tx FIFO is not full. + * @retval >=1 Tx FIFO is full. + * + * @details This macro get Tx full register value. + */ +#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Rx FIFO is not full. + * @retval >=1 Rx FIFO is full. + * + * @details This macro get Rx full register value. + */ +#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk) + + +/** + * @brief Enable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter empty interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel)) + + +/** + * @brief Disable specified UART interrupt + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntSel Interrupt type select + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details This macro enable specified UART interrupt. + */ +#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel)) + + +/** + * @brief Get specified interrupt flag/status + * + * @param[in] uart The pointer of the specified UART module + * @param[in] u32eIntTypeFlag Interrupt Type Flag, should be + * - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator + * - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag + * - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag + * - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag + * - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag + * - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator + * - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator + * - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator + * - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator + * - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator + * - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator + * - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator + * - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator + * - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag + * - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag + * - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag + * - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag + * - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag + * - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag + * - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag + * - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag + * - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag + * + * @retval 0 The specified interrupt is not happened. + * 1 The specified interrupt is happened. + * + * @details This macro get specified interrupt flag or interrupt indicator status. + */ +#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0) + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +static __INLINE void UART_CLEAR_RTS(UART_T* uart); +static __INLINE void UART_SET_RTS(UART_T* uart); + + +/** + * @brief Set RTS pin to low + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to low. + */ +__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + uart->MODEM &= ~UART_MODEM_RTS_Msk; +} + + +/** + * @brief Set RTS pin to high + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro set RTS pin to high. + */ +__STATIC_INLINE void UART_SET_RTS(UART_T* uart) +{ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk; +} + + +/** + * @brief Clear RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @return None + * + * @details This macro clear RS-485 address byte detection flag. + */ +#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk) + + +/** + * @brief Get RS-485 Address Byte Detection Flag + * + * @param[in] uart The pointer of the specified UART module + * + * @retval 0 Receiver detects a data that is not an address bit. + * @retval 1 Receiver detects a data that is an address bit. + * + * @details This macro get RS-485 address byte detection flag. + */ +#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos) + + + +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Close(UART_T* uart); +void UART_DisableFlowCtrl(UART_T* uart); +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_EnableFlowCtrl(UART_T* uart); +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag); +void UART_Open(UART_T* uart, uint32_t u32baudrate); +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC); +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction); +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr); +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength); +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __UART_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/inc/usbd.h b/arch/riscv32/fe310/src/StdDriver/inc/usbd.h new file mode 100644 index 00000000..c5b7ae4d --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/usbd.h @@ -0,0 +1,735 @@ +/****************************************************************************** + * @file usbd.h + * @version V3.00 + * @brief M2351 series USBD driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved. + ******************************************************************************/ +#ifndef __USBD_H__ +#define __USBD_H__ + +#define SUPPORT_LPM // define to support LPM + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + +/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs + @{ +*/ +typedef struct s_usbd_info +{ + uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */ + uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */ + uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */ + uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */ + uint8_t *gu8BosDesc; /*!< Pointer for USB BOS Descriptor */ + uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */ + uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */ + +} S_USBD_INFO_T; /*!< Device description structure */ + +extern const S_USBD_INFO_T gsInfo; + +/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */ + + + + +/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants + @{ +*/ +#define USBD_BUF_BASE (uint32_t)(((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_BASE+NS_OFFSET+0x100UL):(USBD_BASE+0x100UL)) /*!< USBD buffer base address */ +#define USBD_MAX_EP 12UL /*!< Total EP number */ + +#define EP0 0UL /*!< Endpoint 0 */ +#define EP1 1UL /*!< Endpoint 1 */ +#define EP2 2UL /*!< Endpoint 2 */ +#define EP3 3UL /*!< Endpoint 3 */ +#define EP4 4UL /*!< Endpoint 4 */ +#define EP5 5UL /*!< Endpoint 5 */ +#define EP6 6UL /*!< Endpoint 6 */ +#define EP7 7UL /*!< Endpoint 7 */ +#define EP8 8UL /*!< Endpoint 8 */ +#define EP9 9UL /*!< Endpoint 9 */ +#define EP10 10UL /*!< Endpoint 10 */ +#define EP11 11UL /*!< Endpoint 11 */ + +/** @cond HIDDEN_SYMBOLS */ +/* USB Request Type */ +#define REQ_STANDARD 0x00UL +#define REQ_CLASS 0x20UL +#define REQ_VENDOR 0x40UL + +/* USB Standard Request */ +#define GET_STATUS 0x00UL +#define CLEAR_FEATURE 0x01UL +#define SET_FEATURE 0x03UL +#define SET_ADDRESS 0x05UL +#define GET_DESCRIPTOR 0x06UL +#define SET_DESCRIPTOR 0x07UL +#define GET_CONFIGURATION 0x08UL +#define SET_CONFIGURATION 0x09UL +#define GET_INTERFACE 0x0AUL +#define SET_INTERFACE 0x0BUL +#define SYNC_FRAME 0x0CUL + +/* USB Descriptor Type */ +#define DESC_DEVICE 0x01UL +#define DESC_CONFIG 0x02UL +#define DESC_STRING 0x03UL +#define DESC_INTERFACE 0x04UL +#define DESC_ENDPOINT 0x05UL +#define DESC_QUALIFIER 0x06UL +#define DESC_OTHERSPEED 0x07UL +#define DESC_IFPOWER 0x08UL +#define DESC_OTG 0x09UL +#define DESC_BOS 0x0FUL +#define DESC_CAPABILITY 0x10UL + +/* USB Device Capability Type */ +#define CAP_WIRELESS 0x01UL +#define CAP_USB20_EXT 0x02UL + +/*! b, then return a. Otherwise, return b. + */ +#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b)) + + +/** + * @brief Compare two input numbers and return minimum one + * + * @param[in] a First number to be compared + * @param[in] b Second number to be compared + * + * @return Minimum value between a and b + * + * @details If a < b, then return a. Otherwise, return b. + */ +#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b)) + + +/** + * @brief Enable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB and PHY. + * + */ +#define USBD_ENABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= 0x7D0)):((uint32_t)(USBD->ATTR |= 0x7D0))) + +/** + * @brief Disable USB + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB. + * + */ +#define USBD_DISABLE_USB() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN)):((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))) + +/** + * @brief Enable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to enable USB PHY. + * + */ +#define USBD_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN)):((uint32_t)(USBD->ATTR |= USBD_PHY_EN))) + +/** + * @brief Disable USB PHY + * + * @param None + * + * @return None + * + * @details To set USB ATTR control register to disable USB PHY. + * + */ +#define USBD_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN)):((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))) + +/** + * @brief Enable SE0. Force USB PHY transceiver to drive SE0. + * + * @param None + * + * @return None + * + * @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus. + * + */ +#define USBD_SET_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0)):((uint32_t)(USBD->SE0 |= USBD_DRVSE0))) + +/** + * @brief Disable SE0 + * + * @param None + * + * @return None + * + * @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function. + * + */ +#define USBD_CLR_SE0() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0)):((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))) + +/** + * @brief Set USB device address + * + * @param[in] addr The USB device address. + * + * @return None + * + * @details Write USB device address to USB_FADDR register. + * + */ +#define USBD_SET_ADDR(addr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->FADDR = (addr)):(USBD->FADDR = (addr))) + +/** + * @brief Get USB device address + * + * @param None + * + * @return USB device address + * + * @details Read USB_FADDR register to get USB device address. + * + */ +#define USBD_GET_ADDR() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->FADDR)):((uint32_t)(USBD->FADDR))) + +/** + * @brief Enable USB interrupt function + * + * @param[in] intr The combination of the specified interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. + * (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS) + * + * @return None + * + * @details Enable USB related interrupt functions specified by intr parameter. + * + */ +#define USBD_ENABLE_INT(intr) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTEN |= (intr)):(USBD->INTEN |= (intr))) + +/** + * @brief Get interrupt status + * + * @param None + * + * @return The value of USB_INTSTS register + * + * @details Return all interrupt flags of USB_INTSTS register. + * + */ +#define USBD_GET_INT_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->INTSTS)):((uint32_t)(USBD->INTSTS))) + +/** + * @brief Clear USB interrupt flag + * + * @param[in] flag The combination of the specified interrupt flags. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. + * (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB) + * + * @return None + * + * @details Clear USB related interrupt flags specified by flag parameter. + * + */ +#define USBD_CLR_INT_FLAG(flag) (((__PC() & NS_OFFSET) == NS_OFFSET)? (USBD_NS->INTSTS = (flag)):(USBD->INTSTS = (flag))) + +/** + * @brief Get endpoint status + * + * @param None + * + * @return The value of USB_EPSTS register. + * + * @details Return all endpoint status. + * + */ +#define USBD_GET_EP_FLAG() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->EPSTS)):((uint32_t)(USBD->EPSTS))) + +/** + * @brief Get USB bus state + * + * @param None + * + * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0]. + * Bit 0 indicates USB bus reset status. + * Bit 1 indicates USB bus suspend status. + * Bit 2 indicates USB bus resume status. + * Bit 3 indicates USB bus time-out status. + * Bit 12 indicates USB bus LPM L1 suspend status. + * Bit 13 indicates USB bus LPM L1 resume status. + * + * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events. + * + */ +#define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F))) + +/** + * @brief Check cable connection state + * + * @param None + * + * @retval 0 USB cable is not attached. + * @retval 1 USB cable is attached. + * + * @details Check the connection state by FLDET bit of USB_FLDET register. + * + */ +#define USBD_IS_ATTACHED() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk)):((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))) + +/** + * @brief Stop USB transaction of the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID. + * + */ +#define USBD_STOP_TRANSACTION(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)) + +/** + * @brief Set USB DATA1 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA1(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)) + +/** + * @brief Set USB DATA0 PID for the specified endpoint ID + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction. + * Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions. + * + */ +#define USBD_SET_DATA0(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))) + +/** + * @brief Set USB payload size (IN data) + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] size The transfer length. + * + * @return None + * + * @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction. + * + */ +#define USBD_SET_PAYLOAD_LEN(ep, size) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))) + +/** + * @brief Get USB payload size (OUT data) + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The value of USB_MXPLDx register. + * + * @details Get the data length of OUT data transaction by reading USB_MXPLDx register. + * + */ +#define USBD_GET_PAYLOAD_LEN(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))) + +/** + * @brief Configure endpoint + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] config The USB configuration. + * + * @return None + * + * @details This macro will write config parameter to USB_CFGx register of specified endpoint ID. + * + */ +#define USBD_CONFIG_EP(ep, config) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))) + +/** + * @brief Set USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @param[in] offset The SRAM offset. + * + * @return None + * + * @details This macro will set the SRAM offset for the specified endpoint ID. + * + */ +#define USBD_SET_EP_BUF_ADDR(ep, offset) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset)):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))) + +/** + * @brief Get the offset of the specified USB endpoint buffer + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return The offset of the specified endpoint buffer. + * + * @details This macro will return the SRAM offset of the specified endpoint ID. + * + */ +#define USBD_GET_EP_BUF_ADDR(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4)))):((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))) + +/** + * @brief Set USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically. + * + */ +#define USBD_SET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @return None + * + * @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token. + */ +#define USBD_CLR_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)) + +/** + * @brief Get USB endpoint stall state + * + * @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11. + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state of the specified endpoint ID. + * + */ +#define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)) + +/** + * @brief To support byte access between USB SRAM and system SRAM + * + * @param[in] dest Destination pointer. + * + * @param[in] src Source pointer. + * + * @param[in] size Byte count. + * + * @return None + * + * @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter. + * + */ +__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) +{ + uint32_t volatile i = 0UL; + + while(size--) + { + dest[i] = src[i]; + i++; + } +} + + +/** + * @brief Set USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Set USB endpoint stall state. Endpoint will respond STALL token automatically. + * + */ +__STATIC_INLINE void USBD_SetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + USBD_T *pUSBD; + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Clear USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @return None + * + * @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token. + */ +__STATIC_INLINE void USBD_ClearStall(uint8_t epnum) +{ + uint32_t u32CfgAddr; + uint32_t u32Cfg; + uint32_t i; + + USBD_T *pUSBD; + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + *((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL); + break; + } + } +} + +/** + * @brief Get USB endpoint stall state + * + * @param[in] epnum USB endpoint number + * + * @retval 0 USB endpoint is not stalled. + * @retval Others USB endpoint is stalled. + * + * @details Get USB endpoint stall state. + * + */ +__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) +{ + uint32_t u32CfgAddr = 0UL; + uint32_t u32Cfg; + uint32_t i; + + USBD_T *pUSBD; + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + for(i = 0UL; i < USBD_MAX_EP; i++) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFG; /* USBD_CFG0 */ + u32Cfg = *((__IO uint32_t *)(u32CfgAddr)); + + if((u32Cfg & 0xFUL) == epnum) + { + u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&pUSBD->EP[0].CFGP; /* USBD_CFGP0 */ + break; + } + } + + return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); +} + +extern volatile uint8_t g_USBD_u8RemoteWakeupEn; +extern uint8_t g_USBD_au8SetupPacket[8]; + + +typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ +typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */ +typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ +typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ + +extern const S_USBD_INFO_T *g_USBD_sInfo; /*!< A pointer for USB information structure */ +extern VENDOR_REQ g_USBD_pfnVendorRequest; /*!< USB Vendor Request Functional Pointer */ +extern CLASS_REQ g_USBD_pfnClassRequest; /*!< USB Class Request Functional Pointer */ +extern SET_INTERFACE_REQ g_USBD_pfnSetInterface; /*!< USB Set Interface Functional Pointer */ +extern SET_CONFIG_CB g_USBD_pfnSetConfigCallback; /*!< USB Set configuration callback function pointer */ +extern uint32_t g_USBD_u32EpStallLock; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/*--------------------------------------------------------------------*/ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); +void USBD_Start(void); +void USBD_GetSetupPacket(uint8_t *buf); +void USBD_ProcessSetupPacket(void); +void USBD_StandardRequest(void); +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size); +void USBD_CtrlIn(void); +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size); +void USBD_CtrlOut(void); +void USBD_SwReset(void); +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq); +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback); +void USBD_LockEpStall(uint32_t u32EpBitmap); + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USBD_H__ */ + +/*** (C) COPYRIGHT 2018-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/usci_i2c.h b/arch/riscv32/fe310/src/StdDriver/inc/usci_i2c.h new file mode 100644 index 00000000..58c45cd0 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/usci_i2c.h @@ -0,0 +1,321 @@ +/**************************************************************************//** + * @file USCI_I2C.h + * @version V3.0 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2351 series USCI I2C(UI2C) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ +#ifndef __USCI_I2C_H__ +#define __USCI_I2C_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + +/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C master event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_MASTER_EVENT +{ + MASTER_SEND_ADDRESS = 10u, /*!< Master send address to Slave */ + MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */ + MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */ + MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */ + MASTER_SEND_DATA, /*!< Master Send Data to Slave */ + MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */ + MASTER_READ_DATA, /*!< Master Get Data from Slave */ + MASTER_STOP, /*!< Master send stop to Slave */ + MASTER_SEND_START /*!< Master send start to Slave */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C slave event definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +enum UI2C_SLAVE_EVENT +{ + SLAVE_ADDRESS_ACK = 100u, /*!< Slave send address ACK */ + SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */ + SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */ + SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */ + SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */ + SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */ +}; + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_CTL constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_CTL_PTRG (0x20U) /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */ +#define UI2C_CTL_STA (0x08U) /*!< USCI_CTL setting for I2C control bits. It would set STA bit */ +#define UI2C_CTL_STO (0x04U) /*!< USCI_CTL setting for I2C control bits. It would set STO bit */ +#define UI2C_CTL_AA (0x02U) /*!< USCI_CTL setting for I2C control bits. It would set AA bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C GCMode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_GCMODE_ENABLE (1U) /*!< Enable USCI_I2C GC Mode */ +#define UI2C_GCMODE_DISABLE (0U) /*!< Disable USCI_I2C GC Mode */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C Wakeup Mode constant definitions. */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_DATA_TOGGLE_WK (0x0U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle */ +#define UI2C_ADDR_MATCH_WK (0x1U << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI_I2C interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UI2C_TO_INT_MASK (0x001U) /*!< Time-out interrupt mask */ +#define UI2C_STAR_INT_MASK (0x002U) /*!< Start condition received interrupt mask */ +#define UI2C_STOR_INT_MASK (0x004U) /*!< Stop condition received interrupt mask */ +#define UI2C_NACK_INT_MASK (0x008U) /*!< Non-acknowledge interrupt mask */ +#define UI2C_ARBLO_INT_MASK (0x010U) /*!< Arbitration lost interrupt mask */ +#define UI2C_ERR_INT_MASK (0x020U) /*!< Error interrupt mask */ +#define UI2C_ACK_INT_MASK (0x040U) /*!< Acknowledge interrupt mask */ + +/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This macro sets the USCI_I2C protocol control register at one time + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Ctrl Set the register value of USCI_I2C control register. + * + * @return None + * + * @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, PTRG, ACK. + */ +#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2EU) | (u8Ctrl)) + +/** + * @brief This macro only set START bit to protocol control register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register. + */ +#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk) + +/** + * @brief This macro only set STOP bit to the control register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register. + */ +#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk)) + +/** + * @brief This macro returns the data stored in data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Data + * + * @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus + */ +#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT) + +/** + * @brief This macro writes the data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus + */ +#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data)) + +/** + * @brief This macro returns time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 USCI_I2C bus time-out is not happened + * @retval 1 USCI_I2C bus time-out is happened + * + * @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared. + */ +#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0) + +/** + * @brief This macro returns wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @retval 0 Chip is not woken-up from power-down mode + * @retval 1 Chip is woken-up from power-down mode + * + * @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep. + */ +#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0) + +/** + * @brief This macro is used to clear USCI_I2C wake-up flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details If USCI_I2C wake-up flag is set, use this macro to clear it. + */ +#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk) + +/** + * @brief This macro disables the USCI_I2C 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function. + */ +#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk)) + +/** + * @brief This macro enables the 10-bit address mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To enable USCI_I2C 10-bit address match function. + */ +#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk) + +/** + * @brief This macro gets USCI_I2C protocol interrupt flag or bus status + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return A word data of USCI_I2C_PROTSTS register + * + * @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status. + */ +#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS) + +/** + * @brief This macro clears specified protocol interrupt flag + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UI2C_PROTSTS_ACKIF_Msk + * - \ref UI2C_PROTSTS_ERRIF_Msk + * - \ref UI2C_PROTSTS_ARBLOIF_Msk + * - \ref UI2C_PROTSTS_NACKIF_Msk + * - \ref UI2C_PROTSTS_STORIF_Msk + * - \ref UI2C_PROTSTS_STARIF_Msk + * - \ref UI2C_PROTSTS_TOIF_Msk + * @return None + * + * @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag. + */ +#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag)) + +/** + * @brief This macro enables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function. + */ +#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel)) + +/** + * @brief This macro disables specified protocol interrupt + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref UI2C_PROTIEN_ACKIEN_Msk + * - \ref UI2C_PROTIEN_ERRIEN_Msk + * - \ref UI2C_PROTIEN_ARBLOIEN_Msk + * - \ref UI2C_PROTIEN_NACKIEN_Msk + * - \ref UI2C_PROTIEN_STORIEN_Msk + * - \ref UI2C_PROTIEN_STARIEN_Msk + * - \ref UI2C_PROTIEN_TOIEN_Msk + * @return None + * + * @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion. + */ +#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel)) + + +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock); +void UI2C_Close(UI2C_T *ui2c); +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c); +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack); +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask); +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c); +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock); +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask); +void UI2C_ClearIntFlag(UI2C_T* ui2c, uint32_t u32Mask); +uint32_t UI2C_GetData(UI2C_T *ui2c); +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data); +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode); +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask); +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt); +void UI2C_DisableTimeout(UI2C_T *ui2c); +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode); +void UI2C_DisableWakeup(UI2C_T *ui2c); +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr); +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/usci_spi.h b/arch/riscv32/fe310/src/StdDriver/inc/usci_spi.h new file mode 100644 index 00000000..df54f9db --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/usci_spi.h @@ -0,0 +1,406 @@ +/****************************************************************************//** + * @file usci_spi.h + * @version V3.00 + * @brief M2351 series USCI_SPI driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_SPI_H__ +#define __USCI_SPI_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + +/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants + @{ +*/ + +#define USPI_MODE_0 (0x0UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */ +#define USPI_MODE_1 (0x1UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_2 (0x2UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */ +#define USPI_MODE_3 (0x3UL << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */ + +#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave */ +#define USPI_MASTER (0x0UL) /*!< Set as master */ + +#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS */ +#define USPI_SS_ACTIVE_HIGH (0x0UL) /*!< SS active high */ +#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low */ + +/* USCI_SPI Interrupt Mask */ +#define USPI_SSINACT_INT_MASK (0x001UL) /*!< Slave Slave Inactive interrupt mask */ +#define USPI_SSACT_INT_MASK (0x002UL) /*!< Slave Slave Active interrupt mask */ +#define USPI_SLVTO_INT_MASK (0x004UL) /*!< Slave Mode Time-out interrupt mask */ +#define USPI_SLVBE_INT_MASK (0x008UL) /*!< Slave Mode Bit Count Error interrupt mask */ +#define USPI_TXUDR_INT_MASK (0x010UL) /*!< Slave Transmit Under Run interrupt mask */ +#define USPI_RXOV_INT_MASK (0x020UL) /*!< Receive Buffer Overrun interrupt mask */ +#define USPI_TXST_INT_MASK (0x040UL) /*!< Transmit Start interrupt mask */ +#define USPI_TXEND_INT_MASK (0x080UL) /*!< Transmit End interrupt mask */ +#define USPI_RXST_INT_MASK (0x100UL) /*!< Receive Start interrupt mask */ +#define USPI_RXEND_INT_MASK (0x200UL) /*!< Receive End interrupt mask */ + +/* USCI_SPI Status Mask */ +#define USPI_BUSY_MASK (0x01UL) /*!< Busy status mask */ +#define USPI_RX_EMPTY_MASK (0x02UL) /*!< RX empty status mask */ +#define USPI_RX_FULL_MASK (0x04UL) /*!< RX full status mask */ +#define USPI_TX_EMPTY_MASK (0x08UL) /*!< TX empty status mask */ +#define USPI_TX_FULL_MASK (0x10UL) /*!< TX full status mask */ +#define USPI_SSLINE_STS_MASK (0x20UL) /*!< USCI_SPI_SS line status mask */ + +/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief Disable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Enable slave 3-wire mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk ) + +/** + * @brief Get the Rx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Rx buffer flag + * @retval 0: Rx buffer is not empty + * @retval 1: Rx buffer is empty + * \hideinitializer + */ +#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer empty flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not empty + * @retval 1: Tx buffer is empty + * \hideinitializer + */ +#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 ) + +/** + * @brief Get the Tx buffer full flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Tx buffer flag + * @retval 0: Tx buffer is not full + * @retval 1: Tx buffer is full + * \hideinitializer + */ +#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 ) + +/** + * @brief Get the datum read from RX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return data in Rx register + * \hideinitializer + */ +#define USPI_READ_RX(uspi) ( (uspi)->RXDAT ) + +/** + * @brief Write datum to TX register. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus. + * @return None + * \hideinitializer + */ +#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = (u32TxData) ) + +/** + * @brief Set USCI_SPI_SS pin to high state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_HIGH(uspi) \ + do{ \ + (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set USCI_SPI_SS pin to low state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode. + * \hideinitializer + */ +#define USPI_SET_SS_LOW(uspi) \ + do{ \ + (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \ + (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ + }while(0) + +/** + * @brief Set the length of suspend interval. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SuspCycle Decide the length of suspend interval. + * @return None + * \hideinitializer + */ +#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | ((u32SuspCycle) << USPI_PROTCTL_SUSPITV_Pos) ) + +/** + * @brief Set the USCI_SPI transfer sequence with LSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the USCI_SPI transfer sequence with MSB first. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk ) + +/** + * @brief Set the data width of a USCI_SPI transaction. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Width The data width + * @return None + * \hideinitializer + */ +#define USPI_SET_DATA_WIDTH(uspi, u32Width) \ + do{ \ + if((u32Width) == 16ul){ \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (0 << USPI_LINECTL_DWIDTH_Pos); \ + }else { \ + (uspi)->LINECTL = ((uspi)->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | ((u32Width) << USPI_LINECTL_DWIDTH_Pos); \ + } \ + }while(0) + +/** + * @brief Get the USCI_SPI busy state. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return USCI_SPI busy status + * @retval 0: USCI_SPI module is not busy + * @retval 1: USCI_SPI module is busy + * \hideinitializer + */ +#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 ) + +/** + * @brief Get the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Wakeup status. + * @retval 0 Flag is not set. + * @retval 1 Flag is set. + * \hideinitializer + */ +#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0 ) + +/** + * @brief Clear the USCI_SPI wakeup flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + * \hideinitializer + */ +#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk ) + +/** + * @brief Get protocol interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of protocol status register. + * \hideinitializer + */ +#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS ) + +/** + * @brief Clear specified protocol interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_PROTSTS_SSACTIF_Msk + * - \ref USPI_PROTSTS_SSINAIF_Msk + * - \ref USPI_PROTSTS_SLVBEIF_Msk + * - \ref USPI_PROTSTS_SLVTOIF_Msk + * - \ref USPI_PROTSTS_RXENDIF_Msk + * - \ref USPI_PROTSTS_RXSTIF_Msk + * - \ref USPI_PROTSTS_TXENDIF_Msk + * - \ref USPI_PROTSTS_TXSTIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_PROT_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->PROTSTS = (u32IntTypeFlag) ) + +/** + * @brief Get buffer interrupt flag/status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return The interrupt flag/status of buffer status register. + * \hideinitializer + */ +#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS ) + +/** + * @brief Clear specified buffer interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref USPI_BUFSTS_TXUDRIF_Msk + * - \ref USPI_BUFSTS_RXOVIF_Msk + * @return None + * \hideinitializer + */ +#define USPI_CLR_BUF_INT_FLAG(uspi, u32IntTypeFlag) ( (uspi)->BUFSTS = (u32IntTypeFlag) ) + +/** + * @brief Enable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN |= (u32IntSel) ) + +/** + * @brief Disable specified protocol interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_PROTIEN_SLVBEIEN_Msk + * - \ref USPI_PROTIEN_SLVTOIEN_Msk + * - \ref USPI_PROTIEN_SSACTIEN_Msk + * - \ref USPI_PROTIEN_SSINAIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ( (uspi)->PROTIEN &= ~ (u32IntSel) ) + +/** + * @brief Enable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL |= (u32IntSel) ) + +/** + * @brief Disable specified buffer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_BUFCTL_RXOVIEN_Msk + * - \ref USPI_BUFCTL_TXUDRIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ( (uspi)->BUFCTL &= ~ (u32IntSel) ) + +/** + * @brief Enable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN |= (u32IntSel) ) + +/** + * @brief Disable specified transfer interrupt. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32IntSel Interrupt Type, should be + * - \ref USPI_INTEN_RXENDIEN_Msk + * - \ref USPI_INTEN_RXSTIEN_Msk + * - \ref USPI_INTEN_TXENDIEN_Msk + * - \ref USPI_INTEN_TXSTIEN_Msk + * @return None + * \hideinitializer + */ +#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ( (uspi)->INTEN &= ~ (u32IntSel) ) + +/** + * @brief Trigger RX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function. + */ +#define USPI_TRIGGER_RX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Trigger TX PDMA function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function. + */ +#define USPI_TRIGGER_TX_PDMA(uspi) ( (uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk | USPI_PDMACTL_PDMAEN_Msk ) + +/** + * @brief Disable RX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function. + */ +#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk ) + +/** + * @brief Disable TX PDMA transfer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None. + * @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function. + */ +#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk ) + +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock); +void USPI_Close(USPI_T *uspi); +void USPI_ClearRxBuf(USPI_T *uspi); +void USPI_ClearTxBuf(USPI_T *uspi); +void USPI_DisableAutoSS(USPI_T *uspi); +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel); +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock); +uint32_t USPI_GetBusClock(USPI_T *uspi); +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask); +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask); +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask); +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask); +void USPI_EnableWakeup(USPI_T *uspi); +void USPI_DisableWakeup(USPI_T *uspi); + + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_SPI_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/usci_uart.h b/arch/riscv32/fe310/src/StdDriver/inc/usci_uart.h new file mode 100644 index 00000000..cd8afc74 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/usci_uart.h @@ -0,0 +1,417 @@ +/****************************************************************************** + * @file usci_uart.h + * @version V3.00 + * @brief M2351 series USCI UART (UUART) driver header file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#ifndef __USCI_UART_H__ +#define __USCI_UART_H__ + + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants + @{ +*/ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_LINECTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_WORD_LEN_6 (6UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */ +#define UUART_WORD_LEN_7 (7UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */ +#define UUART_WORD_LEN_8 (8UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */ +#define UUART_WORD_LEN_9 (9UL << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* UUART_PROTCTL constants definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_PARITY_NONE (0x0UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity */ +#define UUART_PARITY_ODD (0x1UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity */ +#define UUART_PARITY_EVEN (0x3UL << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity */ + +#define UUART_STOP_BIT_1 (0x0UL) /*!< UUART_PROTCTL setting for one stop bit */ +#define UUART_STOP_BIT_2 (0x1UL) /*!< UUART_PROTCTL setting for two stop bit */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* USCI UART interrupt mask definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define UUART_ABR_INT_MASK (0x002UL) /*!< Auto-baud rate interrupt mask */ +#define UUART_RLS_INT_MASK (0x004UL) /*!< Receive line status interrupt mask */ +#define UUART_BUF_RXOV_INT_MASK (0x008UL) /*!< Buffer RX overrun interrupt mask */ +#define UUART_TXST_INT_MASK (0x010UL) /*!< TX start interrupt mask */ +#define UUART_TXEND_INT_MASK (0x020UL) /*!< Tx end interrupt mask */ +#define UUART_RXST_INT_MASK (0x040UL) /*!< RX start interrupt mask */ +#define UUART_RXEND_INT_MASK (0x080UL) /*!< RX end interrupt mask */ + + +/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */ + + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u8Data Data byte to transmit. + * + * @return None + * + * @details This macro write Data to Tx data register. + */ +#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data)) + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The oldest data byte in RX buffer. + * + * @details This macro read Rx data register. + */ +#define UUART_READ(uuart) ((uuart)->RXDAT) + + +/** + * @brief Get Tx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not empty + * @retval >=1 Tx buffer is empty + * + * @details This macro get Transmitter buffer empty register value. + */ +#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) + + +/** + * @brief Get Rx empty + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not empty + * @retval >=1 Rx buffer is empty + * + * @details This macro get Receiver buffer empty register value. + */ +#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) + + +/** + * @brief Check specified usci_uart port transmission is over. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx transmission is not over + * @retval 1 Tx transmission is over + * + * @details This macro return Transmitter Empty Flag register bit value. \n + * It indicates if specified usci_uart port transmission is over nor not. + */ +#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos) + + +/** + * @brief Check specified usci_uart port receiver is empty. + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx receiver is not empty + * @retval 1 Rx receiver is empty + * + * @details This macro return Receive Empty Flag register bit value. \n + * It indicates if specified usci_uart port receiver is empty nor not. + */ +#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos) + + +/** + * @brief Wait specified usci_uart port transmission is over + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro wait specified usci_uart port transmission is over. + */ +#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)) + + +/** + * @brief Check TX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 TX buffer is full + * @retval 0 TX buffer is not full + * + * @details This macro check TX buffer is full or not. + */ +#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos) + + +/** + * @brief Check RX buffer is full or not + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 1 RX buffer is full + * @retval 0 RX buffer is not full + * + * @details This macro check RX buffer is full or not. + */ +#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos) + + +/** + * @brief Get Tx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Tx buffer is not full. + * @retval >=1 Tx buffer is full. + * + * @details This macro get Tx full register value. + */ +#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk) + + +/** + * @brief Get Rx full register value + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Rx buffer is not full. + * @retval >=1 Rx buffer is full. + * + * @details This macro get Rx full register value. + */ +#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk) + + +/** + * @brief Enable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART protocol interrupt. + */ +#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART protocol interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt + * - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART protocol interrupt. + */ +#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel)) + + +/** + * @brief Enable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART buffer interrupt. + */ +#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART buffer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART buffer interrupt. + */ +#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel)) + + +/** + * @brief Enable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro enable specified USCI_UART transfer interrupt. + */ +#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel)) + + +/** + * @brief Disable specified USCI_UART transfer interrupt + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntSel Interrupt type select + * - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt + * - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt + * - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt + * - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt + * + * @return None + * + * @details This macro disable specified USCI_UART transfer interrupt. + */ +#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel)) + + +/** + * @brief Get protocol interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of protocol status register. + * + * @details This macro get protocol status register value. + */ +#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS) + + +/** + * @brief Clear specified protocol interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator + * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag + * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag + * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag + * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag + * - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag + * - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag + * - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag + * - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag + * + * @return None + * + * @details This macro clear specified protocol interrupt flag. + */ +#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag)) + + +/** + * @brief Get transmit/receive buffer interrupt flag/status + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return The interrupt flag/status of buffer status register. + * + * @details This macro get buffer status register value. + */ +#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS) + + +/** + * @brief Clear specified buffer interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * @param[in] u32IntTypeFlag Interrupt Type Flag, should be + * - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator + * + * @return None + * + * @details This macro clear specified buffer interrupt flag. + */ +#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag)) + + +/** + * @brief Get wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @retval 0 Chip did not wake up from power-down mode. + * @retval 1 Chip waked up from power-down mode. + * + * @details This macro get wakeup flag. + */ +#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 ) + + +/** + * @brief Clear wakeup flag + * + * @param[in] uuart The pointer of the specified USCI_UART module + * + * @return None + * + * @details This macro clear wakeup flag. + */ +#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk) + + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask); +void UUART_Close(UUART_T* uuart); +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask); +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask); +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate); +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes); +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits); +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes); +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode); +void UUART_DisableWakeup(UUART_T* uuart); +void UUART_EnableFlowCtrl(UUART_T* uuart); +void UUART_DisableFlowCtrl(UUART_T* uuart); + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __USCI_UART_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/wdt.h b/arch/riscv32/fe310/src/StdDriver/inc/wdt.h new file mode 100644 index 00000000..f2470809 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/wdt.h @@ -0,0 +1,219 @@ +/**************************************************************************//** + * @file wdt.h + * @version V3.00 + * @brief Watchdog Timer(WDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WDT_H__ +#define __WDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Time-out Interval Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks \hideinitializer */ +#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Reset Delay Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks \hideinitializer */ +#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WDT Free Reset Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5UL) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter \hideinitializer */ + +/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Clear WDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out reset system flag. + * \hideinitializer + */ +#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk) + +/** + * @brief Clear WDT Time-out Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out interrupt flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk) + +/** + * @brief Clear WDT Wake-up Flag + * + * @param None + * + * @return None + * + * @details This macro clears WDT time-out wake-up system flag. + * \hideinitializer + */ +#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk) + +/** + * @brief Get WDT Time-out Reset Flag + * + * @param None + * + * @retval 0 WDT time-out reset system did not occur + * @retval 1 WDT time-out reset system occurred + * + * @details This macro indicates system has been reset by WDT time-out reset or not. + * \hideinitializer + */ +#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Interrupt Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt did not occur + * @retval 1 WDT time-out interrupt occurred + * + * @details This macro indicates WDT time-out interrupt occurred or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1UL : 0UL) + +/** + * @brief Get WDT Time-out Wake-up Flag + * + * @param None + * + * @retval 0 WDT time-out interrupt does not cause CPU wake-up + * @retval 1 WDT time-out interrupt event cause CPU wake-up + * + * @details This macro indicates WDT time-out interrupt event has waked up system or not. + * \hideinitializer + */ +#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1UL : 0UL) + +/** + * @brief Reset WDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reset the internal 18-bit WDT up counter value. + * @note If WDT is activated and time-out reset system function is enabled also, user should \n + * reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n + * reset system before the WDT time-out reset delay period expires. + * \hideinitializer + */ +#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD) + + +/*---------------------------------------------------------------------------------------------------------*/ +/* static inline functions */ +/*---------------------------------------------------------------------------------------------------------*/ +/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */ +__STATIC_INLINE void WDT_Close(void); +__STATIC_INLINE void WDT_EnableInt(void); +__STATIC_INLINE void WDT_DisableInt(void); + +/** + * @brief Stop WDT Counting + * + * @param None + * + * @return None + * + * @details This function will stop WDT counting and disable WDT module. + */ +__STATIC_INLINE void WDT_Close(void) +{ + WDT->CTL = 0UL; + while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait disable WDTEN bit completed, it needs 2 * WDT_CLK. */ +} + +/** + * @brief Enable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will enable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_EnableInt(void) +{ + WDT->CTL |= WDT_CTL_INTEN_Msk; + while(WDT->CTL & WDT_CTL_SYNC_Msk) {} /* Wait enable WDTEN bit completed, it needs 2 * WDT_CLK. */ +} + +/** + * @brief Disable WDT Time-out Interrupt + * + * @param None + * + * @return None + * + * @details This function will disable the WDT time-out interrupt function. + */ +__STATIC_INLINE void WDT_DisableInt(void) +{ + /* Do not touch another write 1 clear bits */ + WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk); +} + +void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup); + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WDT_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/inc/wwdt.h b/arch/riscv32/fe310/src/StdDriver/inc/wwdt.h new file mode 100644 index 00000000..d26552c6 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/inc/wwdt.h @@ -0,0 +1,152 @@ +/**************************************************************************//** + * @file wwdt.h + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver header file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#ifndef __WWDT_H__ +#define __WWDT_H__ + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants + @{ +*/ +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Prescale Period Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) \hideinitializer */ +#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) \hideinitializer */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* WWDT Reload Counter Keyword Constant Definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter \hideinitializer */ + +/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */ + + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Clear WWDT Reset System Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT time-out reset system flag. + * \hideinitializer + */ +#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk) + +/** + * @brief Clear WWDT Compared Match Interrupt Flag + * + * @param None + * + * @return None + * + * @details This macro is used to clear WWDT compared match interrupt flag. + * \hideinitializer + */ +#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk) + +/** + * @brief Get WWDT Reset System Flag + * + * @param None + * + * @retval 0 WWDT time-out reset system did not occur + * @retval 1 WWDT time-out reset system occurred + * + * @details This macro is used to indicate system has been reset by WWDT time-out reset or not. + * \hideinitializer + */ +#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Compared Match Interrupt Flag + * + * @param None + * + * @retval 0 WWDT compare match interrupt did not occur + * @retval 1 WWDT compare match interrupt occurred + * + * @details This macro is used to indicate WWDT counter value matches CMPDAT value or not. + * \hideinitializer + */ +#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0) + +/** + * @brief Get WWDT Counter + * + * @param None + * + * @return WWDT Counter Value + * + * @details This macro reflects the current WWDT counter value. + * \hideinitializer + */ +#define WWDT_GET_COUNTER() (WWDT->CNT) + +/** + * @brief Reload WWDT Counter + * + * @param None + * + * @return None + * + * @details This macro is used to reload the WWDT counter value to 0x3F. + * @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n + * between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n + * WWDT reset signal will generate immediately to reset system. + * \hideinitializer + */ +#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD) + +void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt); + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +#endif /* __WWDT_H__ */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/Makefile b/arch/riscv32/fe310/src/StdDriver/src/Makefile new file mode 100644 index 00000000..cf4c8331 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/Makefile @@ -0,0 +1,106 @@ +############################################################################ +# arch/cortex-m23/m2351/src/StdDriver/Makefile +# +# Copyright (c) 2019 Samsung Electronics Co., Ltd. All Rights Reserved. +# Author: Taras Drozdovskyi t.drozdovsky@samsung.com +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs +-include $(TOPDIR)/.config + +CFLAGS += -I../../CMSIS/Include +CFLAGS += -I../../StdDriver/inc +CFLAGS += -I../../Device/Nuvoton/M2351/Include +CFLAGS += -I$(TOPDIR)/include/mtower +CFLAGS += -I$(TOPDIR)/arch/$(CONFIG_ARCH)/$(CONFIG_ARCH_FAMILY)/src/$(CONFIG_PLATFORM) + +ifeq ($(WORLD), secure) +CFLAGS += -mcmse +endif + +CFLAGS += -Wno-unused-parameter -Wno-undef -Wno-maybe-uninitialized +CFLAGS += -Wno-unused-variable -Wno-pointer-compare + +#SRCS += acmp.c +#SRCS += bpwm.c +#SRCS += can.c +#SRCS += crc.c +#SRCS += crypto.c +#SRCS += dac.c +#SRCS += eadc.c +#SRCS += ebi.c +#SRCS += ecap.c +#SRCS += epwm.c +SRCS += fmc.c +SRCS += gpio.c +#SRCS += i2c.c +#SRCS += i2s.c +#SRCS += pdma.c +#SRCS += qei.c +#SRCS += qspi.c +SRCS += retarget.c +#SRCS += rtc.c +#SRCS += sc.c +#SRCS += scuart.c +#SRCS += sdh.c +#SRCS += spi.c +SRCS += sys.c +#SRCS += timer.c +#SRCS += timer_pwm.c +SRCS += uart.c +#SRCS += usbd.c +#SRCS += usci_i2c.c +#SRCS += usci_spi.c +#SRCS += usci_uart.c +#SRCS += wdt.c +#SRCS += wwdt.c + +ifeq ($(WORLD), secure) +SRCS += clk.c +endif + +ifneq ($(WORLD), secure) +CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_NONSECURE_DEBUG_UART)) +CFLAGS += -DDEBUG_OUT_PREFIX=$(CONFIG_NONSECURE_FONT_COLOR) +OBJDIR = $(TOPDIR)/build/nonsecure$(subst $(TOPDIR),,$(shell pwd)) +endif + +ifeq ($(WORLD), secure) +CFLAGS += -DDEBUG_PORT=$(subst ",,$(CONFIG_SECURE_DEBUG_UART)) +CFLAGS += -DDEBUG_OUT_PREFIX=$(CONFIG_SECURE_FONT_COLOR) +OBJDIR = $(TOPDIR)/build/secure$(subst $(TOPDIR),,$(shell pwd)) +endif + +OBJS = $(addprefix $(OBJDIR)/, $(SRCS:.c=.o)) + +current_dir = $(subst $(TOPDIR),,$(shell pwd)) + +$(OBJDIR)/%.o : %.c + $(Q) mkdir -p $(OBJDIR)/$(dir $<) + @echo "CC: $<" + $(Q) $(CC) $(CFLAGS) -c -o $@ $^ + +libm2351_StdDriver_s.a: $(OBJS) + $(Q) $(AR) $(OBJDIR)/$@ $(OBJS) + $(Q) cp $(OBJDIR)/$@ $(TOPDIR)/lib/$@ + +libm2351_StdDriver_ns.a: $(OBJS) + $(Q) $(AR) $(OBJDIR)/$@ $(OBJS) + $(Q) cp $(OBJDIR)/$@ $(TOPDIR)/lib/$@ + +clean: + rm -f libm2351_StdDriver.a + diff --git a/arch/riscv32/fe310/src/StdDriver/src/acmp.c b/arch/riscv32/fe310/src/StdDriver/src/acmp.c new file mode 100644 index 00000000..dc7a182f --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/acmp.c @@ -0,0 +1,87 @@ +/**************************************************************************//** + * @file acmp.c + * @version V3.00 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief Analog Comparator(ACMP) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include "M2351.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ACMP_Driver ACMP Driver + @{ +*/ + + +/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions + @{ +*/ + + +/** + * @brief Configure the specified ACMP module + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * @param[in] u32NegSrc Comparator negative input selection. Including: + * - \ref ACMP_CTL_NEGSEL_PIN + * - \ref ACMP_CTL_NEGSEL_CRV + * - \ref ACMP_CTL_NEGSEL_VBG + * - \ref ACMP_CTL_NEGSEL_DAC + * @param[in] u32HysSel The hysteresis function option. Including: + * - \ref ACMP_CTL_HYSTERESIS_30MV + * - \ref ACMP_CTL_HYSTERESIS_20MV + * - \ref ACMP_CTL_HYSTERESIS_10MV + * - \ref ACMP_CTL_HYSTERESIS_DISABLE + * + * @return None + * + * @details Configure hysteresis function, select the source of negative input and enable analog comparator. + */ +void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel) +{ + acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk); +} + +/** + * @brief Close analog comparator + * + * @param[in] acmp The pointer of the specified ACMP module + * @param[in] u32ChNum Comparator number. + * + * @return None + * + * @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator. + */ +void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum) +{ + acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk); +} + + + +/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ACMP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/bpwm.c b/arch/riscv32/fe310/src/StdDriver/src/bpwm.c new file mode 100644 index 00000000..9ede0107 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/bpwm.c @@ -0,0 +1,713 @@ +/**************************************************************************//** + * @file bpwm.c + * @version V1.00 + * @brief M2351 series BPWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup BPWM_Driver BPWM Driver + @{ +*/ + + +/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions + @{ +*/ + +/** + * @brief Configure BPWM capture and get the nearest unit time. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure BPWM capture and get the nearest unit time. + */ +uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec = 0U; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + uint8_t u8BreakLoop = 0U; + + (void)u32ChannelNum; + (void)u32CaptureEdge; + /* clock source is from PCLK */ + if((((uint32_t)bpwm) == BPWM0_BASE) || (((uint32_t)bpwm) == BPWM0_BASE + NS_OFFSET)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + u32PWMClockSrc /= 1000UL; + for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u32Prescale == 0x1000U) + { + /* limit to the maximum unit time(nano second) */ + u8BreakLoop = 1U; + } + if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) + { + u8BreakLoop = 1U; + } + } + else + { + u8BreakLoop = 1U; + } + if(u8BreakLoop) + { + break; + } + } + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* all channels share a prescaler */ + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + + /* set BPWM to down count type(edge aligned) */ + (bpwm)->CTL1 = (1UL); + + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + /* clock source is from PCLK */ + if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else/* if((bpwm == BPWM1)||(bpwm == BPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i <= (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* all channels share a prescaler */ + BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale); + /* set BPWM to up counter type(edge aligned) */ + (bpwm)->CTL1 = BPWM_UP_COUNTER; + + u32CNR = u32CNR - 1U; + BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR); + BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL); + + + (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << BPWM_WGCTL0_ZPCTL0_Pos)); + (bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \ + (BPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << BPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to start BPWM module. + * @note All channels share one counter. + */ +void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Stop BPWM module + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM module. + * @note All channels share one period. + */ +void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->PERIOD = 0UL; +} + +/** + * @brief Stop BPWM generation immediately by clear channel enable bit + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used. + * @return None + * @details This function is used to stop BPWM generation immediately by clear channel enable bit. + * @note All channels share one counter. + */ +void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (void)u32ChannelMask; + (bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_EVEN_CMP_DOWN_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_UP_COUNT_POINT + * - \ref BPWM_TRIGGER_ADC_ODD_CMP_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable selected channel to trigger ADC + */ +void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3)); + (bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3)); + (bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3 + * @return None + * @details This function is used to disable selected channel to trigger ADC + */ +void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4UL) + { + (bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3)); + } + else + { + (bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag + */ +void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32Condition; + (bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel + */ +uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s) + */ +void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN |= u32ChannelMask; + (bpwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s) + */ +void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->CAPINEN &= ~u32ChannelMask; + (bpwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enables BPWM output generation of selected channel(s) + */ +void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables BPWM output generation of selected channel(s) + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disables BPWM output generation of selected channel(s) + */ +void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask) +{ + (bpwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref BPWM_CAPTURE_INT_RISING_LATCH + * - \ref BPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (bpwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapIf = 0UL; + + u32CapIf = ((((bpwm)->CAPIF & (BYTE1_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1); + u32CapIf |= (((bpwm)->CAPIF & (BYTE0_Msk << u32ChannelNum)) ? 1UL : 0UL); + return u32CapIf; +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel + */ +void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTEN &= ~(uint32_t)((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel + */ +void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (bpwm)->INTSTS = (BYTE2_Msk | BYTE3_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel + */ +uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + return ((((bpwm)->INTSTS & ((BYTE2_Msk | BYTE3_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (void)u32ChannelNum; + (void)u32IntPeriodType; + (bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable period interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk; +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk; +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to enable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to disable zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk; +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk; +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return zero interrupt flag of specified channel + * @retval 0 zero interrupt did not occur + * @retval 1 zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode BPWM counter loading mode. + * - \ref BPWM_LOAD_MODE_IMMEDIATE + * - \ref BPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Set BPWM clock source + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @param[in] u32ClkSrcSel BPWM external clock source. + * - \ref BPWM_CLKSRC_BPWM_CLK + * - \ref BPWM_CLKSRC_TIMER0 + * - \ref BPWM_CLKSRC_TIMER1 + * - \ref BPWM_CLKSRC_TIMER2 + * - \ref BPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set BPWM clock source. + * @note All channels share channel 0's setting. + */ +void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (void)u32ChannelNum; + (bpwm)->CLKSRC = (u32ClkSrcSel); +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] bpwm The pointer of the specified BPWM module + * - BPWM0 : BPWM Group 0 + * - BPWM1 : BPWM Group 1 + * @param[in] u32ChannelNum BPWM channel number. This parameter is not used. + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + * @note All channels share channel 0's setting. + */ +void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + (bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk; +} + + +/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group BPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/can.c b/arch/riscv32/fe310/src/StdDriver/src/can.c new file mode 100644 index 00000000..56986b6d --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/can.c @@ -0,0 +1,1193 @@ +/**************************************************************************//** + * @file can.c + * @version V1.00 + * @brief CAN driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "M2351.h" + +#if defined(__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CAN_Driver CAN Driver + @{ +*/ + +/** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions + @{ +*/ + +/** @cond HIDDEN_SYMBOLS */ + +#if defined(CAN1) +static uint8_t gu8LockCanIf[2][2] = {{0U}}; /* The chip has two CANs. */ +#elif defined(CAN0) || defined(CAN) +static uint8_t gu8LockCanIf[1][2] = {{0U}}; /* The chip only has one CAN. */ +#endif + +#define RETRY_COUNTS (0x10000000UL) + +#define TSEG1_MIN 2 +#define TSEG1_MAX 16 +#define TSEG2_MIN 1 +#define TSEG2_MAX 8 +#define BRP_MIN 1 +#define BRP_MAX 1024 /* 6-bit BRP field + 4-bit BRPE field*/ +#define SJW_MAX 4UL +#define BRP_INC 1 + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + + +static uint32_t LockIF(CAN_T *tCAN); +static uint32_t LockIF_TL(CAN_T *tCAN); +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo); +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2); + +/** + * @brief Check if any interface is available then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If a interface is + * available, set a flag to lock the interface. + */ +static uint32_t LockIF(CAN_T *tCAN) +{ + uint32_t u32CanNo; + uint32_t u32FreeIfNo; + uint32_t u32IntMask; + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1 : 0; +#else // defined(CAN0) || defined(CAN) + u32CanNo = 0U; +#endif + + u32FreeIfNo = 2U; + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + /* Check interface 1 is available or not */ + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U) + { + if(gu8LockCanIf[u32CanNo][0] == (uint8_t)FALSE) + { + gu8LockCanIf[u32CanNo][0] = (uint8_t)TRUE; + u32FreeIfNo = 0U; + } + } + + /* Or check interface 2 is available or not */ + if(u32FreeIfNo == 2U) + { + if((tCAN->IF[1].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0U) + { + if(gu8LockCanIf[u32CanNo][1] == (uint8_t)FALSE) + { + gu8LockCanIf[u32CanNo][1] = (uint8_t)TRUE; + u32FreeIfNo = 1U; + } + } + } + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + + return u32FreeIfNo; +} + +/** + * @brief Check if any interface is available in a time limitation then lock it for usage. + * @param[in] tCAN The pointer to CAN module base address. + * @retval 0 IF0 is free + * @retval 1 IF1 is free + * @retval 2 No IF is free + * @details Search the first free message interface, starting from 0. If no interface is + * it will try again until time out. If a interface is available, set a flag to + * lock the interface. + */ +static uint32_t LockIF_TL(CAN_T *tCAN) +{ + uint32_t u32Count; + uint32_t u32FreeIfNo = 0U; + + for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++) + { + if((u32FreeIfNo = LockIF(tCAN)) != 2U) + { + break; + } + } + + return u32FreeIfNo; +} + +/** + * @brief Release locked interface. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Info The interface number, 0 or 1. + * @return none + * @details Release the locked interface. + */ +static void ReleaseIF(CAN_T *tCAN, uint32_t u32IfNo) +{ + uint32_t u32IntMask; + uint32_t u32CanNo; + + if(u32IfNo < 2U) + { + +#if defined(CAN1) + u32CanNo = (tCAN == CAN1) ? 1U : 0U; +#else // defined(CAN0) || defined(CAN) + u32CanNo = 0U; +#endif + + /* Disable CAN interrupt */ + u32IntMask = tCAN->CON & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + tCAN->CON = tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk); + + gu8LockCanIf[u32CanNo][u32IfNo] = (uint8_t)FALSE; + + /* Enable CAN interrupt */ + tCAN->CON |= u32IntMask; + } +} + +/** + * @brief Enter initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] Following values can be used. + * \ref CAN_CON_DAR_Msk Disable automatic retransmission. + * \ref CAN_CON_EIE_Msk Enable error interrupt. + * \ref CAN_CON_SIE_Msk Enable status interrupt. + * \ref CAN_CON_IE_Msk CAN interrupt. + * @return None + * @details This function is used to set CAN to enter initialization mode and enable access bit timing + * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() + * to leave initialization mode and lock bit timing register to let new configuration + * take effect. + */ +void CAN_EnterInitMode(CAN_T *tCAN, uint8_t u8Mask) +{ + tCAN->CON = u8Mask | (CAN_CON_INIT_Msk | CAN_CON_CCE_Msk); +} + + +/** + * @brief Leave initialization mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to set CAN to leave initialization mode to let + * bit timing configuration take effect after configuration ready. + */ +void CAN_LeaveInitMode(CAN_T *tCAN) +{ + tCAN->CON &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); + while(tCAN->CON & CAN_CON_INIT_Msk) {} /* Check INIT bit is released */ +} + +/** + * @brief Wait message into message buffer in basic mode. + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to wait message into message buffer in basic mode. Please notice the + * function is polling NEWDAT bit of MCON register by while loop and it is used in basic mode. + */ +void CAN_WaitMsg(CAN_T *tCAN) +{ + tCAN->STATUS = 0x0U; /* clr status */ + + while(1) + { + if(tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) /* check new data */ + { + /* DEBUG_PRINTF("New Data IN\n"); */ + break; + } + + if(tCAN->STATUS & CAN_STATUS_RXOK_Msk) + { + /* DEBUG_PRINTF("Rx OK\n"); */ + } + + if(tCAN->STATUS & CAN_STATUS_LEC_Msk) + { + /* DEBUG_PRINTF("Error\n"); */ + } + } +} + +/** + * @brief Get current bit rate + * @param[in] tCAN The pointer to CAN module base address. + * @return Current Bit-Rate (kilo bit per second) + * @details Return current CAN bit rate according to the user bit-timing parameter settings + */ +uint32_t CAN_GetCANBitRate(CAN_T *tCAN) +{ + uint8_t u8Tseg1, u8Tseg2; + uint32_t u32Bpr; + + u8Tseg1 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG1_Msk) >> CAN_BTIME_TSEG1_Pos); + u8Tseg2 = (uint8_t)((tCAN->BTIME & CAN_BTIME_TSEG2_Msk) >> CAN_BTIME_TSEG2_Pos); + u32Bpr = (tCAN->BTIME & CAN_BTIME_BRP_Msk); + u32Bpr |= (tCAN->BRPE << 6); + + + return (SystemCoreClock / (u32Bpr + 1U) / ((uint32_t)u8Tseg1 + (uint32_t)u8Tseg2 + 3U)); +} + +/** + * @brief Switch the CAN into test mode. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8TestMask Specifies the configuration in test modes + * \ref CAN_TEST_BASIC_Msk Enable basic mode of test mode + * \ref CAN_TEST_SILENT_Msk Enable silent mode of test mode + * \ref CAN_TEST_LBACK_Msk Enable Loop Back Mode of test mode + * \ref CAN_TEST_TX0_Msk / \ref CAN_TEST_TX1_Msk Control CAN_TX pin bit field + * @return None + * @details Switch the CAN into test mode. There are four test mode (BASIC/SILENT/LOOPBACK/ + * LOOPBACK combined SILENT/CONTROL_TX_PIN)could be selected. After setting test mode,user + * must call CAN_LeaveInitMode() to let the setting take effect. + */ +void CAN_EnterTestMode(CAN_T *tCAN, uint8_t u8TestMask) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST = u8TestMask; +} + + +/** + * @brief Leave the test mode + * @param[in] tCAN The pointer to CAN module base address. + * @return None + * @details This function is used to Leave the test mode (switch into normal mode). + */ +void CAN_LeaveTestMode(CAN_T *tCAN) +{ + tCAN->CON |= CAN_CON_TEST_Msk; + tCAN->TEST &= ~(CAN_TEST_LBACK_Msk | CAN_TEST_SILENT_Msk | CAN_TEST_BASIC_Msk); + tCAN->CON &= (~CAN_CON_TEST_Msk); +} + +/** + * @brief Get the waiting status of a received message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @retval non-zero The corresponding message object has a new data bit is set. + * @retval 0 No message object has new data. + * @details This function is used to get the waiting status of a received message. + */ +uint32_t CAN_IsNewDataReceived(CAN_T *tCAN, uint8_t u8MsgObj) +{ + uint32_t ret; + + if((uint32_t)u8MsgObj < 16U) + { + ret = tCAN->NDAT1 & (1UL << u8MsgObj); + } + else + { + ret = tCAN->NDAT2 & (1UL << (u8MsgObj - 16U)); + } + + return ret; +} + + +/** + * @brief Send CAN message in BASIC mode of test mode + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure containing data to transmit. + * @return TRUE: Transmission OK + * FALSE: Check busy flag of interface 0 is timeout + * @details The function is used to send CAN message in BASIC mode of test mode. Before call the API, + * the user should be call CAN_EnterTestMode(CAN_TEST_BASIC) and let CAN controller enter + * basic mode of test mode. Please notice IF1 Registers used as Tx Buffer in basic mode. + */ +int32_t CAN_BasicSendMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + uint32_t i = 0UL; + while(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) {} + + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[0].ARB1 = 0UL; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) ; + } + else + { + /* extended ID*/ + tCAN->IF[0].ARB1 = (pCanMsg->Id) & 0xFFFFUL; + tCAN->IF[0].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_XTD_Msk; + + } + + if(pCanMsg->FrameType) + { + tCAN->IF[0].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[0].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + tCAN->IF[0].MCON = (tCAN->IF[0].MCON & (~CAN_IF_MCON_DLC_Msk)) | pCanMsg->DLC; + tCAN->IF[0].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | pCanMsg->Data[0]; + tCAN->IF[0].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | pCanMsg->Data[2]; + tCAN->IF[0].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + tCAN->IF[0].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + /* request transmission*/ + tCAN->IF[0].CREQ &= (~CAN_IF_CREQ_BUSY_Msk); + if(tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /* DEBUG_PRINTF("Cannot clear busy for sending ...\n"); */ + return (int32_t)FALSE; + } + + tCAN->IF[0].CREQ |= CAN_IF_CREQ_BUSY_Msk; /* sending */ + + for(i = 0UL; i < 0xFFFFFUL; i++) + { + if((tCAN->IF[0].CREQ & CAN_IF_CREQ_BUSY_Msk) == 0UL) + { + break; + } + } + + if(i >= 0xFFFFFUL) + { + /* DEBUG_PRINTF("Cannot send out...\n"); */ + return (int32_t)FALSE; + } + + + return (int32_t)TRUE; +} + +/** + * @brief Get a message information in BASIC mode. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @return FALSE No any message received. + * TRUE Receive a message success. + * + */ +int32_t CAN_BasicReceiveMsg(CAN_T *tCAN, STR_CANMSG_T* pCanMsg) +{ + + if((tCAN->IF[1].MCON & CAN_IF_MCON_NEWDAT_Msk) == 0UL) /* In basic mode, receive data always save in IF2 */ + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + tCAN->IF[1].CMASK = CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + if((tCAN->IF[1].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0UL) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 >> 2) & 0x07FFUL; + + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + pCanMsg->Id = (tCAN->IF[1].ARB2 & 0x1FFFUL) << 16; + pCanMsg->Id |= (uint32_t)tCAN->IF[1].ARB1; + } + + /* + pCanMsg->FrameType = (uint32_t)(!(uint32_t)((tCAN->IF[1].ARB2 & (uint32_t)CAN_IF_ARB2_DIR_Msk) >> (uint32_t)CAN_IF_ARB2_DIR_Pos)); + */ + + pCanMsg->FrameType = (tCAN->IF[1].ARB2 & CAN_IF_ARB2_DIR_Msk) ? 0UL : 1UL; + + pCanMsg->DLC = (uint8_t)(tCAN->IF[1].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[1].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[1].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[1].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[1].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + return (int32_t)TRUE; +} + +/** + * @brief Set Rx message object, include ID mask. + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObjAndMsk(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint32_t u32idmask, uint8_t u8singleOrFifoLast) +{ + uint8_t u8MsgIfNum; + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* Command Setting */ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u8MsgIfNum].ARB1 = 0U; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2; + } + else + { + tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16; + } + + tCAN->IF[u8MsgIfNum].MASK1 = (u32idmask & 0xFFFFUL); + tCAN->IF[u8MsgIfNum].MASK2 = (u32idmask >> 16) & 0xFFFFUL; + + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u8MsgIfNum].DAT_A1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_A2 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B2 = 0U; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Set Rx message object + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8idType Specifies the identifier type of the frames that will be transmitted + * This parameter can be one of the following values: + * \ref CAN_STD_ID (standard ID, 11-bit) + * \ref CAN_EXT_ID (extended ID, 29-bit) + * @param[in] u32id Specifies the identifier used for acceptance filtering. + * @param[in] u8singleOrFifoLast Specifies the end-of-buffer indicator. + * This parameter can be one of the following values: + * TRUE: for a single receive object or a FIFO receive object that is the last one of the FIFO. + * FALSE: for a FIFO receive object that is not the last one. + * @retval TRUE SUCCESS + * @retval FALSE No useful interface + * @details The function is used to configure a receive message object. + */ +int32_t CAN_SetRxMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8idType, uint32_t u32id, uint8_t u8singleOrFifoLast) +{ + uint8_t u8MsgIfNum; + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* Command Setting */ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(u8idType == CAN_STD_ID) /* According STD/EXT ID format,Configure Mask and Arbitration register */ + { + tCAN->IF[u8MsgIfNum].ARB1 = 0U; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | (u32id & 0x7FFUL) << 2; + } + else + { + tCAN->IF[u8MsgIfNum].ARB1 = u32id & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = CAN_IF_ARB2_MSGVAL_Msk | CAN_IF_ARB2_XTD_Msk | (u32id & 0x1FFF0000UL) >> 16; + } + + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_UMASK_Msk | CAN_IF_MCON_RXIE_Msk; + if(u8singleOrFifoLast) + { + tCAN->IF[u8MsgIfNum].MCON |= CAN_IF_MCON_EOB_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].MCON &= (~CAN_IF_MCON_EOB_Msk); + } + + tCAN->IF[u8MsgIfNum].DAT_A1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_A2 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B1 = 0U; + tCAN->IF[u8MsgIfNum].DAT_B2 = 0U; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Gets the message + * @param[in] u8MsgObj Specifies the Message object number, from 0 to 31. + * @param[in] u8Release Specifies the message release indicator. + * This parameter can be one of the following values: + * TRUE: the message object is released when getting the data. + * FALSE:the message object is not released. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * @retval TRUE Success + * @retval FALSE No any message received + * @details Gets the message, if received. + */ +int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CANMSG_T* pCanMsg) +{ + uint8_t u8MsgIfNum; + uint32_t u32Tmp; + + if(!CAN_IsNewDataReceived(tCAN, u8MsgObj)) + { + return (int32_t)FALSE; + } + + /* Get and lock a free interface */ + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_RXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_MASK_Msk + | CAN_IF_CMASK_ARB_Msk + | CAN_IF_CMASK_CONTROL_Msk + | CAN_IF_CMASK_CLRINTPND_Msk + | (u8Release ? CAN_IF_CMASK_TXRQSTNEWDAT_Msk : 0UL) + | CAN_IF_CMASK_DATAA_Msk + | CAN_IF_CMASK_DATAB_Msk; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u8MsgObj; + + while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + + if((tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_XTD_Msk) == 0U) + { + /* standard ID*/ + pCanMsg->IdType = CAN_STD_ID; + pCanMsg->Id = (tCAN->IF[u8MsgIfNum].ARB2 & CAN_IF_ARB2_ID_Msk) >> 2; + } + else + { + /* extended ID*/ + pCanMsg->IdType = CAN_EXT_ID; + + u32Tmp = (((tCAN->IF[u8MsgIfNum].ARB2) & 0x1FFFUL) << 16); + u32Tmp |= tCAN->IF[u8MsgIfNum].ARB1; + + pCanMsg->Id = u32Tmp; + } + + pCanMsg->DLC = (uint8_t)(tCAN->IF[u8MsgIfNum].MCON & CAN_IF_MCON_DLC_Msk); + pCanMsg->Data[0] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA0_Msk); + pCanMsg->Data[1] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A1 & CAN_IF_DAT_A1_DATA1_Msk) >> CAN_IF_DAT_A1_DATA1_Pos); + pCanMsg->Data[2] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA2_Msk); + pCanMsg->Data[3] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_A2 & CAN_IF_DAT_A2_DATA3_Msk) >> CAN_IF_DAT_A2_DATA3_Pos); + pCanMsg->Data[4] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA4_Msk); + pCanMsg->Data[5] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B1 & CAN_IF_DAT_B1_DATA5_Msk) >> CAN_IF_DAT_B1_DATA5_Pos); + pCanMsg->Data[6] = (uint8_t)(tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA6_Msk); + pCanMsg->Data[7] = (uint8_t)((tCAN->IF[u8MsgIfNum].DAT_B2 & CAN_IF_DAT_B2_DATA7_Msk) >> CAN_IF_DAT_B2_DATA7_Pos); + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + return (int32_t)TRUE; +} + +static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2) +{ + *tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000; + if(*tseg2 < TSEG2_MIN) + { + *tseg2 = TSEG2_MIN; + } + if(*tseg2 > TSEG2_MAX) + { + *tseg2 = TSEG2_MAX; + } + + *tseg1 = tseg - *tseg2; + + if(*tseg1 > TSEG1_MAX) + { + *tseg1 = TSEG1_MAX; + *tseg2 = tseg - *tseg1; + } + return 1000 * (tseg + 1 - *tseg2) / (tseg + 1); +} + +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Set bus baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * + * @return u32CurrentBitRate Real baud-rate value. + * + * @details The function is used to set bus timing parameter according current clock and target baud-rate. + */ +uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate) +{ + long rate; + long best_error = 1000000000, error = 0; + int best_tseg = 0, best_brp = 0, brp = 0; + int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0; + int spt_error = 1000, spt = 0, sampl_pt; + int64_t clock_freq = 0; + uint32_t sjw = 1UL; + + CAN_EnterInitMode(tCAN, 0U); + + clock_freq = (int64_t)CLK_GetPCLK0Freq(); + + if(u32BaudRate >= 1000000UL) + { + u32BaudRate = 1000000UL; + } + + /* Use CIA recommended sample points */ + if(u32BaudRate > 800000UL) + { + sampl_pt = 750; + } + else if(u32BaudRate > 500000UL) + { + sampl_pt = 800; + } + else + { + sampl_pt = 875; + } + + /* tseg even = round down, odd = round up */ + for(tseg = (TSEG1_MAX + TSEG2_MAX) * 2 + 1; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2; tseg--) + { + tsegall = 1 + tseg / 2; + /* Compute all possible tseg choices (tseg=tseg1+tseg2) */ + + /* brp = (int32_t)(clock_freq / (tsegall * u32BaudRate)) + (tseg % 2); */ + brp = (int32_t)(clock_freq / ((int64_t)tsegall * (int32_t)u32BaudRate)) + (tseg % 2); + + + /* chose brp step which is possible in system */ + brp = (brp / BRP_INC) * BRP_INC; + + if((brp >= BRP_MIN) && (brp <= BRP_MAX)) + { + rate = (int32_t)(clock_freq / ((int64_t)brp * tsegall)); + + error = (int32_t)u32BaudRate - rate; + + /* tseg brp biterror */ + if(error < 0) + { + error = -error; + } + + if(error <= best_error) + { + best_error = error; + if(error == 0) + { + spt = can_update_spt(sampl_pt, tseg / 2, &tseg1, &tseg2); + error = sampl_pt - spt; + if(error < 0) + { + error = -error; + } + if(error <= spt_error) + { + spt_error = error; + best_tseg = tseg / 2; + best_brp = brp; + if(error == 0) + { + break; + } + } + } + else + { + best_tseg = tseg / 2; + best_brp = brp; + } + } + } + } + + spt = can_update_spt(sampl_pt, best_tseg, &tseg1, &tseg2); + + /* check for sjw user settings */ + /* bt->sjw is at least 1 -> sanitize upper bound to sjw_max */ + if(sjw > SJW_MAX) + { + sjw = SJW_MAX; + } + /* bt->sjw must not be higher than tseg2 */ + if(tseg2 < (int32_t)sjw) + { + sjw = (uint32_t)tseg2; + } + + /* real bit-rate */ + u32BaudRate = (uint32_t)(int32_t)(clock_freq / (int32_t)(best_brp * (tseg1 + tseg2 + 1))); + + tCAN->BTIME = (((uint32_t)tseg2 - 1UL) << CAN_BTIME_TSEG2_Pos) | (((uint32_t)tseg1 - 1UL) << CAN_BTIME_TSEG1_Pos) | + (((uint32_t)best_brp - 1UL) & CAN_BTIME_BRP_Msk) | (sjw << CAN_BTIME_SJW_Pos); + + + tCAN->BRPE = (((uint32_t)best_brp - 1UL) >> 6) & 0x0FUL; + + /* DEBUG_PRINTF("\n bitrate = %d \n", CAN_GetCANBitRate(tCAN)); */ + + CAN_LeaveInitMode(tCAN); + + return u32BaudRate; +} + +/** + * @brief The function is used to disable all CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * + * @return None + * + * @details No Status Change Interrupt and Error Status Interrupt will be generated. + */ + + +void CAN_Close(CAN_T *tCAN) +{ + CAN_DisableInt(tCAN, (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + + + +/** + * @brief Set CAN operation mode and target baud-rate. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32BaudRate The target CAN baud-rate. The range of u32BaudRate is 1~1000KHz. + * @param[in] u32Mode The CAN operation mode. Valid values are: + * - \ref CAN_NORMAL_MODE Normal operation. + * - \ref CAN_BASIC_MODE Basic mode. + * @return u32CurrentBitRate Real baud-rate value. + * + * @details Set bus timing parameter according current clock and target baud-rate. + * In Basic mode, IF1 Registers used as Tx Buffer, IF2 Registers used as Rx Buffer. + */ +uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode) +{ + uint32_t u32CurrentBitRate; + + u32CurrentBitRate = CAN_SetBaudRate(tCAN, u32BaudRate); + + if(u32Mode == CAN_BASIC_MODE) + { + CAN_EnterTestMode(tCAN, (uint8_t)CAN_TEST_BASIC_Msk); + } + + return u32CurrentBitRate; +} + +/** + * @brief The function is used to configure a transmit object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No useful interface. + * @retval TRUE Config message object success. + * + * @details The two sets of interface registers (IF1 and IF2) control the software access to the Message RAM. + * They buffer the data to be transferred to and from the RAM, avoiding conflicts between software accesses and message reception/transmission. + */ +int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint8_t u8MsgIfNum; + + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + /* update the contents needed for transmission*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_MASK_Msk | CAN_IF_CMASK_ARB_Msk | + CAN_IF_CMASK_CONTROL_Msk | CAN_IF_CMASK_DATAA_Msk | CAN_IF_CMASK_DATAB_Msk; + + if(pCanMsg->IdType == CAN_STD_ID) + { + /* standard ID*/ + tCAN->IF[u8MsgIfNum].ARB1 = 0UL; + tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x7FFUL) << 2) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + else + { + /* extended ID*/ + tCAN->IF[u8MsgIfNum].ARB1 = (pCanMsg->Id) & 0xFFFFUL; + tCAN->IF[u8MsgIfNum].ARB2 = (((pCanMsg->Id) & 0x1FFF0000UL) >> 16) | CAN_IF_ARB2_DIR_Msk | CAN_IF_ARB2_XTD_Msk | CAN_IF_ARB2_MSGVAL_Msk; + } + + if(pCanMsg->FrameType) + { + tCAN->IF[u8MsgIfNum].ARB2 |= CAN_IF_ARB2_DIR_Msk; + } + else + { + tCAN->IF[u8MsgIfNum].ARB2 &= (~CAN_IF_ARB2_DIR_Msk); + } + + + tCAN->IF[u8MsgIfNum].DAT_A1 = ((uint32_t)pCanMsg->Data[1] << 8) | (uint32_t)pCanMsg->Data[0]; + tCAN->IF[u8MsgIfNum].DAT_A2 = ((uint32_t)pCanMsg->Data[3] << 8) | (uint32_t)pCanMsg->Data[2]; + tCAN->IF[u8MsgIfNum].DAT_B1 = ((uint32_t)pCanMsg->Data[5] << 8) | pCanMsg->Data[4]; + tCAN->IF[u8MsgIfNum].DAT_B2 = ((uint32_t)pCanMsg->Data[7] << 8) | pCanMsg->Data[6]; + + tCAN->IF[u8MsgIfNum].MCON = CAN_IF_MCON_NEWDAT_Msk | pCanMsg->DLC | CAN_IF_MCON_TXIE_Msk | CAN_IF_MCON_EOB_Msk; + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Set transmit request bit. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return TRUE: Start transmit message. + * + * @details If a transmission is requested by programming bit TxRqst/NewDat (IFn_CMASK[2]), the TxRqst (IFn_MCON[8]) will be ignored. + */ +int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum) +{ + uint8_t u8MsgIfNum; + + if((u8MsgIfNum = (uint8_t)LockIF_TL(tCAN)) == 2U) + { + return (int32_t)FALSE; + } + + tCAN->STATUS &= (~CAN_STATUS_TXOK_Msk); + + /* read the message contents*/ + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk + | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + while(tCAN->IF[u8MsgIfNum].CREQ & CAN_IF_CREQ_BUSY_Msk) + { + /*Wait*/ + } + tCAN->IF[u8MsgIfNum].CMASK = CAN_IF_CMASK_WRRD_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u8MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, (uint32_t)u8MsgIfNum); + + return (int32_t)TRUE; +} + +/** + * @brief Enable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. Valid values are: + * - \ref CAN_CON_IE_Msk Module interrupt enable. + * - \ref CAN_CON_SIE_Msk Status change interrupt enable. + * - \ref CAN_CON_EIE_Msk Error interrupt enable. + * + * @return None + * + * @details The application software has two possibilities to follow the source of a message interrupt. + * First, it can follow the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register. + */ +void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = (tCAN->CON & ~(CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)) | + (u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk)); +} + +/** + * @brief Disable CAN interrupt. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32Mask Interrupt Mask. (CAN_CON_IE_Msk / CAN_CON_SIE_Msk / CAN_CON_EIE_Msk). + * + * @return None + * + * @details The interrupt remains active until the Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset. + */ +void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask) +{ + tCAN->CON = tCAN->CON & ~((u32Mask & (CAN_CON_IE_Msk | CAN_CON_SIE_Msk | CAN_CON_EIE_Msk))); +} + + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID) +{ + uint32_t u32TimeOutCount = 0UL; + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + + return (int32_t)TRUE; +} + +/** + * @brief The function is used to configure a receive message object. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * @param[in] u32IDMask Specifies the identifier mask used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure a receive message object success. + * + * @details If the RxIE bit (CAN_IFn_MCON[10]) is set, the IntPnd bit (CAN_IFn_MCON[13]) + * will be set when a received Data Frame is accepted and stored in the Message Object. + */ +int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask) +{ + uint32_t u32TimeOutCount = 0UL; + + while(CAN_SetRxMsgObjAndMsk(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, u32IDMask, (uint8_t)TRUE) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + + return (int32_t)TRUE; +} + +/** + * @brief The function is used to configure several receive message objects. + * + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum The starting MSG RAM number(0 ~ 31). + * @param[in] u32MsgCount the number of MSG RAM of the FIFO. + * @param[in] u32IDType Specifies the identifier type of the frames that will be transmitted. Valid values are: + * - \ref CAN_STD_ID The 11-bit identifier. + * - \ref CAN_EXT_ID The 29-bit identifier. + * @param[in] u32ID Specifies the identifier used for acceptance filtering. + * + * @retval FALSE No useful interface. + * @retval TRUE Configure receive message objects success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum, uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID) +{ + uint32_t i = 0UL; + uint32_t u32TimeOutCount; + uint32_t u32EOB_Flag = 0UL; + + for(i = 1UL; i < u32MsgCount; i++) + { + u32TimeOutCount = 0UL; + + u32MsgNum += (i - 1UL); + + if(i == u32MsgCount) + { + u32EOB_Flag = 1UL; + } + + while(CAN_SetRxMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)u32IDType, u32ID, (uint8_t)u32EOB_Flag) == (int32_t)FALSE) + { + if(++u32TimeOutCount >= RETRY_COUNTS) + { + return (int32_t)FALSE; + } + } + } + + return (int32_t)TRUE; +} + + +/** + * @brief Send CAN message. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE 1. When operation in basic mode: Transmit message time out. \n + * 2. When operation in normal mode: No useful interface. \n + * @retval TRUE Transmit Message success. + * + * @details The receive/transmit priority for the Message Objects is attached to the message number. + * Message Object 1 has the highest priority, while Message Object 32 has the lowest priority. + */ +int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint32_t cond0, cond1; + + cond0 = tCAN->CON & CAN_CON_TEST_Msk; + cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk; + if(cond0 && cond1) + { + return (CAN_BasicSendMsg(tCAN, pCanMsg)); + } + else + { + if(CAN_SetTxMsg(tCAN, u32MsgNum, pCanMsg) == (int32_t)FALSE) + { + return (int32_t)FALSE; + } + CAN_TriggerTxMsg(tCAN, u32MsgNum); + } + + return (int32_t)TRUE; +} + + +/** + * @brief Gets the message, if received. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * @param[in] pCanMsg Pointer to the message structure where received data is copied. + * + * @retval FALSE No any message received. + * @retval TRUE Receive Message success. + * + * @details The Interface Registers avoid conflict between the CPU accesses to the Message RAM and CAN message reception + * and transmission by buffering the data to be transferred. + */ +int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum, STR_CANMSG_T* pCanMsg) +{ + uint32_t cond0, cond1; + + cond0 = tCAN->CON & CAN_CON_TEST_Msk; + cond1 = tCAN->TEST & CAN_TEST_BASIC_Msk; + + if(cond0 && cond1) + { + return (CAN_BasicReceiveMsg(tCAN, pCanMsg)); + } + else + { + return CAN_ReadMsgObj(tCAN, (uint8_t)u32MsgNum, (uint8_t)TRUE, pCanMsg); + } +} + +/** + * @brief Clear interrupt pending bit. + * @param[in] tCAN The pointer to CAN module base address. + * @param[in] u32MsgNum Specifies the Message object number, from 0 to 31. + * + * @return None + * + * @details An interrupt remains pending until the application software has cleared it. + */ +void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum) +{ + uint32_t u32MsgIfNum; + + if((u32MsgIfNum = LockIF_TL(tCAN)) == 2UL) + { + u32MsgIfNum = 0UL; + } + + tCAN->IF[u32MsgIfNum].CMASK = CAN_IF_CMASK_CLRINTPND_Msk | CAN_IF_CMASK_TXRQSTNEWDAT_Msk; + tCAN->IF[u32MsgIfNum].CREQ = 1UL + u32MsgNum; + + ReleaseIF(tCAN, u32MsgIfNum); +} + +/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CAN_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/clk.c b/arch/riscv32/fe310/src/StdDriver/src/clk.c new file mode 100644 index 00000000..8340e5ad --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/clk.c @@ -0,0 +1,1237 @@ +/**************************************************************************//** + * @file clk.c + * @version V3.00 + * @brief M2351 series Clock Controller (CLK) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CLK_Driver CLK Driver + @{ +*/ + + +/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions + @{ +*/ + + +/** + * @brief Disable frequency output function + * @param None + * @return None + * @details This function disable frequency output function. + */ +void CLK_DisableCKO(void) +{ + /* Disable CKO clock source */ + CLK->APBCLK0 &= (~CLK_APBCLK0_CLKOCKEN_Msk); +} + + +/** + * @brief This function enable frequency divider module clock. + * enable frequency divider clock function and configure frequency divider. + * @param[in] u32ClkSrc is frequency divider function clock source. Including : + * - \ref CLK_CLKSEL1_CLKOSEL_HXT + * - \ref CLK_CLKSEL1_CLKOSEL_LXT + * - \ref CLK_CLKSEL1_CLKOSEL_HCLK + * - \ref CLK_CLKSEL1_CLKOSEL_HIRC + * @param[in] u32ClkDiv is divider output frequency selection. + * @param[in] u32ClkDivBy1En is frequency divided by one enable. + * @return None + * + * @details Output selected clock to CKO. The output clock frequency is divided by u32ClkDiv. + * The formula is: + * CKO frequency = (Clock source frequency) / 2^(u32ClkDiv + 1) + * This function is just used to set CKO clock. + * User must enable I/O for CKO clock output pin by themselves. + */ +void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En) +{ + /* CKO = clock source / 2^(u32ClkDiv + 1) */ + CLK->CLKOCTL = CLK_CLKOCTL_CLKOEN_Msk | u32ClkDiv | (u32ClkDivBy1En << CLK_CLKOCTL_DIV1EN_Pos); + + /* Enable CKO clock source */ + CLK->APBCLK0 |= CLK_APBCLK0_CLKOCKEN_Msk; + + /* Select CKO clock source */ + CLK->CLKSEL1 = (CLK->CLKSEL1 & (~CLK_CLKSEL1_CLKOSEL_Msk)) | (u32ClkSrc); + +} + +/** + * @brief Enter to Power-down mode + * @param None + * @return None + * @details This function is used to let system enter to Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_PowerDown(void) +{ + /* Set the processor uses deep sleep as its low power mode */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + + /* Set system Power-down enabled*/ + CLK->PWRCTL |= CLK_PWRCTL_PDEN_Msk; + + /* Chip enter Power-down mode after CPU run WFI instruction */ + __WFI(); +} + + + +/** + * @brief Enter to Idle mode + * @param None + * @return None + * @details This function let system enter to Idle mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_Idle(void) +{ + /* Set the processor uses sleep as its low power mode */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + + /* Set chip in idle mode because of WFI command */ + CLK->PWRCTL &= ~CLK_PWRCTL_PDEN_Msk; + + /* Chip enter idle mode after CPU run WFI instruction */ + __WFI(); +} + + +/** + * @brief Get external high speed crystal clock frequency + * @param None + * @return External high frequency crystal frequency + * @details This function get external high frequency crystal frequency. The frequency unit is Hz. + */ +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetHXTFreq(void) +{ + uint32_t u32Freq = 0UL; + uint32_t u32HXTEN = CLK->PWRCTL & CLK_PWRCTL_HXTEN_Msk; + + if(u32HXTEN) + { + u32Freq = __HXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get external low speed crystal clock frequency + * @param None + * @return External low speed crystal clock frequency + * @details This function get external low frequency crystal frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetLXTFreq(void) +{ + uint32_t u32Freq = 0UL; + uint32_t u32LXTEN = CLK->PWRCTL & CLK_PWRCTL_LXTEN_Msk; + + if(u32LXTEN) + { + u32Freq = __LXT; + } + else + { + u32Freq = 0UL; + } + + return u32Freq; +} + +/** + * @brief Get HCLK frequency + * @param None + * @return HCLK frequency + * @details This function get HCLK frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetHCLKFreq(void) +{ + SystemCoreClockUpdate(); + return SystemCoreClock; +} + +/** + * @brief Get PCLK0 frequency + * @param None + * @return PCLK0 frequency + * @details This function get PCLK0 frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetPCLK0Freq(void) +{ + SystemCoreClockUpdate(); + return (SystemCoreClock >> ((CLK->PCLKDIV & CLK_PCLKDIV_APB0DIV_Msk) >> CLK_PCLKDIV_APB0DIV_Pos)); +} + +/** + * @brief Get PCLK1 frequency + * @param None + * @return PCLK1 frequency + * @details This function get PCLK1 frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetPCLK1Freq(void) +{ + SystemCoreClockUpdate(); + return (SystemCoreClock >> ((CLK->PCLKDIV & CLK_PCLKDIV_APB1DIV_Msk) >> CLK_PCLKDIV_APB1DIV_Pos)); +} + +/** + * @brief Get CPU frequency + * @param None + * @return CPU frequency + * @details This function get CPU frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetCPUFreq(void) +{ + uint32_t u32Freq, u32HclkSrc, u32HclkDiv; + uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, 0UL, __HIRC}; + uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; + + /* Update PLL Clock */ + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) + { + PllClock = 0UL; /* PLL is in power down mode or fix low */ + } + else /* PLL is in normal mode */ + { + + /* PLL source clock */ + if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + /* Calculate PLL frequency */ + if(u32PllReg & CLK_PLLCTL_BP_Msk) + { + PllClock = u32FIN; /* PLL is in bypass mode */ + } + else + { + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + PllClock = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); + } + } + + /* HCLK clock source */ + u32HclkSrc = CLK->CLKSEL0 & CLK_CLKSEL0_HCLKSEL_Msk; + + if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_LXT) + { + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 |= CLK_APBCLK0_RTCCKEN_Msk; /* Enable RTC clock to get LXT clock source */ + } + + if(RTC->LXTCTL & RTC_LXTCTL_C32KS_Msk) + { + u32Freq = __LIRC32; /* LXT clock source is LIRC32 */ + } + else + { + u32Freq = __LXT; /* LXT clock source is external LXT */ + } + + if(u32RTCCKEN == 0UL) + { + CLK->APBCLK0 &= (~CLK_APBCLK0_RTCCKEN_Msk); /* Disable RTC clock if it is disabled before */ + } + + } + else if(u32HclkSrc == CLK_CLKSEL0_HCLKSEL_PLL) + { + u32Freq = PllClock;/* Use PLL clock */ + } + else + { + u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */ + } + + /* HCLK clock source divider */ + u32HclkDiv = (CLK->CLKDIV0 & CLK_CLKDIV0_HCLKDIV_Msk) + 1UL; + + /* Update System Core Clock */ + SystemCoreClock = u32Freq / u32HclkDiv; + + /* Update Cycles per micro second */ + CyclesPerUs = (SystemCoreClock + 500000UL) / 1000000UL; + + return SystemCoreClock; +} + +/** + * @brief Set HCLK frequency + * @param[in] u32Hclk is HCLK frequency. + * The range of u32Hclk is 24 MHz ~ 64 MHz if power level is PL0. + * The range of u32Hclk is 24 MHz ~ 48 MHz if power level is PL1. + * @return HCLK frequency + * @details This function is used to set HCLK frequency. The frequency unit is Hz. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_SetCoreClock(uint32_t u32Hclk) +{ + uint32_t u32HIRCSTB, u32PLSTATUS; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Read power level status */ + u32PLSTATUS = SYS->PLSTS & SYS_PLSTS_PLSTATUS_Msk; + + /* Check HCLK frequency range */ + if((u32PLSTATUS == SYS_PLSTS_PLSTATUS_PL0) && (u32Hclk > FREQ_64MHZ)) + { + u32Hclk = FREQ_64MHZ; + } + else if((u32PLSTATUS == SYS_PLSTS_PLSTATUS_PL1) && (u32Hclk > FREQ_48MHZ)) + { + u32Hclk = FREQ_48MHZ; + } + else if(u32Hclk < FREQ_24MHZ) + { + u32Hclk = FREQ_24MHZ; + } + + /* Switch HCLK clock source to HIRC clock for safe */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; + CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); + + /* Enable Flash access cycle auto-tuning function */ + FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk); + + /* Configure PLL setting if HXT clock is stable */ + if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk) + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HXT, u32Hclk); + } + /* Configure PLL setting if HXT clock is not stable */ + else + { + u32Hclk = CLK_EnablePLL(CLK_PLLCTL_PLLSRC_HIRC, u32Hclk); + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + } + + /* Select HCLK clock source to PLL, + Select HCLK clock source divider as 1 + and update system core clock + */ + CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); + + /* Disable HIRC if HIRC is disabled before setting core clock */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } + + /* Return actually HCLK frequency is PLL frequency divide 1 */ + return u32Hclk; +} + + +/** + * @brief Set HCLK clock source and HCLK clock divider + * @param[in] u32ClkSrc is HCLK clock source. Including : + * - \ref CLK_CLKSEL0_HCLKSEL_HXT + * - \ref CLK_CLKSEL0_HCLKSEL_LXT + * - \ref CLK_CLKSEL0_HCLKSEL_PLL + * - \ref CLK_CLKSEL0_HCLKSEL_LIRC + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC48 + * - \ref CLK_CLKSEL0_HCLKSEL_HIRC + * @param[in] u32ClkDiv is HCLK clock divider. Including : + * - \ref CLK_CLKDIV0_HCLK(x) + * @return None + * @details This function set HCLK clock source and HCLK clock divider. + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32HIRCSTB; + + /* Read HIRC clock source stable flag */ + u32HIRCSTB = CLK->STATUS & CLK_STATUS_HIRCSTB_Msk; + + /* Switch to HIRC for Safe. Avoid HCLK too high when applying new divider. */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; + + /* Enable Flash access cycle auto-tuning function */ + FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk); + + /* Apply new Divider */ + CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; + + /* Disable Flash access cycle auto-tuning function and set Flash access cycle if HCLK switches to HIRC48 */ + if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_HIRC48) + { + FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | FMC_CYCCTL_FADIS_Msk | (3UL); + } + + /* Switch HCLK to new HCLK source */ + CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; + + /* Update System Core Clock */ + SystemCoreClockUpdate(); + + /* Disable HIRC if HIRC is disabled before switching HCLK source */ + if(u32HIRCSTB == 0UL) + { + CLK->PWRCTL &= ~CLK_PWRCTL_HIRCEN_Msk; + } +} +/** + * @brief This function set selected module clock source and module clock divider + * @param[in] u32ModuleIdx is module index. + * @param[in] u32ClkSrc is module clock source. + * @param[in] u32ClkDiv is module clock divider. + * @return None + * @details Valid parameter combinations listed in following table: + * + * |Module index |Clock source |Divider | + * | :---------------- | :----------------------------------- | :----------------------- | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HXT |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_PLL |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HCLK |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref SDH0_MODULE |\ref CLK_CLKSEL0_SDH0SEL_HIRC |\ref CLK_CLKDIV0_SDH0(x) | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | + * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | + * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_PCLK0 | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_EXT_TRG | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LIRC | x | + * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LXT | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_PCLK0 | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_EXT_TRG | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_LIRC | x | + * |\ref TMR1_MODULE |\ref CLK_CLKSEL1_TMR1SEL_HIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LXT | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_PCLK1 | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_EXT_TRG | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_LIRC | x | + * |\ref TMR2_MODULE |\ref CLK_CLKSEL1_TMR2SEL_HIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LXT | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_PCLK1 | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_EXT_TRG | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_LIRC | x | + * |\ref TMR3_MODULE |\ref CLK_CLKSEL1_TMR3SEL_HIRC | x | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_PLL |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_LXT |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART0_MODULE |\ref CLK_CLKSEL1_UART0SEL_HIRC |\ref CLK_CLKDIV0_UART0(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_PLL |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_LXT |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART1_MODULE |\ref CLK_CLKSEL1_UART1SEL_HIRC |\ref CLK_CLKDIV0_UART1(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_PLL |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_LXT |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART2_MODULE |\ref CLK_CLKSEL3_UART2SEL_HIRC |\ref CLK_CLKDIV4_UART2(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_PLL |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_LXT |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART3_MODULE |\ref CLK_CLKSEL3_UART3SEL_HIRC |\ref CLK_CLKDIV4_UART3(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_PLL |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_LXT |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART4_MODULE |\ref CLK_CLKSEL3_UART4SEL_HIRC |\ref CLK_CLKDIV4_UART4(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_PLL |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_LXT |\ref CLK_CLKDIV4_UART5(x) | + * |\ref UART5_MODULE |\ref CLK_CLKSEL3_UART5SEL_HIRC |\ref CLK_CLKDIV4_UART5(x) | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_LXT | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HCLK | x | + * |\ref CLKO_MODULE |\ref CLK_CLKSEL1_CLKOSEL_HIRC | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 | x | + * |\ref WWDT_MODULE |\ref CLK_CLKSEL1_WWDTSEL_LIRC | x | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LXT | x | + * |\ref RTC_MODULE |\ref CLK_CLKSEL3_RTCSEL_LIRC | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HXT | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PLL | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_PCLK0 | x | + * |\ref I2S0_MODULE |\ref CLK_CLKSEL3_I2S0SEL_HIRC | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HXT | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PLL | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_PCLK0 | x | + * |\ref QSPI0_MODULE |\ref CLK_CLKSEL2_QSPI0SEL_HIRC | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HXT | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PLL | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_PCLK1 | x | + * |\ref SPI0_MODULE |\ref CLK_CLKSEL2_SPI0SEL_HIRC | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HXT | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PLL | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_PCLK0 | x | + * |\ref SPI1_MODULE |\ref CLK_CLKSEL2_SPI1SEL_HIRC | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HXT | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PLL | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_PCLK1 | x | + * |\ref SPI2_MODULE |\ref CLK_CLKSEL2_SPI2SEL_HIRC | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HXT | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | + * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HIRC |\ref CLK_CLKDIV1_SC0(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HXT |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PLL |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_PCLK1 |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) | + * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) | + * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | + */ +void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) +{ + uint32_t u32Sel = 0UL, u32Div = 0UL; + uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Apply new divider */ + M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; + } + + if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + /* Set new clock selection setting */ + M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; + } +} + +/** + * @brief Set SysTick clock source + * @param[in] u32ClkSrc is module clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * @return None + * @details This function set SysTick clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc) +{ + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; +} + +/** + * @brief Enable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48EN_Msk + * @return None + * @details This function enable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL |= u32ClkMask; +} + +/** + * @brief Disable clock source + * @param[in] u32ClkMask is clock source mask. Including : + * - \ref CLK_PWRCTL_HXTEN_Msk + * - \ref CLK_PWRCTL_LXTEN_Msk + * - \ref CLK_PWRCTL_HIRCEN_Msk + * - \ref CLK_PWRCTL_LIRCEN_Msk + * - \ref CLK_PWRCTL_HIRC48EN_Msk + * @return None + * @details This function disable clock source. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisableXtalRC(uint32_t u32ClkMask) +{ + CLK->PWRCTL &= ~u32ClkMask; +} + +/** + * @brief This function enable module clock + * @param[in] u32ModuleIdx is module index. Including : + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CRPT_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI0_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * @return None + * @details This function enable module clock. + */ +void CLK_EnableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK; + u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(volatile uint32_t *)u32TmpAddr |= u32TmpVal; +} + +/** + * @brief This function disable module clock + * @param[in] u32ModuleIdx is module index + * - \ref PDMA0_MODULE + * - \ref PDMA1_MODULE + * - \ref ISP_MODULE + * - \ref EBI_MODULE + * - \ref SDH0_MODULE + * - \ref CRC_MODULE + * - \ref CRPT_MODULE + * - \ref FMCIDLE_MODULE + * - \ref USBH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref ACMP01_MODULE + * - \ref I2C0_MODULE + * - \ref I2C1_MODULE + * - \ref I2C2_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref CAN0_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref EADC_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref USCI0_MODULE + * - \ref USCI1_MODULE + * - \ref DAC_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * - \ref QEI0_MODULE + * - \ref QEI1_MODULE + * - \ref QEI0_MODULE + * - \ref TRNG_MODULE + * - \ref ECAP0_MODULE + * - \ref ECAP1_MODULE + * @return None + * @details This function disable module clock. + */ +void CLK_DisableModuleClock(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); + u32TmpAddr = (uint32_t)&CLK->AHBCLK; + u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); + + *(uint32_t *)u32TmpAddr &= u32TmpVal; +} + + +/** + * @brief Set PLL frequency + * @param[in] u32PllClkSrc is PLL clock source. Including : + * - \ref CLK_PLLCTL_PLLSRC_HXT + * - \ref CLK_PLLCTL_PLLSRC_HIRC + * @param[in] u32PllFreq is PLL frequency. The range of u32PllFreq is 24 MHz ~ 144 MHz. + * @return PLL frequency + * @details This function is used to configure PLLCTL register to set specified PLL frequency. \n + * The register write-protection function should be disabled before using this function. + */ +uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq) +{ + uint32_t u32PllSrcClk, u32NR, u32NF, u32NO, u32PllClk; + uint32_t u32Tmp, u32Tmp2, u32Tmp3, u32Min, u32MinNF, u32MinNR; + + /* Disable PLL first to avoid unstable when setting PLL */ + CLK_DisablePLL(); + + /* PLL source clock is from HXT */ + if(u32PllClkSrc == CLK_PLLCTL_PLLSRC_HXT) + { + + /* Enable HXT clock */ + CLK->PWRCTL |= CLK_PWRCTL_HXTEN_Msk; + + /* Wait for HXT clock ready */ + CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk); + + /* Select PLL source clock from HXT */ + u32PllSrcClk = __HXT; + } + + /* PLL source clock is from HIRC */ + else + { + + /* Enable HIRC clock */ + CLK->PWRCTL |= CLK_PWRCTL_HIRCEN_Msk; + + /* Wait for HIRC clock ready */ + CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); + + /* Select PLL source clock from HIRC */ + u32PllSrcClk = __HIRC; + } + + /* Check PLL frequency range */ + if((u32PllFreq <= FREQ_144MHZ) && (u32PllFreq >= FREQ_24MHZ)) + { + + /* Select "NO" according to request frequency */ + if((u32PllFreq < FREQ_48MHZ) && (u32PllFreq >= FREQ_24MHZ)) + { + u32NO = 3UL; + u32PllFreq = u32PllFreq << 2; + } + else if((u32PllFreq < FREQ_96MHZ) && (u32PllFreq >= FREQ_48MHZ)) + { + u32NO = 1UL; + u32PllFreq = u32PllFreq << 1; + } + else + { + u32NO = 0UL; + } + + /* u32NR start from 3 to avoid calculation overflow */ + u32NR = 3UL; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinNR = 0UL; + u32MinNF = 0UL; + + for(; u32NR <= 32UL; u32NR++) + { + u32Tmp = u32PllSrcClk / u32NR; + if((u32Tmp >= FREQ_2MHZ) && (u32Tmp <= FREQ_8MHZ)) + { + for(u32NF = 2UL; u32NF <= 513UL; u32NF++) + { + u32Tmp2 = (u32Tmp * u32NF) << 1; + if((u32Tmp2 >= FREQ_96MHZ) && (u32Tmp2 <= FREQ_200MHZ)) + { + u32Tmp3 = (u32Tmp2 > u32PllFreq) ? u32Tmp2 - u32PllFreq : u32PllFreq - u32Tmp2; + if(u32Tmp3 < u32Min) + { + u32Min = u32Tmp3; + u32MinNR = u32NR; + u32MinNF = u32NF; + + /* Break when get good results */ + if(u32Min == 0UL) + { + break; + } + } + } + } + } + } + + /* Enable and apply new PLL setting. */ + CLK->PLLCTL = u32PllClkSrc | (u32NO << 14) | ((u32MinNR - 1UL) << 9) | (u32MinNF - 2UL); + + /* Actual PLL output clock frequency */ + u32PllClk = u32PllSrcClk / ((u32NO + 1UL) * u32MinNR) * (u32MinNF << 1); + + } + else + { + + /* Wrong frequency request. Just return default setting. */ + if((SYS->PLSTS & SYS_PLSTS_PLSTATUS_Msk) == SYS_PLCTL_PLSEL_PL0) + { + + /* Apply default PLL setting and return */ + CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_64MHz_HXT; + + /* Actual PLL output clock frequency */ + u32PllClk = FREQ_64MHZ; + + } + else + { + + /* Apply default PLL setting and return */ + CLK->PLLCTL = u32PllClkSrc | CLK_PLLCTL_48MHz_HXT; + + /* Actual PLL output clock frequency */ + u32PllClk = FREQ_48MHZ; + } + + } + + /* Wait for PLL clock stable */ + CLK_WaitClockReady(CLK_STATUS_PLLSTB_Msk); + + /* Return actual PLL output clock frequency */ + return u32PllClk; +} + +/** + * @brief Disable PLL + * @param None + * @return None + * @details This function set PLL in Power-down mode. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_DisablePLL(void) +{ + CLK->PLLCTL |= CLK_PLLCTL_PD_Msk; +} + +/** + * @brief This function check selected clock source status + * @param[in] u32ClkMask is selected clock source. Including : + * - \ref CLK_STATUS_HXTSTB_Msk + * - \ref CLK_STATUS_LXTSTB_Msk + * - \ref CLK_STATUS_HIRCSTB_Msk + * - \ref CLK_STATUS_LIRCSTB_Msk + * - \ref CLK_STATUS_PLLSTB_Msk + * - \ref CLK_STATUS_HIRC48STB_Msk + * - \ref CLK_STATUS_EXTLXTSTB_Msk + * - \ref CLK_STATUS_LIRC32STB_Msk + * @retval 0 clock is not stable + * @retval 1 clock is stable + * @details To wait for clock ready by specified clock source stable flag or timeout (~300ms) + */ +uint32_t CLK_WaitClockReady(uint32_t u32ClkMask) +{ + int32_t i32TimeOutCnt = 2400000; + uint32_t u32Ret = 1U; + + while((CLK->STATUS & u32ClkMask) != u32ClkMask) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; + break; + } + } + return u32Ret; +} + +/** + * @brief Enable System Tick counter + * @param[in] u32ClkSrc is System Tick clock source. Including: + * - \ref CLK_CLKSEL0_STCLKSEL_HXT + * - \ref CLK_CLKSEL0_STCLKSEL_LXT + * - \ref CLK_CLKSEL0_STCLKSEL_HXT_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 + * - \ref CLK_CLKSEL0_STCLKSEL_HCLK + * @param[in] u32Count is System Tick reload value. It could be 0~0xFFFFFF. + * @return None + * @details This function set System Tick clock source, reload value, enable System Tick counter and interrupt. \n + * The register write-protection function should be disabled before using this function. + */ +void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; + + /* Set System Tick clock source */ + if(u32ClkSrc == CLK_CLKSEL0_STCLKSEL_HCLK) + { + SysTick->CTRL |= SysTick_CTRL_CLKSOURCE_Msk; + } + else + { + CLK->CLKSEL0 = (CLK->CLKSEL0 & ~CLK_CLKSEL0_STCLKSEL_Msk) | u32ClkSrc; + } + + /* Set System Tick reload value */ + SysTick->LOAD = u32Count; + + /* Clear System Tick current value and counter flag */ + SysTick->VAL = 0UL; + + /* Set System Tick interrupt enabled and counter enabled */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; +} + +/** + * @brief Disable System Tick counter + * @param None + * @return None + * @details This function disable System Tick counter. + */ +void CLK_DisableSysTick(void) +{ + /* Set System Tick counter disabled */ + SysTick->CTRL = 0UL; +} + +/** + * @brief Power-down mode selected + * @param[in] u32PDMode is power down mode index. Including : + * - \ref CLK_PMUCTL_PDMSEL_PD + * - \ref CLK_PMUCTL_PDMSEL_LLPD + * - \ref CLK_PMUCTL_PDMSEL_FWPD + * - \ref CLK_PMUCTL_PDMSEL_ULLPD + * - \ref CLK_PMUCTL_PDMSEL_SPD + * - \ref CLK_PMUCTL_PDMSEL_DPD + * @return None + * @details This function is used to set power-down mode. + */ +void CLK_SetPowerDownMode(uint32_t u32PDMode) +{ + CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_PDMSEL_Msk)) | (u32PDMode); +} + +/** + * @brief Set Wake-up pin trigger type at Deep Power down mode + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_DPDWKPIN_RISING + * - \ref CLK_DPDWKPIN_FALLING + * - \ref CLK_DPDWKPIN_BOTHEDGE + * @return None + * @details This function is used to enable Wake-up pin trigger type. + */ + +void CLK_EnableDPDWKPin(uint32_t u32TriggerType) +{ + CLK->PMUCTL = (CLK->PMUCTL & (~CLK_PMUCTL_WKPINEN_Msk)) | (u32TriggerType); +} + +/** + * @brief Get power manager wake up source + * @param[in] None + * @return None + * @details This function get power manager wake up source. + */ + +uint32_t CLK_GetPMUWKSrc(void) +{ + return (CLK->PMUSTS); +} + +/** + * @brief Set specified GPIO as wake up source at Standby Power-down mode + * @param[in] u32Port GPIO port. It could be 0~3. + * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. + * @param[in] u32TriggerType Wake-up pin trigger type + * - \ref CLK_SPDWKPIN_RISING + * - \ref CLK_SPDWKPIN_FALLING + * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function + * - \ref CLK_SPDWKPIN_DEBOUNCEEN + * - \ref CLK_SPDWKPIN_DEBOUNCEDIS + * @return None + * @details This function is used to set specified GPIO as wake up source at Standby Power-down mode. + */ + +void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) +{ + uint32_t u32TmpAddr = 0UL; + uint32_t u32TmpVal = 0UL; + + /* GPx Stand-by Power-down Wake-up Pin Select */ + u32TmpAddr = (uint32_t)&CLK->PASWKCTL; + u32TmpAddr += (0x4UL * u32Port); + + u32TmpVal = inpw((uint32_t *)u32TmpAddr); + u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | + (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; + outpw((uint32_t *)u32TmpAddr, u32TmpVal); +} + +/** + * @brief Get PLL clock frequency + * @param None + * @return PLL frequency + * @details This function get PLL frequency. The frequency unit is Hz. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetPLLClockFreq(void) +{ + uint32_t u32PllFreq = 0UL, u32PllReg; + uint32_t u32FIN, u32NF, u32NR, u32NO; + uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; + + u32PllReg = CLK->PLLCTL; + + if(u32PllReg & (CLK_PLLCTL_PD_Msk | CLK_PLLCTL_OE_Msk)) + { + u32PllFreq = 0UL; /* PLL is in power down mode or fix low */ + } + else /* PLL is in normal mode */ + { + + /* PLL source clock */ + if(u32PllReg & CLK_PLLCTL_PLLSRC_Msk) + { + u32FIN = __HIRC; /* PLL source clock from HIRC */ + } + else + { + u32FIN = __HXT; /* PLL source clock from HXT */ + } + + /* Calculate PLL frequency */ + if(u32PllReg & CLK_PLLCTL_BP_Msk) + { + u32PllFreq = u32FIN; /* PLL is in bypass mode */ + } + else + { + /* PLL is output enabled in normal work mode */ + u32NO = au8NoTbl[((u32PllReg & CLK_PLLCTL_OUTDIV_Msk) >> CLK_PLLCTL_OUTDIV_Pos)]; + u32NF = ((u32PllReg & CLK_PLLCTL_FBDIV_Msk) >> CLK_PLLCTL_FBDIV_Pos) + 2UL; + u32NR = ((u32PllReg & CLK_PLLCTL_INDIV_Msk) >> CLK_PLLCTL_INDIV_Pos) + 1UL; + + /* u32FIN is shifted 2 bits to avoid overflow */ + u32PllFreq = (((u32FIN >> 2) * (u32NF << 1)) / (u32NR * u32NO) << 2); + } + } + + return u32PllFreq; +} + +/** + * @brief Get selected module clock source + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref USBH_MODULE + * - \ref WDT_MODULE + * - \ref WWDT_MODULE + * - \ref RTC_MODULE + * - \ref TMR0_MODULE + * - \ref TMR1_MODULE + * - \ref TMR2_MODULE + * - \ref TMR3_MODULE + * - \ref CLKO_MODULE + * - \ref QSPI0_MODULE + * - \ref SPI0_MODULE + * - \ref SPI1_MODULE + * - \ref SPI2_MODULE + * - \ref SPI3_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref I2S0_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EPWM0_MODULE + * - \ref EPWM1_MODULE + * - \ref BPWM0_MODULE + * - \ref BPWM1_MODULE + * @return Selected module clock source setting + * @details This function get selected module clock source. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; + + /* Get clock source selection setting */ + if(u32ModuleIdx == EPWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); + } + else if(u32ModuleIdx == EPWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); + } + else if(u32ModuleIdx == BPWM0_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); + } + else if(u32ModuleIdx == BPWM1_MODULE) + { + u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); + } + else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock select control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); + + /* Get clock source selection setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} + +/** + * @brief Get selected module clock divider number + * @param[in] u32ModuleIdx is module index. + * - \ref SDH0_MODULE + * - \ref USBH_MODULE + * - \ref UART0_MODULE + * - \ref UART1_MODULE + * - \ref UART2_MODULE + * - \ref UART3_MODULE + * - \ref UART4_MODULE + * - \ref UART5_MODULE + * - \ref OTG_MODULE + * - \ref USBD_MODULE + * - \ref SC0_MODULE + * - \ref SC1_MODULE + * - \ref SC2_MODULE + * - \ref EADC_MODULE + * @return Selected module clock divider number setting + * @details This function get selected module clock divider number. + */ + +__NONSECURE_ENTRY_WEAK +uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; + + if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) + { + /* Get clock divider control register address */ + u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); + /* Get clock divider number setting */ + u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); + } + + return u32TmpVal; +} + + +/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CLK_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/crc.c b/arch/riscv32/fe310/src/StdDriver/src/crc.c new file mode 100644 index 00000000..ae2b0e97 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/crc.c @@ -0,0 +1,119 @@ +/**************************************************************************//** + * @file crc.c + * @version V3.00 + * @brief Cyclic Redundancy Check(CRC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRC_Driver CRC Driver + @{ +*/ + +/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions + @{ +*/ + +/** + * @brief CRC Open + * + * @param[in] u32Mode CRC operation polynomial mode. Valid values are: + * - \ref CRC_CCITT + * - \ref CRC_8 + * - \ref CRC_16 + * - \ref CRC_32 + * @param[in] u32Attribute CRC operation data attribute. Valid values are combined with: + * - \ref CRC_CHECKSUM_COM + * - \ref CRC_CHECKSUM_RVS + * - \ref CRC_WDATA_COM + * - \ref CRC_WDATA_RVS + * @param[in] u32Seed Seed value. + * @param[in] u32DataLen CPU Write Data Length. Valid values are: + * - \ref CRC_CPU_WDATA_8 + * - \ref CRC_CPU_WDATA_16 + * - \ref CRC_CPU_WDATA_32 + * + * @return None + * + * @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n + * After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly. + */ +void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen) +{ + CRC_T *pCRC; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pCRC = CRC_NS; + } + else + { + pCRC = CRC; + } + + pCRC->SEED = u32Seed; + pCRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk; + + /* Setting CHKSINIT bit will reload the initial seed value(CRC_SEED register) to CRC controller */ + pCRC->CTL |= CRC_CTL_CHKSINIT_Msk; +} + +/** + * @brief Get CRC Checksum + * + * @param[in] None + * + * @return Checksum Result + * + * @details This macro gets the CRC checksum result by current CRC polynomial mode. + */ +uint32_t CRC_GetChecksum(void) +{ + CRC_T *pCRC; + uint32_t u32Checksum = 0UL; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pCRC = CRC_NS; + } + else + { + pCRC = CRC; + } + + switch(pCRC->CTL & CRC_CTL_CRCMODE_Msk) + { + case CRC_CCITT: + case CRC_16: + u32Checksum = (pCRC->CHECKSUM & 0xFFFFUL); + break; + + case CRC_32: + u32Checksum = pCRC->CHECKSUM; + break; + + case CRC_8: + u32Checksum = (pCRC->CHECKSUM & 0xFFUL); + break; + + default: + break; + } + + return u32Checksum; +} + +/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/crypto.c b/arch/riscv32/fe310/src/StdDriver/src/crypto.c new file mode 100644 index 00000000..a1a22677 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/crypto.c @@ -0,0 +1,3489 @@ +/**************************************************************************//** + * @file crypto.c + * @version V1.10 + * @brief Cryptographic Accelerator driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include +#include "M2351.h" + +#define ENABLE_DEBUG 0 +#define XOM_SUPPORT 0 + +#if ENABLE_DEBUG +#define CRPT_DBGMSG printf +#else +#define CRPT_DBGMSG(...) do { } while (0) /* disable debug */ +#endif + +#if defined(__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup CRYPTO_Driver CRYPTO Driver + @{ +*/ + + +/** @addtogroup CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions + @{ +*/ + +/* // @cond HIDDEN_SYMBOLS */ + +static uint32_t g_AES_CTL[4]; +static uint32_t g_TDES_CTL[4]; + +static char hex_char_tbl[] = "0123456789abcdef"; + +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count); +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx); +static void Hex2Reg(char input[], uint32_t volatile reg[]); +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]); +static char ch2hex(char ch); +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift); +static int get_nibble_value(char c); + +/* // @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Open PRNG function + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32KeySize it is PRNG key size, including: + * - \ref PRNG_KEY_SIZE_64 + * - \ref PRNG_KEY_SIZE_128 + * - \ref PRNG_KEY_SIZE_192 + * - \ref PRNG_KEY_SIZE_256 + * @param[in] u32SeedReload is PRNG seed reload or not, including: + * - \ref PRNG_SEED_CONT + * - \ref PRNG_SEED_RELOAD + * @param[in] u32Seed The new seed. Only valid when u32SeedReload is PRNG_SEED_RELOAD. + * @return None + */ +void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed) +{ + if(u32SeedReload) + { + crpt->PRNG_SEED = u32Seed; + } + + crpt->PRNG_CTL = (u32KeySize << CRPT_PRNG_CTL_KEYSZ_Pos) | + (u32SeedReload << CRPT_PRNG_CTL_SEEDRLD_Pos); +} + +/** + * @brief Start to generate one PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @return None + */ +void PRNG_Start(CRPT_T *crpt) +{ + crpt->PRNG_CTL |= CRPT_PRNG_CTL_START_Msk; +} + +/** + * @brief Read the PRNG key. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32RandKey The key buffer to store newly generated PRNG key. + * @return None + */ +void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]) +{ + uint32_t i, wcnt; + + wcnt = (((crpt->PRNG_CTL & CRPT_PRNG_CTL_KEYSZ_Msk) >> CRPT_PRNG_CTL_KEYSZ_Pos) + 1U) * 2U; + + for(i = 0U; i < wcnt; i++) + { + u32RandKey[i] = crpt->PRNG_KEY[i]; + } + + crpt->PRNG_CTL &= ~CRPT_PRNG_CTL_SEEDRLD_Msk; +} + + +/** + * @brief Open AES encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32EncDec 1: AES encode; 0: AES decode + * @param[in] u32OpMode AES operation mode, including: + * - \ref AES_MODE_ECB + * - \ref AES_MODE_CBC + * - \ref AES_MODE_CFB + * - \ref AES_MODE_OFB + * - \ref AES_MODE_CTR + * - \ref AES_MODE_CBC_CS1 + * - \ref AES_MODE_CBC_CS2 + * - \ref AES_MODE_CBC_CS3 + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @param[in] u32SwapType is AES input/output data swap control, including: + * - \ref AES_NO_SWAP + * - \ref AES_OUT_SWAP + * - \ref AES_IN_SWAP + * - \ref AES_IN_OUT_SWAP + * @return None + */ +void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, + uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType) +{ + crpt->AES_CTL = (u32Channel << CRPT_AES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_AES_CTL_ENCRPT_Pos) | + (u32OpMode << CRPT_AES_CTL_OPMODE_Pos) | + (u32KeySize << CRPT_AES_CTL_KEYSZ_Pos) | + (u32SwapType << CRPT_AES_CTL_OUTSWAP_Pos); + g_AES_CTL[u32Channel] = crpt->AES_CTL; +} + +/** + * @brief Start AES encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32DMAMode AES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop AES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous AES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last AES encrypt/decrypt of a series of AES_Start. + * @return None + */ +void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + crpt->AES_CTL = g_AES_CTL[u32Channel]; + crpt->AES_CTL |= CRPT_AES_CTL_START_Msk | (u32DMAMode << CRPT_AES_CTL_DMALAST_Pos); +} + +/** + * @brief Set AES keys + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32Keys An word array contains AES keys. + * @param[in] u32KeySize is AES key size, including: + * - \ref AES_KEY_SIZE_128 + * - \ref AES_KEY_SIZE_192 + * - \ref AES_KEY_SIZE_256 + * @return None + */ +void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize) +{ + uint32_t i, wcnt, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_KEY[0] + (u32Channel * 0x3CUL); + wcnt = 4UL + u32KeySize * 2UL; + + for(i = 0U; i < wcnt; i++) + { + outpw(key_reg_addr, au32Keys[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES initial vectors + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] au32IV A four entry word array contains AES initial vectors. + * @return None + */ +void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]) +{ + uint32_t i, key_reg_addr; + + key_reg_addr = (uint32_t)&crpt->AES0_IV[0] + (u32Channel * 0x3CUL); + + for(i = 0U; i < 4U; i++) + { + outpw(key_reg_addr, au32IV[i]); + key_reg_addr += 4UL; + } +} + +/** + * @brief Set AES DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel AES channel. Must be 0~3. + * @param[in] u32SrcAddr AES DMA source address + * @param[in] u32DstAddr AES DMA destination address + * @param[in] u32TransCnt AES DMA transfer byte count + * @return None + */ +void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->AES0_SADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->AES0_DADDR + (u32Channel * 0x3CUL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->AES0_CNT + (u32Channel * 0x3CUL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open TDES encrypt/decrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32EncDec 1: TDES encode; 0: TDES decode + * @param[in] Is3DES 1: TDES; 0: DES + * @param[in] Is3Key 1: TDES 3 key mode; 0: TDES 2 key mode + * @param[in] u32OpMode TDES operation mode, including: + * - \ref TDES_MODE_ECB + * - \ref TDES_MODE_CBC + * - \ref TDES_MODE_CFB + * - \ref TDES_MODE_OFB + * - \ref TDES_MODE_CTR + * @param[in] u32SwapType is TDES input/output data swap control and word swap control, including: + * - \ref TDES_NO_SWAP + * - \ref TDES_WHL_SWAP + * - \ref TDES_OUT_SWAP + * - \ref TDES_OUT_WHL_SWAP + * - \ref TDES_IN_SWAP + * - \ref TDES_IN_WHL_SWAP + * - \ref TDES_IN_OUT_SWAP + * - \ref TDES_IN_OUT_WHL_SWAP + * @return None + */ +void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, + uint32_t u32OpMode, uint32_t u32SwapType) +{ + (void)crpt; + g_TDES_CTL[u32Channel] = (u32Channel << CRPT_TDES_CTL_CHANNEL_Pos) | + (u32EncDec << CRPT_TDES_CTL_ENCRPT_Pos) | + u32OpMode | (u32SwapType << CRPT_TDES_CTL_BLKSWAP_Pos); + if(Is3DES) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_TMODE_Msk; + } + if(Is3Key) + { + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_3KEYS_Msk; + } +} + +/** + * @brief Start TDES encrypt/decrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous TDES encrypt/decrypt. + * - \ref CRYPTO_DMA_LAST Last TDES encrypt/decrypt of a series of TDES_Start. + * @return None + */ +void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode) +{ + g_TDES_CTL[u32Channel] |= CRPT_TDES_CTL_START_Msk | (u32DMAMode << CRPT_TDES_CTL_DMALAST_Pos); + crpt->TDES_CTL = g_TDES_CTL[u32Channel]; +} + +/** + * @brief Set TDES keys + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] au32Keys The TDES keys. au32Keys[0][0] is Key0 high word and au32Keys[0][1] is key0 low word. + * @return None + */ +void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]) +{ + uint32_t i, reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_KEY1H + (0x40UL * u32Channel); + + for(i = 0U; i < 3U; i++) + { + outpw(reg_addr, au32Keys[i][0]); /* TDESn_KEYxH */ + reg_addr += 4UL; + outpw(reg_addr, au32Keys[i][1]); /* TDESn_KEYxL */ + reg_addr += 4UL; + } +} + +/** + * @brief Set TDES initial vectors + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32IVH TDES initial vector high word. + * @param[in] u32IVL TDES initial vector low word. + * @return None + */ +void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_IVH + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVH); + + reg_addr = (uint32_t)&crpt->TDES0_IVL + (u32Channel * 0x40UL); + outpw(reg_addr, u32IVL); +} + +/** + * @brief Set TDES DMA transfer configuration. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32Channel TDES channel. Must be 0~3. + * @param[in] u32SrcAddr TDES DMA source address + * @param[in] u32DstAddr TDES DMA destination address + * @param[in] u32TransCnt TDES DMA transfer byte count + * @return None + */ +void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, + uint32_t u32DstAddr, uint32_t u32TransCnt) +{ + uint32_t reg_addr; + + reg_addr = (uint32_t)&crpt->TDES0_SADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32SrcAddr); + + reg_addr = (uint32_t)&crpt->TDES0_DADDR + (u32Channel * 0x40UL); + outpw(reg_addr, u32DstAddr); + + reg_addr = (uint32_t)&crpt->TDES0_CNT + (u32Channel * 0x40UL); + outpw(reg_addr, u32TransCnt); +} + +/** + * @brief Open SHA encrypt function. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32OpMode SHA operation mode, including: + * - \ref SHA_MODE_SHA1 + * - \ref SHA_MODE_SHA224 + * - \ref SHA_MODE_SHA256 + * @param[in] u32SwapType is SHA input/output data swap control, including: + * - \ref SHA_NO_SWAP + * - \ref SHA_OUT_SWAP + * - \ref SHA_IN_SWAP + * - \ref SHA_IN_OUT_SWAP + * @param[in] hmac_key_len HMAC key byte count + * @return None + */ +void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len) +{ + crpt->HMAC_CTL = (u32OpMode << CRPT_HMAC_CTL_OPMODE_Pos) | + (u32SwapType << CRPT_HMAC_CTL_OUTSWAP_Pos); + + if(hmac_key_len != 0UL) + { + crpt->HMAC_KEYCNT = hmac_key_len; + } +} + +/** + * @brief Start SHA encrypt + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32DMAMode TDES DMA control, including: + * - \ref CRYPTO_DMA_ONE_SHOT One shop SHA encrypt. + * - \ref CRYPTO_DMA_CONTINUE Continuous SHA encrypt. + * - \ref CRYPTO_DMA_LAST Last SHA encrypt of a series of SHA_Start. + * @return None + */ +void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode) +{ + crpt->HMAC_CTL &= ~(0x7UL << CRPT_HMAC_CTL_DMALAST_Pos); + crpt->HMAC_CTL |= CRPT_HMAC_CTL_START_Msk | (u32DMAMode << CRPT_HMAC_CTL_DMALAST_Pos); +} + +/** + * @brief Set SHA DMA transfer + * @param[in] crpt The pointer of CRYPTO module + * @param[in] u32SrcAddr SHA DMA source address + * @param[in] u32TransCnt SHA DMA transfer byte count + * @return None + */ +void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt) +{ + crpt->HMAC_SADDR = u32SrcAddr; + crpt->HMAC_DMACNT = u32TransCnt; +} + +/** + * @brief Read the SHA digest. + * @param[in] crpt The pointer of CRYPTO module + * @param[out] u32Digest The SHA encrypt output digest. + * @return None + */ +void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]) +{ + uint32_t i, wcnt, reg_addr; + + i = (crpt->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos; + + if(i == SHA_MODE_SHA1) + { + wcnt = 5UL; + } + else if(i == SHA_MODE_SHA224) + { + wcnt = 7UL; + } + else if(i == SHA_MODE_SHA256) + { + wcnt = 8UL; + } + else if(i == SHA_MODE_SHA384) + { + wcnt = 12UL; + } + else + { + /* SHA_MODE_SHA512 */ + wcnt = 16UL; + } + + reg_addr = (uint32_t) & (crpt->HMAC_DGST[0]); + for(i = 0UL; i < wcnt; i++) + { + u32Digest[i] = inpw(reg_addr); + reg_addr += 4UL; + } +} + + +/*-----------------------------------------------------------------------------------------------*/ +/* */ +/* ECC */ +/* */ +/*-----------------------------------------------------------------------------------------------*/ + +#define ECCOP_POINT_MUL (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_MODULE (0x1UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_ADD (0x2UL << CRPT_ECC_CTL_ECCOP_Pos) +#define ECCOP_POINT_DOUBLE (0x0UL << CRPT_ECC_CTL_ECCOP_Pos) + +#define MODOP_DIV (0x0UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_MUL (0x1UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_ADD (0x2UL << CRPT_ECC_CTL_MODOP_Pos) +#define MODOP_SUB (0x3UL << CRPT_ECC_CTL_MODOP_Pos) + +enum +{ + CURVE_GF_P, + CURVE_GF_2M, +}; + +/*-----------------------------------------------------*/ +/* Define elliptic curve (EC): */ +/*-----------------------------------------------------*/ +#if !XOM_SUPPORT // Replace with XOM ready curve table +static const ECC_CURVE _Curve[] = +{ + { + /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ + CURVE_P_192, + 48, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFC", /* "000000000000000000000000000000000000000000000003" */ + "64210519e59c80e70fa7e9ab72243049feb8deecc146b9b1", + "188da80eb03090f67cbf20eb43a18800f4ff0afd82ff1012", + "07192b95ffc8da78631011ed6b24cdd573f977a11e794811", + 58, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFF", /* "6277101735386680763835789423207666416083908700390324961279" */ + 58, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFF99DEF836146BC9B1B4D22831", /* "6277101735386680763835789423176059013767194773182842284081" */ + 192, /* key_len */ + 7, + 2, + 1, + CURVE_GF_P + }, + { + /* NIST: Curve P-224 : y^2=x^3-ax+b (mod p) */ + CURVE_P_224, + 56, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFE", /* "00000000000000000000000000000000000000000000000000000003" */ + "b4050a850c04b3abf54132565044b0b7d7bfd8ba270b39432355ffb4", + "b70e0cbd6bb4bf7f321390b94a03c1d356c21122343280d6115c1d21", + "bd376388b5f723fb4c22dfe6cd4375a05a07476444d5819985007e34", + 70, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "0026959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFF16A2E0B8F03E13DD29455C5C2A3D", /* "0026959946667150639794667015087019625940457807714424391721682722368061" */ + 224, /* key_len */ + 9, + 8, + 3, + CURVE_GF_P + }, + { + /* NIST: Curve P-256 : y^2=x^3-ax+b (mod p) */ + CURVE_P_256, + 64, /* Echar */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFC", /* "0000000000000000000000000000000000000000000000000000000000000003" */ + "5ac635d8aa3a93e7b3ebbd55769886bc651d06b0cc53b0f63bce3c3e27d2604b", + "6b17d1f2e12c4247f8bce6e563a440f277037d812deb33a0f4a13945d898c296", + "4fe342e2fe1a7f9b8ee7eb4a7c0f9e162bce33576b315ececbb6406837bf51f5", + 78, /* Epl */ + "FFFFFFFF00000001000000000000000000000000FFFFFFFFFFFFFFFFFFFFFFFF", /* "115792089210356248762697446949407573530086143415290314195533631308867097853951" */ + 78, /* Eol */ + "FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551", /* "115792089210356248762697446949407573529996955224135760342422259061068512044369" */ + 256, /* key_len */ + 10, + 5, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-384 : y^2=x^3-ax+b (mod p) */ + CURVE_P_384, + 96, /* Echar */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFC", /* "000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "b3312fa7e23ee7e4988e056be3f82d19181d9c6efe8141120314088f5013875ac656398d8a2ed19d2a85c8edd3ec2aef", + "aa87ca22be8b05378eb1c71ef320ad746e1d3b628ba79b9859f741e082542a385502f25dbf55296c3a545e3872760ab7", + "3617de4a96262c6f5d9e98bf9292dc29f8f41dbd289a147ce9da3113b5f0b8c00a60b1ce1d7e819d7a431d7c90ea0e5f", + 116, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEFFFFFFFF0000000000000000FFFFFFFF", /* "39402006196394479212279040100143613805079739270465446667948293404245721771496870329047266088258938001861606973112319" */ + 116, /* Eol */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC7634D81F4372DDF581A0DB248B0A77AECEC196ACCC52973", /* "39402006196394479212279040100143613805079739270465446667946905279627659399113263569398956308152294913554433653942643" */ + 384, /* key_len */ + 12, + 3, + 2, + CURVE_GF_P + }, + { + /* NIST: Curve P-521 : y^2=x^3-ax+b (mod p)*/ + CURVE_P_521, + 131, /* Echar */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFC", /* "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000003" */ + "051953eb9618e1c9a1f929a21a0b68540eea2da725b99b315f3b8b489918ef109e156193951ec7e937b1652c0bd3bb1bf073573df883d2c34f1ef451fd46b503f00", + "0c6858e06b70404e9cd9e3ecb662395b4429c648139053fb521f828af606b4d3dbaa14b5e77efe75928fe1dc127a2ffa8de3348b3c1856a429bf97e7e31c2e5bd66", + "11839296a789a3bc0045c8a5fb42c7d1bd998f54449579b446817afbd17273e662c97ee72995ef42640c550b9013fad0761353c7086a272c24088be94769fd16650", + 157, /* Epl */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397656052122559640661454554977296311391480858037121987999716643812574028291115057151" */ + 157, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFA51868783BF2F966B7FCC0148F709A5D03BB5C9B8899C47AEBB6FB71E91386409", /* "6864797660130609714981900799081393217269435300143305409394463459185543183397655394245057746333217197532963996371363321113864768612440380340372808892707005449" */ + 521, /* key_len */ + 32, + 32, + 32, + CURVE_GF_P + }, + { + /* NIST: Curve B-163 : y^2+xy=x^3+ax^2+b */ + CURVE_B_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "20a601907b8c953ca1481eb10512f78744a3205fd", + "3f0eba16286a2d57ea0991168d4994637e8343e36", + "0d51fbc6c71a0094fa2cdd545b11c5c0c797324f1", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "40000000000000000000292FE77E70C12A4234C33", /* "5846006549323611672814742442876390689256843201587" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve B-233 : y^2+xy=x^3+ax^2+b */ + CURVE_B_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000001", + "066647ede6c332c7f8c0923bb58213b333b20e9ce4281fe115f7d8f90ad", + "0fac9dfcbac8313bb2139f1bb755fef65bc391f8b36f8f8eb7371fd558b", + "1006a08a41903350678e58528bebf8a0beff867a7ca36716f7e01f81052", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "1000000000000000000000000000013E974E72F8A6922031D2603CFE0D7", /* "6901746346790563787434755862277025555839812737345013555379383634485463" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve B-283 : y^2+xy=x^3+ax^2+b */ + CURVE_B_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000001", + "27b680ac8b8596da5a4af8a19a0303fca97fd7645309fa2a581485af6263e313b79a2f5", + "5f939258db7dd90e1934f8c70b0dfec2eed25b8557eac9c80e2e198f8cdbecd86b12053", + "3676854fe24141cb98fe6d4b20d02b4516ff702350eddb0826779c813f0df45be8112f4", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFEF90399660FC938A90165B042A7CEFADB307", /* "7770675568902916283677847627294075626569625924376904889109196526770044277787378692871" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve B-409 : y^2+xy=x^3+ax^2+b */ + CURVE_B_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "021a5c2c8ee9feb5c4b9a753b7b476b7fd6422ef1f3dd674761fa99d6ac27c8a9a197b272822f6cd57a55aa4f50ae317b13545f", + "15d4860d088ddb3496b0c6064756260441cde4af1771d4db01ffe5b34e59703dc255a868a1180515603aeab60794e54bb7996a7", + "061b1cfab6be5f32bbfa78324ed106a7636b9c5a7bd198d0158aa4f5488d08f38514f1fdf4b4f40d2181b3681c364ba0273c706", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "10000000000000000000000000000000000000000000000000001E2AAD6A612F33307BE5FA47C3C9E052F838164CD37D9A21173", /* "661055968790248598951915308032771039828404682964281219284648798304157774827374805208143723762179110965979867288366567526771" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve B-571 : y^2+xy=x^3+ax^2+b */ + CURVE_B_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "2f40e7e2221f295de297117b7f3d62f5c6a97ffcb8ceff1cd6ba8ce4a9a18ad84ffabbd8efa59332be7ad6756a66e294afd185a78ff12aa520e4de739baca0c7ffeff7f2955727a", + "303001d34b856296c16c0d40d3cd7750a93d1d2955fa80aa5f40fc8db7b2abdbde53950f4c0d293cdd711a35b67fb1499ae60038614f1394abfa3b4c850d927e1e7769c8eec2d19", + "37bf27342da639b6dccfffeb73d69d78c6c27a6009cbbca1980f8533921e8a684423e43bab08a576291af8f461bb2a8b3531d2f0485c19b16e2f1516e23dd3c1a4827af1b8ac15b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "3FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE661CE18FF55987308059B186823851EC7DD9CA1161DE93D5174D66E8382E9BB2FE84E47", /* "3864537523017258344695351890931987344298927329706434998657235251451519142289560424536143999389415773083133881121926944486246872462816813070234528288303332411393191105285703" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, + { + /* NIST: Curve K-163 : y^2+xy=x^3+ax^2+b */ + CURVE_K_163, + 41, /* Echar */ + "00000000000000000000000000000000000000001", + "00000000000000000000000000000000000000001", + "2fe13c0537bbc11acaa07d793de4e6d5e5c94eee8", + "289070fb05d38ff58321f2e800536d538ccdaa3d9", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 49, /* Eol */ + "4000000000000000000020108A2E0CC0D99F8A5EF", /* "5846006549323611672814741753598448348329118574063" */ + 163, /* key_len */ + 7, + 6, + 3, + CURVE_GF_2M + }, + { + /* NIST: Curve K-233 : y^2+xy=x^3+ax^2+b */ + CURVE_K_233, + 59, /* Echar 59 */ + "00000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000001", + "17232ba853a7e731af129f22ff4149563a419c26bf50a4c9d6eefad6126", + "1db537dece819b7f70f555a67c427a8cd9bf18aeb9b56e0c11056fae6a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 70, /* Eol */ + "8000000000000000000000000000069D5BB915BCD46EFB1AD5F173ABDF", /* "3450873173395281893717377931138512760570940988862252126328087024741343" */ + 233, /* key_len */ + 74, + 74, + 74, + CURVE_GF_2M + }, + { + /* NIST: Curve K-283 : y^2+xy=x^3+ax^2+b */ + CURVE_K_283, + 71, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000001", + "503213f78ca44883f1a3b8162f188e553cd265f23c1567a16876913b0c2ac2458492836", + "1ccda380f1c9e318d90f95d07e5426fe87e45c0e8184698e45962364e34116177dd2259", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 85, /* Eol */ + "1FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE9AE2ED07577265DFF7F94451E061E163C61", /* "3885337784451458141838923813647037813284811733793061324295874997529815829704422603873" */ + 283, /* key_len */ + 12, + 7, + 5, + CURVE_GF_2M + }, + { + /* NIST: Curve K-409 : y^2+xy=x^3+ax^2+b */ + CURVE_K_409, + 103, /* Echar */ + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "060f05f658f49c1ad3ab1890f7184210efd0987e307c84c27accfb8f9f67cc2c460189eb5aaaa62ee222eb1b35540cfe9023746", + "1e369050b7c4e42acba1dacbf04299c3460782f918ea427e6325165e9ea10e3da5f6c42e9c55215aa9ca27a5863ec48d8e0286b", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 123, /* Eol */ + "7FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFE5F83B2D4EA20400EC4557D5ED3E3E7CA5B4B5C83B8E01E5FCF", /* "330527984395124299475957654016385519914202341482140609642324395022880711289249191050673258457777458014096366590617731358671" */ + 409, /* key_len */ + 87, + 87, + 87, + CURVE_GF_2M + }, + { + /* NIST: Curve K-571 : y^2+xy=x^3+ax^2+b */ + CURVE_K_571, + 143, /* Echar */ + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000", + "00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001", + "26eb7a859923fbc82189631f8103fe4ac9ca2970012d5d46024804801841ca44370958493b205e647da304db4ceb08cbbd1ba39494776fb988b47174dca88c7e2945283a01c8972", + "349dc807f4fbf374f4aeade3bca95314dd58cec9f307a54ffc61efc006d8a2c9d4979c0ac44aea74fbebbb9f772aedcb620b01a7ba7af1b320430c8591984f601cd4c143ef1c7a3", + 68, /* Epl */ + "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF000000000000000000000001", /* "26959946667150639794667015087019630673557916260026308143510066298881" */ + 172, /* Eol */ + "20000000000000000000000000000000000000000000000000000000000000000000000131850E1F19A63E4B391A8DB917F4138B630D84BE5D639381E91DEB45CFE778F637C1001", /* "1932268761508629172347675945465993672149463664853217499328617625725759571144780212268133978522706711834706712800825351461273674974066617311929682421617092503555733685276673" */ + 571, /* key_len */ + 10, + 5, + 2, + CURVE_GF_2M + }, +}; +#endif + + +static ECC_CURVE *pCurve; +static ECC_CURVE Curve_Copy; + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve); +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve); +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode); + +static char temp_hex_str[160]; + +static volatile uint32_t g_ECC_done, g_ECCERR_done; + +void ECC_DriverISR(CRPT_T *crpt) +{ + if(crpt->INTSTS & CRPT_INTSTS_ECCIF_Msk) + { + g_ECC_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCIF_Msk; + /* printf("ECC done IRQ.\n"); */ + } + + if(crpt->INTSTS & CRPT_INTSTS_ECCEIF_Msk) + { + g_ECCERR_done = 1UL; + crpt->INTSTS = CRPT_INTSTS_ECCEIF_Msk; + /* printf("ECCERRIF is set!!\n"); */ + } +} + + +#if ENABLE_DEBUG +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) +{ + int32_t i; + + printf("%s => ", str); + for(i = 0; i < count; i++) + { + printf("0x%08x ", regs[i]); + } + printf("\n"); +} +#else +static void dump_ecc_reg(char *str, uint32_t volatile regs[], int32_t count) { (void)str; (void)regs; (void)count; } +#endif +static char ch2hex(char ch) +{ + if(ch <= '9') + { + return ch - '0'; + } + else if((ch <= 'z') && (ch >= 'a')) + { + return ch - 'a' + 10U; + } + else + { + return ch - 'A' + 10U; + } +} + +static void Hex2Reg(char input[], uint32_t volatile reg[]) +{ + char hex; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = ch2hex(input[si]); + val32 |= (uint32_t)hex << (i * 4UL); + si--; + } + reg[ri++] = val32; + } +} + +static void Hex2RegEx(char input[], uint32_t volatile reg[], int shift) +{ + uint32_t hex, carry; + int si, ri; + uint32_t i, val32; + + si = (int)strlen(input) - 1; + ri = 0; + carry = 0U; + while(si >= 0) + { + val32 = 0UL; + for(i = 0UL; (i < 8UL) && (si >= 0); i++) + { + hex = (uint32_t)ch2hex(input[si]); + hex <<= shift; + + val32 |= (uint32_t)((hex & 0xFU) | carry) << (i * 4UL); + carry = (hex >> 4) & 0xFU; + si--; + } + reg[ri++] = val32; + } + if(carry != 0U) + { + reg[ri] = carry; + } +} + +/** + * @brief Extract specified nibble from an unsigned word in character format. + * For example: + * Suppose val32 is 0x786543210, get_Nth_nibble_char(val32, 3) will return a '3'. + * @param[in] val32 The input unsigned word + * @param[in] idx The Nth nibble to be extracted. + * @return The nibble in character format. + */ +static char get_Nth_nibble_char(uint32_t val32, uint32_t idx) +{ + return hex_char_tbl[(val32 >> (idx * 4U)) & 0xfU ]; +} + + +static void Reg2Hex(int32_t count, uint32_t volatile reg[], char output[]) +{ + int32_t idx, ri; + uint32_t i; + + output[count] = 0U; + idx = count - 1; + + for(ri = 0; idx >= 0; ri++) + { + for(i = 0UL; (i < 8UL) && (idx >= 0); i++) + { + output[idx] = get_Nth_nibble_char(reg[ri], i); + idx--; + } + } +} + +static int32_t ecc_init_curve(CRPT_T *crpt, E_ECC_CURVE ecc_curve) +{ + int32_t i, ret = 0; + + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + CRPT_DBGMSG("Cannot find curve %d!!\n", ecc_curve); + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_A[i] = 0UL; + crpt->ECC_B[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + crpt->ECC_N[i] = 0UL; + } + + Hex2Reg(pCurve->Ea, crpt->ECC_A); + Hex2Reg(pCurve->Eb, crpt->ECC_B); + Hex2Reg(pCurve->Px, crpt->ECC_X1); + Hex2Reg(pCurve->Py, crpt->ECC_Y1); + + CRPT_DBGMSG("Key length = %d\n", pCurve->key_len); + dump_ecc_reg("CRPT_ECC_CURVE_A", crpt->ECC_A, 10); + dump_ecc_reg("CRPT_ECC_CURVE_B", crpt->ECC_B, 10); + dump_ecc_reg("CRPT_ECC_POINT_X1", crpt->ECC_X1, 10); + dump_ecc_reg("CRPT_ECC_POINT_Y1", crpt->ECC_Y1, 10); + + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_N[0] = 0x1UL; + crpt->ECC_N[(pCurve->key_len) / 32] |= (1UL << ((pCurve->key_len) % 32)); + crpt->ECC_N[(pCurve->irreducible_k1) / 32] |= (1UL << ((pCurve->irreducible_k1) % 32)); + crpt->ECC_N[(pCurve->irreducible_k2) / 32] |= (1UL << ((pCurve->irreducible_k2) % 32)); + crpt->ECC_N[(pCurve->irreducible_k3) / 32] |= (1UL << ((pCurve->irreducible_k3) % 32)); + } + else + { + Hex2Reg(pCurve->Pp, crpt->ECC_N); + } + } + dump_ecc_reg("CRPT_ECC_CURVE_N", crpt->ECC_N, 10); + return ret; +} + + +static int get_nibble_value(char c) +{ + char ch; + + if((c >= '0') && (c <= '9')) + { + ch = '0'; + return ((int)c - (int)ch); + } + + if((c >= 'a') && (c <= 'f')) + { + ch = 'a'; + return ((int)c - (int)ch + 10); + } + + if((c >= 'A') && (c <= 'F')) + { + ch = 'A'; + return ((int)c - (int)ch + 10); + } + return 0; +} + + +/** + * @brief Check if the private key is located in valid range of curve. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k The input private key. + * @return 1 Is valid. + * @return 0 Is not valid. + * @return -1 Invalid curve. + */ +int ECC_IsPrivateKeyValid(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char private_k[]) +{ + uint32_t i; + + (void)crpt; + pCurve = get_curve(ecc_curve); + if(pCurve == NULL) + { + return -1; + } + + if(strlen(private_k) < strlen(pCurve->Eorder)) + { + return 1; + } + + if(strlen(private_k) > strlen(pCurve->Eorder)) + { + return 0; + } + + for(i = 0U; i < strlen(private_k); i++) + { + if(get_nibble_value(private_k[i]) < get_nibble_value(pCurve->Eorder[i])) + { + return 1; + } + + if(get_nibble_value(private_k[i]) > get_nibble_value(pCurve->Eorder[i])) + { + return 0; + } + } + return 0; +} + + +/** + * @brief Given a private key and curve to generate the public key pair. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] private_k The input private key. + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[out] public_k1 The output publick key 1. + * @param[out] public_k2 The output publick key 2. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]) +{ + int32_t ret = 0, i; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + + Hex2Reg(private_k, crpt->ECC_K); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, public_k1); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, public_k2); + } + + return ret; +} + + +/** + * @brief Given a curve parameter, the other party's public key, and one's own private key to generate the secret Z. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] private_k One's own private key. + * @param[in] public_k1 The other party's publick key 1. + * @param[in] public_k2 The other party's publick key 2. + * @param[out] secret_z The ECC CDH secret Z. + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSecretZ(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[], char secret_z[]) +{ + int32_t i, ret = 0; + uint32_t u32Tmp; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + if((ecc_curve == CURVE_B_163) || (ecc_curve == CURVE_B_233) || (ecc_curve == CURVE_B_283) || + (ecc_curve == CURVE_B_409) || (ecc_curve == CURVE_B_571) || (ecc_curve == CURVE_K_163)) + { + Hex2RegEx(private_k, crpt->ECC_K, 1); + } + else if((ecc_curve == CURVE_K_233) || (ecc_curve == CURVE_K_283) || + (ecc_curve == CURVE_K_409) || (ecc_curve == CURVE_K_571)) + { + Hex2RegEx(private_k, crpt->ECC_K, 2); + } + else + { + Hex2Reg(private_k, crpt->ECC_K); + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* set FSEL (Field selection) */ + if(pCurve->GF == (int)CURVE_GF_2M) + { + crpt->ECC_CTL = 0UL; + } + else /* CURVE_GF_P */ + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | + ECCOP_POINT_MUL | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + Reg2Hex(pCurve->Echar, crpt->ECC_X1, secret_z); + } + + return ret; +} + +static void run_ecc_codec(CRPT_T *crpt, uint32_t mode) +{ + uint32_t u32Tmp; + + if((mode & CRPT_ECC_CTL_ECCOP_Msk) == ECCOP_MODULE) + { + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + else + { + if(pCurve->GF == (int)CURVE_GF_2M) + { + /* point */ + crpt->ECC_CTL = 0UL; + } + else + { + /* CURVE_GF_P */ + crpt->ECC_CTL = CRPT_ECC_CTL_FSEL_Msk; + } + } + + g_ECC_done = g_ECCERR_done = 0UL; + crpt->ECC_CTL |= ((uint32_t)pCurve->key_len << CRPT_ECC_CTL_CURVEM_Pos) | mode | CRPT_ECC_CTL_START_Msk; + + do + { + u32Tmp = g_ECC_done; + u32Tmp |= g_ECCERR_done; + } + while(u32Tmp == 0UL); + + while(crpt->ECC_STS & CRPT_ECC_STS_BUSY_Msk) { } +} + +/** + * @brief ECDSA digital signature generation. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] d The private key. + * @param[in] k The selected random integer. + * @param[out] R R of the (R,S) pair digital signature + * @param[out] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + */ +int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *d, char *k, char *R, char *S) +{ + uint32_t volatile temp_result1[18], temp_result2[18]; + int32_t i, ret = 0; + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + + /* + * 1. Calculate e = HASH(m), where HASH is a cryptographic hashing algorithm, (i.e. SHA-1) + * (1) Use SHA to calculate e + */ + + /* 2. Select a random integer k form [1, n-1] + * (1) Notice that n is order, not prime modulus or irreducible polynomial function + */ + + /* + * 3. Compute r = x1 (mod n), where (x1, y1) = k * G. If r = 0, go to step 2 + * (1) Write the curve parameter A, B, and curve length M to corresponding registers + * (2) Write the prime modulus or irreducible polynomial function to N registers according + * (3) Write the point G(x, y) to X1, Y1 registers + * (4) Write the random integer k to K register + * (5) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Write the curve order and curve length to N ,M registers according + * (10) Write 0x0 to Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 * + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Read X1 registers to get r + */ + + /* 3-(4) Write the random integer k to K register */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_K); + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* 3-(9) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(10) Write 0x0 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* 3-(15) Read X1 registers to get r */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result1, R); + + /* + * 4. Compute s = k ? 1 ¡Ñ (e + d ¡Ñ r)(mod n). If s = 0, go to step 2 + * (1) Write the curve order to N registers according + * (2) Write 0x1 to Y1 registers + * (3) Write the random integer k to X1 registers according + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set START(CRPT_ECC_CTL[0]) to 1 + * (7) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (8) Read X1 registers to get k^-1 + * (9) Write the curve order and curve length to N ,M registers + * (10) Write r, d to X1, Y1 registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (12) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (13) Set START(CRPT_ECC_CTL[0]) to 1 + * (14) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (15) Write the curve order to N registers + * (16) Write e to Y1 registers + * (17) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (18) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (19) Set START(CRPT_ECC_CTL[0]) to 1 + * (20) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (21) Write the curve order and curve length to N ,M registers + * (22) Write k^-1 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get s + */ + + /* S/W: GFp_add_mod_order(pCurve->key_len+2, 0, x1, a, R); */ + + /* 4-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 4-(3) Write the random integer k to X1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(k, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(7) output = %s\n", temp_hex_str); +#endif + + /* 4-(8) Read X1 registers to get k^-1 */ + + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("k^-1 = %s\n", temp_hex_str); +#endif + + /* 4-(9) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(10) Write r, d to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + } + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + Hex2Reg(d, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(14) output = %s\n", temp_hex_str); +#endif + + /* 4-(15) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(16) Write e to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(message, crpt->ECC_Y1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("(20) output = %s\n", temp_hex_str); +#endif + + /* 4-(21) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(22) Write k^-1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(27) Read X1 registers to get s */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + + Reg2Hex(pCurve->Echar, temp_result2, S); + + } /* ret == 0 */ + + return ret; +} + +/** + * @brief ECDSA dogotal signature verification. + * @param[in] crpt The pointer of CRYPTO module + * @param[in] ecc_curve The pre-defined ECC curve. + * @param[in] message The hash value of source context. + * @param[in] public_k1 The public key 1. + * @param[in] public_k2 The public key 2. + * @param[in] R R of the (R,S) pair digital signature + * @param[in] S S of the (R,S) pair digital signature + * @return 0 Success. + * @return -1 "ecc_curve" value is invalid. + * @return -2 Verification failed. + */ +int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, + char *public_k1, char *public_k2, char *R, char *S) +{ + uint32_t temp_result1[18], temp_result2[18]; + uint32_t temp_x[18], temp_y[18]; + int32_t i, ret = 0; + + /* + * 1. Verify that r and s are integers in the interval [1, n-1]. If not, the signature is invalid + * 2. Compute e = HASH (m), where HASH is the hashing algorithm in signature generation + * (1) Use SHA to calculate e + */ + + /* + * 3. Compute w = s^-1 (mod n) + * (1) Write the curve order to N registers + * (2) Write 0x1 to Y1 registers + * (3) Write s to X1 registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (5) Set MOPOP(CRPT_ECC_CTL[12:11]) to 00 + * (6) Set FSEL(CRPT_ECC_CTL[8]) according to used curve of prime field or binary field + * (7) Set START(CRPT_ECC_CTL[0]) to 1 + * (8) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (9) Read X1 registers to get w + */ + + if(ecc_init_curve(crpt, ecc_curve) != 0) + { + ret = -1; + } + + if(ret == 0) + { + + /* 3-(1) Write the curve order to N registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 3-(2) Write 0x1 to Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = 0UL; + } + crpt->ECC_Y1[0] = 0x1UL; + + /* 3-(3) Write s to X1 registers */ + for(i = 0; i < 18; i++) + { + CRPT->ECC_X1[i] = 0UL; + } + Hex2Reg(S, crpt->ECC_X1); + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_DIV); + + /* 3-(9) Read X1 registers to get w */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + CRPT_DBGMSG("e = %s\n", message); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("w = %s\n", temp_hex_str); + CRPT_DBGMSG("o = %s (order)\n", pCurve->Eorder); +#endif + + /* + * 4. Compute u1 = e ¡Ñ w (mod n) and u2 = r ¡Ñ w (mod n) + * (1) Write the curve order and curve length to N ,M registers + * (2) Write e, w to X1, Y1 registers + * (3) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (4) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1 registers to get u1 + * (8) Write the curve order and curve length to N ,M registers + * (9) Write r, w to X1, Y1 registers + * (10) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (11) Set MOPOP(CRPT_ECC_CTL[12:11]) to 01 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Read X1 registers to get u2 + */ + + /* 4-(1) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(2) Write e, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(message, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(7) Read X1 registers to get u1 */ + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("u1 = %s\n", temp_hex_str); +#endif + + /* 4-(8) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* 4-(9) Write r, w to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + } + Hex2Reg(R, crpt->ECC_X1); + + for(i = 0; i < 18; i++) + { + crpt->ECC_Y1[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_MUL); + + /* 4-(14) Read X1 registers to get u2 */ + for(i = 0; i < 18; i++) + { + temp_result2[i] = crpt->ECC_X1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("u2 = %s\n", temp_hex_str); +#endif + + /* + * 5. Compute X¡¦ (x1¡¦, y1¡¦) = u1 * G + u2 * Q + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + * (3) Write u1 to K registers + * (4) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (5) Set START(CRPT_ECC_CTL[0]) to 1 + * (6) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (7) Read X1, Y1 registers to get u1*G + * (8) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (9) Write the public key Q(x,y) to X1, Y1 registers + * (10) Write u2 to K registers + * (11) Set ECCOP(CRPT_ECC_CTL[10:9]) to 00 + * (12) Set START(CRPT_ECC_CTL[0]) to 1 + * (13) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (14) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (15) Write the result data u1*G to X2, Y2 registers + * (16) Set ECCOP(CRPT_ECC_CTL[10:9]) to 10 + * (17) Set START(CRPT_ECC_CTL[0]) to 1 + * (18) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) + * (20) Write the curve order and curve length to N ,M registers + * (21) Write x1¡¦ to X1 registers + * (22) Write 0x0 to Y1 registers + * (23) Set ECCOP(CRPT_ECC_CTL[10:9]) to 01 + * (24) Set MOPOP(CRPT_ECC_CTL[12:11]) to 10 + * (25) Set START(CRPT_ECC_CTL[0]) to 1 + * (26) Wait for BUSY(CRPT_ECC_STS[0]) be cleared + * (27) Read X1 registers to get x1¡¦ (mod n) + * + * 6. The signature is valid if x1¡¦ = r, otherwise it is invalid + */ + + /* + * (1) Write the curve parameter A, B, N, and curve length M to corresponding registers + * (2) Write the point G(x, y) to X1, Y1 registers + */ + ecc_init_curve(crpt, ecc_curve); + + /* (3) Write u1 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result1[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + /* (7) Read X1, Y1 registers to get u1*G */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(7) u1*G, y = %s\n", temp_hex_str); +#endif + + /* (8) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* (9) Write the public key Q(x,y) to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = 0UL; + crpt->ECC_Y1[i] = 0UL; + } + + Hex2Reg(public_k1, crpt->ECC_X1); + Hex2Reg(public_k2, crpt->ECC_Y1); + + /* (10) Write u2 to K registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_K[i] = temp_result2[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_MUL); + + for(i = 0; i < 18; i++) + { + temp_result1[i] = crpt->ECC_X1[i]; + temp_result2[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_result1, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, x = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_result2, temp_hex_str); + CRPT_DBGMSG("5-(13) u2*Q, y = %s\n", temp_hex_str); +#endif + + /* (14) Write the curve parameter A, B, N, and curve length M to corresponding registers */ + ecc_init_curve(crpt, ecc_curve); + + /* Write the result data u2*Q to X1, Y1 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_result1[i]; + crpt->ECC_Y1[i] = temp_result2[i]; + } + + /* (15) Write the result data u1*G to X2, Y2 registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X2[i] = temp_x[i]; + crpt->ECC_Y2[i] = temp_y[i]; + } + + run_ecc_codec(crpt, ECCOP_POINT_ADD); + + /* (19) Read X1, Y1 registers to get X¡¦(x1¡¦, y1¡¦) */ + for(i = 0; i < 18; i++) + { + temp_x[i] = crpt->ECC_X1[i]; + temp_y[i] = crpt->ECC_Y1[i]; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, temp_x, temp_hex_str); + CRPT_DBGMSG("5-(19) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, temp_y, temp_hex_str); + CRPT_DBGMSG("5-(19) y' = %s\n", temp_hex_str); +#endif + + /* (20) Write the curve order and curve length to N ,M registers */ + for(i = 0; i < 18; i++) + { + crpt->ECC_N[i] = 0UL; + } + Hex2Reg(pCurve->Eorder, crpt->ECC_N); + + /* + * (21) Write x1¡¦ to X1 registers + * (22) Write 0x0 to Y1 registers + */ + for(i = 0; i < 18; i++) + { + crpt->ECC_X1[i] = temp_x[i]; + crpt->ECC_Y1[i] = 0UL; + } + +#if ENABLE_DEBUG + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(21) x' = %s\n", temp_hex_str); + Reg2Hex(pCurve->Echar, crpt->ECC_Y1, temp_hex_str); + CRPT_DBGMSG("5-(22) y' = %s\n", temp_hex_str); +#endif + + run_ecc_codec(crpt, ECCOP_MODULE | MODOP_ADD); + + /* (27) Read X1 registers to get x1¡¦ (mod n) */ + Reg2Hex(pCurve->Echar, crpt->ECC_X1, temp_hex_str); + CRPT_DBGMSG("5-(27) x1' (mod n) = %s\n", temp_hex_str); + + /* 6. The signature is valid if x1¡¦ = r, otherwise it is invalid */ + + /* Compare with test pattern to check if r is correct or not */ + if(strcasecmp(temp_hex_str, R) != 0) + { + CRPT_DBGMSG("x1' (mod n) != R Test filed!!\n"); + CRPT_DBGMSG("Signature R [%s] is not matched with expected R [%s]!\n", temp_hex_str, R); + ret = -2; + } + } /* ret == 0 */ + + return ret; +} + +#if XOM_SUPPORT // To support XOM ready curve table + +static int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id) +{ + int32_t i; + + switch(id) + { + case CURVE_P_192: + p32[ 0] = 0x00000000; + p32[ 1] = 0x00000030; + for(i = 2; i <= 8; i++) + p32[i] = 0x46464646; + + p32[ 9] = 0x45464646; + p32[ 10] = 0x46464646; + p32[ 11] = 0x46464646; + p32[ 12] = 0x46464646; + p32[ 13] = 0x43464646; + for(i = 14; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x31323436; + p32[ 39] = 0x39313530; + p32[ 40] = 0x63393565; + p32[ 41] = 0x37653038; + p32[ 42] = 0x37616630; + p32[ 43] = 0x62613965; + p32[ 44] = 0x34323237; + p32[ 45] = 0x39343033; + p32[ 46] = 0x38626566; + p32[ 47] = 0x63656564; + p32[ 48] = 0x36343163; + p32[ 49] = 0x31623962; + for(i = 50; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x64383831; + p32[ 75] = 0x65303861; + p32[ 76] = 0x30333062; + p32[ 77] = 0x36663039; + p32[ 78] = 0x66626337; + p32[ 79] = 0x62653032; + p32[ 80] = 0x31613334; + p32[ 81] = 0x30303838; + p32[ 82] = 0x66663466; + p32[ 83] = 0x64666130; + p32[ 84] = 0x66663238; + p32[ 85] = 0x32313031; + for(i = 86; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x39313730; + p32[111] = 0x35396232; + p32[112] = 0x38636666; + p32[113] = 0x38376164; + p32[114] = 0x30313336; + p32[115] = 0x64653131; + p32[116] = 0x34326236; + p32[117] = 0x35646463; + p32[118] = 0x39663337; + p32[119] = 0x31613737; + p32[120] = 0x39376531; + p32[121] = 0x31313834; + for(i = 122; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x0000003a; + for(i = 147; i <= 153; i++) + p32[i] = 0x46464646; + + p32[154] = 0x45464646; + for(i = 155; i <= 158; i++) + p32[i] = 0x46464646; + + for(i = 159; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x0000003a; + for(i = 192; i <= 197; i++) + p32[i] = 0x46464646; + + p32[198] = 0x45443939; + p32[199] = 0x36333846; + p32[200] = 0x42363431; + p32[201] = 0x31423943; + p32[202] = 0x32443442; + p32[203] = 0x31333832; + for(i = 204; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000c0; + p32[237] = 0x00000007; + p32[238] = 0x00000002; + p32[239] = 0x00000001; + p32[240] = 0x00000000; + return 0; + case CURVE_P_224: + p32[ 0] = 0x00000001; + p32[ 1] = 0x00000038; + for(i = 2; i <= 8; i++) + p32[i] = 0x46464646; + + p32[ 9] = 0x45464646; + for(i = 10; i <= 14; i++) + p32[i] = 0x46464646; + + p32[ 15] = 0x45464646; + for(i = 16; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x35303462; + p32[ 39] = 0x35386130; + p32[ 40] = 0x34306330; + p32[ 41] = 0x62613362; + p32[ 42] = 0x31343566; + p32[ 43] = 0x36353233; + p32[ 44] = 0x34343035; + p32[ 45] = 0x37623062; + p32[ 46] = 0x66623764; + p32[ 47] = 0x61623864; + p32[ 48] = 0x62303732; + p32[ 49] = 0x33343933; + p32[ 50] = 0x35353332; + p32[ 51] = 0x34626666; + for(i = 52; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x65303762; + p32[ 75] = 0x64626330; + p32[ 76] = 0x34626236; + p32[ 77] = 0x66376662; + p32[ 78] = 0x33313233; + p32[ 79] = 0x39623039; + p32[ 80] = 0x33306134; + p32[ 81] = 0x33643163; + p32[ 82] = 0x32633635; + p32[ 83] = 0x32323131; + p32[ 84] = 0x32333433; + p32[ 85] = 0x36643038; + p32[ 86] = 0x63353131; + p32[ 87] = 0x31326431; + for(i = 88; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x37336462; + p32[111] = 0x38383336; + p32[112] = 0x37663562; + p32[113] = 0x62663332; + p32[114] = 0x32326334; + p32[115] = 0x36656664; + p32[116] = 0x33346463; + p32[117] = 0x30613537; + p32[118] = 0x37306135; + p32[119] = 0x34363734; + p32[120] = 0x35643434; + p32[121] = 0x39393138; + p32[122] = 0x30303538; + p32[123] = 0x34336537; + for(i = 124; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000046; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000046; + for(i = 192; i <= 198; i++) + p32[i] = 0x46464646; + + p32[199] = 0x32413631; + p32[200] = 0x38423045; + p32[201] = 0x45333046; + p32[202] = 0x44443331; + p32[203] = 0x35343932; + p32[204] = 0x43354335; + p32[205] = 0x44334132; + for(i = 206; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000e0; + p32[237] = 0x00000009; + p32[238] = 0x00000008; + p32[239] = 0x00000003; + p32[240] = 0x00000000; + return 0; + case CURVE_P_256: + p32[ 0] = 0x00000002; + p32[ 1] = 0x00000040; + p32[ 2] = 0x46464646; + p32[ 3] = 0x46464646; + p32[ 4] = 0x30303030; + p32[ 5] = 0x31303030; + for(i = 6; i <= 11; i++) + p32[i] = 0x30303030; + + for(i = 12; i <= 16; i++) + p32[i] = 0x46464646; + + p32[ 17] = 0x43464646; + for(i = 18; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x36636135; + p32[ 39] = 0x38643533; + p32[ 40] = 0x61336161; + p32[ 41] = 0x37653339; + p32[ 42] = 0x62653362; + p32[ 43] = 0x35356462; + p32[ 44] = 0x38393637; + p32[ 45] = 0x63623638; + p32[ 46] = 0x64313536; + p32[ 47] = 0x30623630; + p32[ 48] = 0x33356363; + p32[ 49] = 0x36663062; + p32[ 50] = 0x65636233; + p32[ 51] = 0x65336333; + p32[ 52] = 0x32643732; + p32[ 53] = 0x62343036; + for(i = 54; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x37316236; + p32[ 75] = 0x32663164; + p32[ 76] = 0x63323165; + p32[ 77] = 0x37343234; + p32[ 78] = 0x63623866; + p32[ 79] = 0x35653665; + p32[ 80] = 0x34613336; + p32[ 81] = 0x32663034; + p32[ 82] = 0x33303737; + p32[ 83] = 0x31386437; + p32[ 84] = 0x62656432; + p32[ 85] = 0x30613333; + p32[ 86] = 0x31613466; + p32[ 87] = 0x35343933; + p32[ 88] = 0x38393864; + p32[ 89] = 0x36393263; + for(i = 90; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x33656634; + p32[111] = 0x32653234; + p32[112] = 0x61316566; + p32[113] = 0x62396637; + p32[114] = 0x37656538; + p32[115] = 0x61346265; + p32[116] = 0x66306337; + p32[117] = 0x36316539; + p32[118] = 0x65636232; + p32[119] = 0x37353333; + p32[120] = 0x31336236; + p32[121] = 0x65636535; + p32[122] = 0x36626263; + p32[123] = 0x38363034; + p32[124] = 0x66623733; + p32[125] = 0x35663135; + for(i = 126; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x0000004e; + p32[147] = 0x46464646; + p32[148] = 0x46464646; + p32[149] = 0x30303030; + p32[150] = 0x31303030; + for(i = 151; i <= 156; i++) + p32[i] = 0x30303030; + + for(i = 157; i <= 162; i++) + p32[i] = 0x46464646; + + for(i = 163; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x0000004e; + p32[192] = 0x46464646; + p32[193] = 0x46464646; + p32[194] = 0x30303030; + p32[195] = 0x30303030; + for(i = 196; i <= 199; i++) + p32[i] = 0x46464646; + + p32[200] = 0x36454342; + p32[201] = 0x44414146; + p32[202] = 0x37313741; + p32[203] = 0x34384539; + p32[204] = 0x39423346; + p32[205] = 0x32434143; + p32[206] = 0x33364346; + p32[207] = 0x31353532; + for(i = 208; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x00000100; + p32[237] = 0x0000000a; + p32[238] = 0x00000005; + p32[239] = 0x00000002; + p32[240] = 0x00000000; + return 0; + case CURVE_P_384: + p32[ 0] = 0x00000003; + p32[ 1] = 0x00000060; + for(i = 2; i <= 16; i++) + p32[i] = 0x46464646; + + p32[ 17] = 0x45464646; + p32[ 18] = 0x46464646; + p32[ 19] = 0x46464646; + for(i = 20; i <= 23; i++) + p32[i] = 0x30303030; + + p32[ 24] = 0x46464646; + p32[ 25] = 0x43464646; + for(i = 26; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x31333362; + p32[ 39] = 0x37616632; + p32[ 40] = 0x65333265; + p32[ 41] = 0x34653765; + p32[ 42] = 0x65383839; + p32[ 43] = 0x62363530; + p32[ 44] = 0x38663365; + p32[ 45] = 0x39316432; + p32[ 46] = 0x64313831; + p32[ 47] = 0x65366339; + p32[ 48] = 0x31386566; + p32[ 49] = 0x32313134; + p32[ 50] = 0x34313330; + p32[ 51] = 0x66383830; + p32[ 52] = 0x33313035; + p32[ 53] = 0x61353738; + p32[ 54] = 0x36353663; + p32[ 55] = 0x64383933; + p32[ 56] = 0x65326138; + p32[ 57] = 0x64393164; + p32[ 58] = 0x35386132; + p32[ 59] = 0x64653863; + p32[ 60] = 0x63653364; + p32[ 61] = 0x66656132; + for(i = 62; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x37386161; + p32[ 75] = 0x32326163; + p32[ 76] = 0x62386562; + p32[ 77] = 0x37333530; + p32[ 78] = 0x31626538; + p32[ 79] = 0x65313763; + p32[ 80] = 0x30323366; + p32[ 81] = 0x34376461; + p32[ 82] = 0x64316536; + p32[ 83] = 0x32366233; + p32[ 84] = 0x37616238; + p32[ 85] = 0x38396239; + p32[ 86] = 0x37663935; + p32[ 87] = 0x30653134; + p32[ 88] = 0x34353238; + p32[ 89] = 0x38336132; + p32[ 90] = 0x32303535; + p32[ 91] = 0x64353266; + p32[ 92] = 0x35356662; + p32[ 93] = 0x63363932; + p32[ 94] = 0x34356133; + p32[ 95] = 0x38336535; + p32[ 96] = 0x36373237; + p32[ 97] = 0x37626130; + for(i = 98; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x37313633; + p32[111] = 0x61346564; + p32[112] = 0x36323639; + p32[113] = 0x66366332; + p32[114] = 0x65396435; + p32[115] = 0x66623839; + p32[116] = 0x32393239; + p32[117] = 0x39326364; + p32[118] = 0x34663866; + p32[119] = 0x64626431; + p32[120] = 0x61393832; + p32[121] = 0x63373431; + p32[122] = 0x61643965; + p32[123] = 0x33313133; + p32[124] = 0x30663562; + p32[125] = 0x30633862; + p32[126] = 0x30366130; + p32[127] = 0x65633162; + p32[128] = 0x65376431; + p32[129] = 0x64393138; + p32[130] = 0x33346137; + p32[131] = 0x63376431; + p32[132] = 0x61653039; + p32[133] = 0x66356530; + for(i = 134; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000074; + for(i = 147; i <= 161; i++) + p32[i] = 0x46464646; + + p32[162] = 0x45464646; + p32[163] = 0x46464646; + p32[164] = 0x46464646; + for(i = 165; i <= 168; i++) + p32[i] = 0x30303030; + + p32[169] = 0x46464646; + p32[170] = 0x46464646; + for(i = 171; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000074; + for(i = 192; i <= 203; i++) + p32[i] = 0x46464646; + + p32[204] = 0x33363743; + p32[205] = 0x31384434; + p32[206] = 0x37333446; + p32[207] = 0x46444432; + p32[208] = 0x41313835; + p32[209] = 0x32424430; + p32[210] = 0x30423834; + p32[211] = 0x41373741; + p32[212] = 0x43454345; + p32[213] = 0x41363931; + p32[214] = 0x35434343; + p32[215] = 0x33373932; + for(i = 216; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x00000180; + p32[237] = 0x0000000c; + p32[238] = 0x00000003; + p32[239] = 0x00000002; + p32[240] = 0x00000000; + return 0; + case CURVE_P_521: + p32[ 0] = 0x00000004; + p32[ 1] = 0x00000083; + p32[ 2] = 0x46464631; + for(i = 3; i <= 33; i++) + p32[i] = 0x46464646; + + p32[ 34] = 0x00434646; + p32[ 35] = 0x00000000; + p32[ 36] = 0x00000000; + p32[ 37] = 0x00000000; + p32[ 38] = 0x39313530; + p32[ 39] = 0x62653335; + p32[ 40] = 0x38313639; + p32[ 41] = 0x39633165; + p32[ 42] = 0x39663161; + p32[ 43] = 0x32613932; + p32[ 44] = 0x62306131; + p32[ 45] = 0x34353836; + p32[ 46] = 0x61656530; + p32[ 47] = 0x37616432; + p32[ 48] = 0x39623532; + p32[ 49] = 0x31336239; + p32[ 50] = 0x62336635; + p32[ 51] = 0x38346238; + p32[ 52] = 0x38313939; + p32[ 53] = 0x30316665; + p32[ 54] = 0x35316539; + p32[ 55] = 0x33393136; + p32[ 56] = 0x65313539; + p32[ 57] = 0x39653763; + p32[ 58] = 0x31623733; + p32[ 59] = 0x63323536; + p32[ 60] = 0x33646230; + p32[ 61] = 0x62316262; + p32[ 62] = 0x33373066; + p32[ 63] = 0x64333735; + p32[ 64] = 0x33383866; + p32[ 65] = 0x33633264; + p32[ 66] = 0x65316634; + p32[ 67] = 0x31353466; + p32[ 68] = 0x36346466; + p32[ 69] = 0x33303562; + p32[ 70] = 0x00303066; + p32[ 71] = 0x00000000; + p32[ 72] = 0x00000000; + p32[ 73] = 0x00000000; + p32[ 74] = 0x38366330; + p32[ 75] = 0x30653835; + p32[ 76] = 0x30376236; + p32[ 77] = 0x65343034; + p32[ 78] = 0x39646339; + p32[ 79] = 0x63653365; + p32[ 80] = 0x32363662; + p32[ 81] = 0x62353933; + p32[ 82] = 0x39323434; + p32[ 83] = 0x38343663; + p32[ 84] = 0x30393331; + p32[ 85] = 0x62663335; + p32[ 86] = 0x66313235; + p32[ 87] = 0x61383238; + p32[ 88] = 0x36303666; + p32[ 89] = 0x33643462; + p32[ 90] = 0x61616264; + p32[ 91] = 0x35623431; + p32[ 92] = 0x65373765; + p32[ 93] = 0x35376566; + p32[ 94] = 0x66383239; + p32[ 95] = 0x63643165; + p32[ 96] = 0x61373231; + p32[ 97] = 0x61666632; + p32[ 98] = 0x33656438; + p32[ 99] = 0x62383433; + p32[100] = 0x38316333; + p32[101] = 0x34613635; + p32[102] = 0x66623932; + p32[103] = 0x37653739; + p32[104] = 0x63313365; + p32[105] = 0x62356532; + p32[106] = 0x00363664; + p32[107] = 0x00000000; + p32[108] = 0x00000000; + p32[109] = 0x00000000; + p32[110] = 0x33383131; + p32[111] = 0x36393239; + p32[112] = 0x39383761; + p32[113] = 0x63623361; + p32[114] = 0x35343030; + p32[115] = 0x35613863; + p32[116] = 0x32346266; + p32[117] = 0x31643763; + p32[118] = 0x39396462; + p32[119] = 0x34356638; + p32[120] = 0x35393434; + p32[121] = 0x34623937; + p32[122] = 0x31383634; + p32[123] = 0x62666137; + p32[124] = 0x32373164; + p32[125] = 0x36653337; + p32[126] = 0x39633236; + p32[127] = 0x37656537; + p32[128] = 0x35393932; + p32[129] = 0x32346665; + p32[130] = 0x63303436; + p32[131] = 0x62303535; + p32[132] = 0x33313039; + p32[133] = 0x30646166; + p32[134] = 0x33313637; + p32[135] = 0x37633335; + p32[136] = 0x61363830; + p32[137] = 0x63323732; + p32[138] = 0x38303432; + p32[139] = 0x39656238; + p32[140] = 0x39363734; + p32[141] = 0x36316466; + p32[142] = 0x00303536; + p32[143] = 0x00000000; + p32[144] = 0x00000000; + p32[145] = 0x00000000; + p32[146] = 0x0000009d; + p32[147] = 0x46464631; + for(i = 148; i <= 178; i++) + p32[i] = 0x46464646; + + p32[179] = 0x00464646; + for(i = 180; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x0000009d; + p32[192] = 0x46464631; + for(i = 193; i <= 207; i++) + p32[i] = 0x46464646; + + p32[208] = 0x35414646; + p32[209] = 0x38363831; + p32[210] = 0x42333837; + p32[211] = 0x39463246; + p32[212] = 0x37423636; + p32[213] = 0x30434346; + p32[214] = 0x46383431; + p32[215] = 0x41393037; + p32[216] = 0x33304435; + p32[217] = 0x43354242; + p32[218] = 0x38384239; + p32[219] = 0x34433939; + p32[220] = 0x42454137; + p32[221] = 0x42463642; + p32[222] = 0x39453137; + p32[223] = 0x36383331; + p32[224] = 0x00393034; + for(i = 225; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x00000209; + p32[237] = 0x00000020; + p32[238] = 0x00000020; + p32[239] = 0x00000020; + p32[240] = 0x00000000; + return 0; + case CURVE_B_163: + p32[ 0] = 0x0000000a; + p32[ 1] = 0x00000029; + for(i = 2; i <= 11; i++) + p32[i] = 0x30303030; + + p32[ 12] = 0x00000031; + for(i = 13; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x36613032; + p32[ 39] = 0x30393130; + p32[ 40] = 0x63386237; + p32[ 41] = 0x63333539; + p32[ 42] = 0x38343161; + p32[ 43] = 0x31626531; + p32[ 44] = 0x32313530; + p32[ 45] = 0x37383766; + p32[ 46] = 0x33613434; + p32[ 47] = 0x66353032; + p32[ 48] = 0x00000064; + for(i = 49; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x65306633; + p32[ 75] = 0x36316162; + p32[ 76] = 0x61363832; + p32[ 77] = 0x37356432; + p32[ 78] = 0x39306165; + p32[ 79] = 0x36313139; + p32[ 80] = 0x39346438; + p32[ 81] = 0x33363439; + p32[ 82] = 0x33386537; + p32[ 83] = 0x33653334; + p32[ 84] = 0x00000036; + for(i = 85; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x31356430; + p32[111] = 0x36636266; + p32[112] = 0x61313763; + p32[113] = 0x34393030; + p32[114] = 0x63326166; + p32[115] = 0x34356464; + p32[116] = 0x31316235; + p32[117] = 0x30633563; + p32[118] = 0x37393763; + p32[119] = 0x66343233; + p32[120] = 0x00000031; + for(i = 121; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000031; + p32[192] = 0x30303034; + for(i = 193; i <= 196; i++) + p32[i] = 0x30303030; + + p32[197] = 0x46323932; + p32[198] = 0x45373745; + p32[199] = 0x31433037; + p32[200] = 0x32344132; + p32[201] = 0x33433433; + p32[202] = 0x00000033; + for(i = 203; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000a3; + p32[237] = 0x00000007; + p32[238] = 0x00000006; + p32[239] = 0x00000003; + p32[240] = 0x00000001; + return 0; + case CURVE_B_233: + p32[ 0] = 0x0000000b; + p32[ 1] = 0x0000003b; + for(i = 2; i <= 15; i++) + p32[i] = 0x30303030; + + p32[ 16] = 0x00313030; + for(i = 17; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x36363630; + p32[ 39] = 0x64653734; + p32[ 40] = 0x33633665; + p32[ 41] = 0x37633233; + p32[ 42] = 0x30633866; + p32[ 43] = 0x62333239; + p32[ 44] = 0x32383562; + p32[ 45] = 0x33623331; + p32[ 46] = 0x32623333; + p32[ 47] = 0x63396530; + p32[ 48] = 0x38323465; + p32[ 49] = 0x31656631; + p32[ 50] = 0x37663531; + p32[ 51] = 0x39663864; + p32[ 52] = 0x00646130; + for(i = 53; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x63616630; + p32[ 75] = 0x63666439; + p32[ 76] = 0x38636162; + p32[ 77] = 0x62333133; + p32[ 78] = 0x33313262; + p32[ 79] = 0x62316639; + p32[ 80] = 0x35353762; + p32[ 81] = 0x36666566; + p32[ 82] = 0x33636235; + p32[ 83] = 0x38663139; + p32[ 84] = 0x66363362; + p32[ 85] = 0x65386638; + p32[ 86] = 0x37333762; + p32[ 87] = 0x35646631; + p32[ 88] = 0x00623835; + for(i = 89; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x36303031; + p32[111] = 0x61383061; + p32[112] = 0x30393134; + p32[113] = 0x30353333; + p32[114] = 0x65383736; + p32[115] = 0x32353835; + p32[116] = 0x62656238; + p32[117] = 0x30613866; + p32[118] = 0x66666562; + p32[119] = 0x61373638; + p32[120] = 0x33616337; + p32[121] = 0x36313736; + p32[122] = 0x30653766; + p32[123] = 0x31386631; + p32[124] = 0x00323530; + for(i = 125; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000046; + p32[192] = 0x30303031; + for(i = 193; i <= 198; i++) + p32[i] = 0x30303030; + + p32[199] = 0x45333130; + p32[200] = 0x45343739; + p32[201] = 0x38463237; + p32[202] = 0x32393641; + p32[203] = 0x31333032; + p32[204] = 0x30363244; + p32[205] = 0x45464333; + p32[206] = 0x00374430; + for(i = 207; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000e9; + p32[237] = 0x0000004a; + p32[238] = 0x0000004a; + p32[239] = 0x0000004a; + p32[240] = 0x00000001; + return 0; + case CURVE_B_283: + p32[ 0] = 0x0000000c; + p32[ 1] = 0x00000047; + for(i = 2; i <= 18; i++) + p32[i] = 0x30303030; + + p32[ 19] = 0x00313030; + for(i = 20; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x36623732; + p32[ 39] = 0x63613038; + p32[ 40] = 0x35386238; + p32[ 41] = 0x61643639; + p32[ 42] = 0x61346135; + p32[ 43] = 0x31613866; + p32[ 44] = 0x33306139; + p32[ 45] = 0x63663330; + p32[ 46] = 0x66373961; + p32[ 47] = 0x34363764; + p32[ 48] = 0x39303335; + p32[ 49] = 0x61326166; + p32[ 50] = 0x34313835; + p32[ 51] = 0x66613538; + p32[ 52] = 0x33363236; + p32[ 53] = 0x33313365; + p32[ 54] = 0x61393762; + p32[ 55] = 0x00356632; + for(i = 56; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x33396635; + p32[ 75] = 0x38353239; + p32[ 76] = 0x64376264; + p32[ 77] = 0x65303964; + p32[ 78] = 0x34333931; + p32[ 79] = 0x37633866; + p32[ 80] = 0x64306230; + p32[ 81] = 0x32636566; + p32[ 82] = 0x32646565; + p32[ 83] = 0x35386235; + p32[ 84] = 0x61653735; + p32[ 85] = 0x38633963; + p32[ 86] = 0x65326530; + p32[ 87] = 0x66383931; + p32[ 88] = 0x62646338; + p32[ 89] = 0x38646365; + p32[ 90] = 0x32316236; + p32[ 91] = 0x00333530; + for(i = 92; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x36373633; + p32[111] = 0x66343538; + p32[112] = 0x31343265; + p32[113] = 0x62633134; + p32[114] = 0x65663839; + p32[115] = 0x62346436; + p32[116] = 0x30643032; + p32[117] = 0x35346232; + p32[118] = 0x66663631; + p32[119] = 0x33323037; + p32[120] = 0x64653035; + p32[121] = 0x38306264; + p32[122] = 0x37373632; + p32[123] = 0x31386339; + p32[124] = 0x64306633; + p32[125] = 0x62353466; + p32[126] = 0x31313865; + p32[127] = 0x00346632; + for(i = 128; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000055; + p32[192] = 0x46464633; + for(i = 193; i <= 199; i++) + p32[i] = 0x46464646; + + p32[200] = 0x45464646; + p32[201] = 0x33303946; + p32[202] = 0x36363939; + p32[203] = 0x39434630; + p32[204] = 0x39413833; + p32[205] = 0x35363130; + p32[206] = 0x32343042; + p32[207] = 0x45433741; + p32[208] = 0x42444146; + p32[209] = 0x00373033; + for(i = 210; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x0000011b; + p32[237] = 0x0000000c; + p32[238] = 0x00000007; + p32[239] = 0x00000005; + p32[240] = 0x00000001; + return 0; + case CURVE_B_409: + p32[ 0] = 0x0000000d; + p32[ 1] = 0x00000067; + for(i = 2; i <= 26; i++) + p32[i] = 0x30303030; + + p32[ 27] = 0x00313030; + for(i = 28; i <= 37; i++) + p32[i] = 0x00000000; + + p32[ 38] = 0x61313230; + p32[ 39] = 0x63326335; + p32[ 40] = 0x39656538; + p32[ 41] = 0x35626566; + p32[ 42] = 0x39623463; + p32[ 43] = 0x33353761; + p32[ 44] = 0x34623762; + p32[ 45] = 0x37623637; + p32[ 46] = 0x34366466; + p32[ 47] = 0x66653232; + p32[ 48] = 0x64336631; + p32[ 49] = 0x34373664; + p32[ 50] = 0x66313637; + p32[ 51] = 0x64393961; + p32[ 52] = 0x32636136; + p32[ 53] = 0x61386337; + p32[ 54] = 0x39316139; + p32[ 55] = 0x37326237; + p32[ 56] = 0x32323832; + p32[ 57] = 0x64633666; + p32[ 58] = 0x35613735; + p32[ 59] = 0x34616135; + p32[ 60] = 0x61303566; + p32[ 61] = 0x37313365; + p32[ 62] = 0x35333162; + p32[ 63] = 0x00663534; + for(i = 64; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x34643531; + p32[ 75] = 0x64303638; + p32[ 76] = 0x64383830; + p32[ 77] = 0x34336264; + p32[ 78] = 0x30623639; + p32[ 79] = 0x36303663; + p32[ 80] = 0x36353734; + p32[ 81] = 0x34303632; + p32[ 82] = 0x64633134; + p32[ 83] = 0x66613465; + p32[ 84] = 0x31373731; + p32[ 85] = 0x62643464; + p32[ 86] = 0x66663130; + p32[ 87] = 0x33623565; + p32[ 88] = 0x39356534; + p32[ 89] = 0x64333037; + p32[ 90] = 0x35353263; + p32[ 91] = 0x38363861; + p32[ 92] = 0x38313161; + p32[ 93] = 0x35313530; + p32[ 94] = 0x61333036; + p32[ 95] = 0x36626165; + p32[ 96] = 0x34393730; + p32[ 97] = 0x62343565; + p32[ 98] = 0x39393762; + p32[ 99] = 0x00376136; + for(i = 100; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x62313630; + p32[111] = 0x61666331; + p32[112] = 0x65623662; + p32[113] = 0x32336635; + p32[114] = 0x61666262; + p32[115] = 0x32333837; + p32[116] = 0x31646534; + p32[117] = 0x37613630; + p32[118] = 0x62363336; + p32[119] = 0x61356339; + p32[120] = 0x31646237; + p32[121] = 0x30643839; + p32[122] = 0x61383531; + p32[123] = 0x35663461; + p32[124] = 0x64383834; + p32[125] = 0x33663830; + p32[126] = 0x34313538; + p32[127] = 0x64663166; + p32[128] = 0x34623466; + p32[129] = 0x64303466; + p32[130] = 0x31383132; + p32[131] = 0x38363362; + p32[132] = 0x36336331; + p32[133] = 0x30616234; + p32[134] = 0x63333732; + p32[135] = 0x00363037; + for(i = 136; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x0000007b; + p32[192] = 0x30303031; + for(i = 193; i <= 204; i++) + p32[i] = 0x30303030; + + p32[205] = 0x41324531; + p32[206] = 0x41364441; + p32[207] = 0x46323136; + p32[208] = 0x30333333; + p32[209] = 0x35454237; + p32[210] = 0x37344146; + p32[211] = 0x39433343; + p32[212] = 0x32353045; + p32[213] = 0x38333846; + p32[214] = 0x43343631; + p32[215] = 0x44373344; + p32[216] = 0x31324139; + p32[217] = 0x00333731; + for(i = 218; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x00000199; + p32[237] = 0x00000057; + p32[238] = 0x00000057; + p32[239] = 0x00000057; + p32[240] = 0x00000001; + return 0; + case CURVE_B_571: + p32[ 0] = 0x0000000e; + p32[ 1] = 0x0000008f; + for(i = 2; i <= 36; i++) + p32[i] = 0x30303030; + + p32[ 37] = 0x00313030; + p32[ 38] = 0x30346632; + p32[ 39] = 0x32653765; + p32[ 40] = 0x66313232; + p32[ 41] = 0x64353932; + p32[ 42] = 0x37393265; + p32[ 43] = 0x62373131; + p32[ 44] = 0x64336637; + p32[ 45] = 0x35663236; + p32[ 46] = 0x39613663; + p32[ 47] = 0x63666637; + p32[ 48] = 0x65633862; + p32[ 49] = 0x63316666; + p32[ 50] = 0x61623664; + p32[ 51] = 0x34656338; + p32[ 52] = 0x31613961; + p32[ 53] = 0x38646138; + p32[ 54] = 0x61666634; + p32[ 55] = 0x38646262; + p32[ 56] = 0x35616665; + p32[ 57] = 0x32333339; + p32[ 58] = 0x61376562; + p32[ 59] = 0x35373664; + p32[ 60] = 0x36366136; + p32[ 61] = 0x34393265; + p32[ 62] = 0x31646661; + p32[ 63] = 0x37613538; + p32[ 64] = 0x31666638; + p32[ 65] = 0x35616132; + p32[ 66] = 0x34653032; + p32[ 67] = 0x33376564; + p32[ 68] = 0x63616239; + p32[ 69] = 0x37633061; + p32[ 70] = 0x66656666; + p32[ 71] = 0x32663766; + p32[ 72] = 0x37353539; + p32[ 73] = 0x00613732; + p32[ 74] = 0x30333033; + p32[ 75] = 0x33643130; + p32[ 76] = 0x35386234; + p32[ 77] = 0x36393236; + p32[ 78] = 0x63363163; + p32[ 79] = 0x30346430; + p32[ 80] = 0x64633364; + p32[ 81] = 0x30353737; + p32[ 82] = 0x64333961; + p32[ 83] = 0x39326431; + p32[ 84] = 0x61663535; + p32[ 85] = 0x61613038; + p32[ 86] = 0x30346635; + p32[ 87] = 0x64386366; + p32[ 88] = 0x32623762; + p32[ 89] = 0x62646261; + p32[ 90] = 0x33356564; + p32[ 91] = 0x66303539; + p32[ 92] = 0x64306334; + p32[ 93] = 0x63333932; + p32[ 94] = 0x31376464; + p32[ 95] = 0x35336131; + p32[ 96] = 0x66373662; + p32[ 97] = 0x39343162; + p32[ 98] = 0x36656139; + p32[ 99] = 0x38333030; + p32[100] = 0x66343136; + p32[101] = 0x34393331; + p32[102] = 0x61666261; + p32[103] = 0x63346233; + p32[104] = 0x64303538; + p32[105] = 0x65373239; + p32[106] = 0x37376531; + p32[107] = 0x38633936; + p32[108] = 0x32636565; + p32[109] = 0x00393164; + p32[110] = 0x66623733; + p32[111] = 0x34333732; + p32[112] = 0x36616432; + p32[113] = 0x36623933; + p32[114] = 0x66636364; + p32[115] = 0x62656666; + p32[116] = 0x36643337; + p32[117] = 0x38376439; + p32[118] = 0x32633663; + p32[119] = 0x30366137; + p32[120] = 0x62633930; + p32[121] = 0x31616362; + p32[122] = 0x66303839; + p32[123] = 0x33333538; + p32[124] = 0x65313239; + p32[125] = 0x38366138; + p32[126] = 0x33323434; + p32[127] = 0x62333465; + p32[128] = 0x38306261; + p32[129] = 0x36373561; + p32[130] = 0x61313932; + p32[131] = 0x34663866; + p32[132] = 0x62623136; + p32[133] = 0x62386132; + p32[134] = 0x31333533; + p32[135] = 0x30663264; + p32[136] = 0x63353834; + p32[137] = 0x31623931; + p32[138] = 0x66326536; + p32[139] = 0x36313531; + p32[140] = 0x64333265; + p32[141] = 0x31633364; + p32[142] = 0x32383461; + p32[143] = 0x31666137; + p32[144] = 0x63613862; + p32[145] = 0x00623531; + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x000000ac; + p32[192] = 0x46464633; + for(i = 193; i <= 208; i++) + p32[i] = 0x46464646; + + p32[209] = 0x45464646; + p32[210] = 0x43313636; + p32[211] = 0x46383145; + p32[212] = 0x39353546; + p32[213] = 0x30333738; + p32[214] = 0x39353038; + p32[215] = 0x36383142; + p32[216] = 0x38333238; + p32[217] = 0x43453135; + p32[218] = 0x39444437; + p32[219] = 0x31314143; + p32[220] = 0x45443136; + p32[221] = 0x35443339; + p32[222] = 0x44343731; + p32[223] = 0x38453636; + p32[224] = 0x45323833; + p32[225] = 0x32424239; + p32[226] = 0x34384546; + p32[227] = 0x00373445; + for(i = 228; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x0000023b; + p32[237] = 0x0000000a; + p32[238] = 0x00000005; + p32[239] = 0x00000002; + p32[240] = 0x00000001; + return 0; + case CURVE_K_163: + p32[ 0] = 0x00000005; + p32[ 1] = 0x00000029; + for(i = 2; i <= 11; i++) + p32[i] = 0x30303030; + + p32[ 12] = 0x00000031; + for(i = 13; i <= 37; i++) + p32[i] = 0x00000000; + + for(i = 38; i <= 47; i++) + p32[i] = 0x30303030; + + p32[ 48] = 0x00000031; + for(i = 49; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x31656632; + p32[ 75] = 0x35306333; + p32[ 76] = 0x62623733; + p32[ 77] = 0x61313163; + p32[ 78] = 0x30616163; + p32[ 79] = 0x39376437; + p32[ 80] = 0x34656433; + p32[ 81] = 0x35643665; + p32[ 82] = 0x39633565; + p32[ 83] = 0x65656534; + p32[ 84] = 0x00000038; + for(i = 85; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x30393832; + p32[111] = 0x62663037; + p32[112] = 0x33643530; + p32[113] = 0x35666638; + p32[114] = 0x31323338; + p32[115] = 0x38653266; + p32[116] = 0x33353030; + p32[117] = 0x33356436; + p32[118] = 0x64636338; + p32[119] = 0x64336161; + p32[120] = 0x00000039; + for(i = 121; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000031; + p32[192] = 0x30303034; + for(i = 193; i <= 196; i++) + p32[i] = 0x30303030; + + p32[197] = 0x30313032; + p32[198] = 0x45324138; + p32[199] = 0x30434330; + p32[200] = 0x46393944; + p32[201] = 0x45354138; + p32[202] = 0x00000046; + for(i = 203; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000a3; + p32[237] = 0x00000007; + p32[238] = 0x00000006; + p32[239] = 0x00000003; + p32[240] = 0x00000001; + return 0; + case CURVE_K_233: + p32[ 0] = 0x00000006; + p32[ 1] = 0x0000003b; + for(i = 2; i <= 15; i++) + p32[i] = 0x30303030; + + p32[ 16] = 0x00303030; + for(i = 17; i <= 37; i++) + p32[i] = 0x00000000; + + for(i = 38; i <= 51; i++) + p32[i] = 0x30303030; + + p32[ 52] = 0x00313030; + for(i = 53; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x33323731; + p32[ 75] = 0x38616232; + p32[ 76] = 0x37613335; + p32[ 77] = 0x31333765; + p32[ 78] = 0x32316661; + p32[ 79] = 0x32326639; + p32[ 80] = 0x31346666; + p32[ 81] = 0x36353934; + p32[ 82] = 0x31346133; + p32[ 83] = 0x36326339; + p32[ 84] = 0x30356662; + p32[ 85] = 0x39633461; + p32[ 86] = 0x65653664; + p32[ 87] = 0x36646166; + p32[ 88] = 0x00363231; + for(i = 89; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x35626431; + p32[111] = 0x65643733; + p32[112] = 0x31386563; + p32[113] = 0x66376239; + p32[114] = 0x35663037; + p32[115] = 0x36613535; + p32[116] = 0x32346337; + p32[117] = 0x63386137; + p32[118] = 0x66623964; + p32[119] = 0x65613831; + p32[120] = 0x35623962; + p32[121] = 0x63306536; + p32[122] = 0x35303131; + p32[123] = 0x65616636; + p32[124] = 0x00336136; + for(i = 125; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000046; + p32[192] = 0x30303038; + for(i = 193; i <= 198; i++) + p32[i] = 0x30303030; + + p32[199] = 0x44393630; + p32[200] = 0x39424235; + p32[201] = 0x43423531; + p32[202] = 0x45363444; + p32[203] = 0x41314246; + p32[204] = 0x31463544; + p32[205] = 0x42413337; + p32[206] = 0x00004644; + for(i = 207; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x000000e9; + p32[237] = 0x0000004a; + p32[238] = 0x0000004a; + p32[239] = 0x0000004a; + p32[240] = 0x00000001; + return 0; + case CURVE_K_283: + p32[ 0] = 0x00000007; + p32[ 1] = 0x00000047; + for(i = 2; i <= 18; i++) + p32[i] = 0x30303030; + + p32[ 19] = 0x00303030; + for(i = 20; i <= 37; i++) + p32[i] = 0x00000000; + + for(i = 38; i <= 54; i++) + p32[i] = 0x30303030; + + p32[ 55] = 0x00313030; + for(i = 56; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x32333035; + p32[ 75] = 0x37663331; + p32[ 76] = 0x34616338; + p32[ 77] = 0x33383834; + p32[ 78] = 0x33613166; + p32[ 79] = 0x36313862; + p32[ 80] = 0x38316632; + p32[ 81] = 0x35356538; + p32[ 82] = 0x32646333; + p32[ 83] = 0x32663536; + p32[ 84] = 0x35316333; + p32[ 85] = 0x31613736; + p32[ 86] = 0x36373836; + p32[ 87] = 0x62333139; + p32[ 88] = 0x61326330; + p32[ 89] = 0x35343263; + p32[ 90] = 0x32393438; + p32[ 91] = 0x00363338; + for(i = 92; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x64636331; + p32[111] = 0x30383361; + p32[112] = 0x39633166; + p32[113] = 0x38313365; + p32[114] = 0x66303964; + p32[115] = 0x30643539; + p32[116] = 0x34356537; + p32[117] = 0x65663632; + p32[118] = 0x34653738; + p32[119] = 0x65306335; + p32[120] = 0x34383138; + p32[121] = 0x65383936; + p32[122] = 0x36393534; + p32[123] = 0x34363332; + p32[124] = 0x31343365; + p32[125] = 0x37313631; + p32[126] = 0x32646437; + p32[127] = 0x00393532; + for(i = 128; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x00000055; + p32[192] = 0x46464631; + for(i = 193; i <= 199; i++) + p32[i] = 0x46464646; + + p32[200] = 0x45464646; + p32[201] = 0x32454139; + p32[202] = 0x37304445; + p32[203] = 0x32373735; + p32[204] = 0x46443536; + p32[205] = 0x39463746; + p32[206] = 0x31353434; + p32[207] = 0x31363045; + p32[208] = 0x33363145; + p32[209] = 0x00313643; + for(i = 210; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x0000011b; + p32[237] = 0x0000000c; + p32[238] = 0x00000007; + p32[239] = 0x00000005; + p32[240] = 0x00000001; + return 0; + case CURVE_K_409: + p32[ 0] = 0x00000008; + p32[ 1] = 0x00000067; + for(i = 2; i <= 26; i++) + p32[i] = 0x30303030; + + p32[ 27] = 0x00303030; + for(i = 28; i <= 37; i++) + p32[i] = 0x00000000; + + for(i = 38; i <= 62; i++) + p32[i] = 0x30303030; + + p32[ 63] = 0x00313030; + for(i = 64; i <= 73; i++) + p32[i] = 0x00000000; + + p32[ 74] = 0x66303630; + p32[ 75] = 0x36663530; + p32[ 76] = 0x34663835; + p32[ 77] = 0x61316339; + p32[ 78] = 0x62613364; + p32[ 79] = 0x30393831; + p32[ 80] = 0x38313766; + p32[ 81] = 0x30313234; + p32[ 82] = 0x30646665; + p32[ 83] = 0x65373839; + p32[ 84] = 0x63373033; + p32[ 85] = 0x32633438; + p32[ 86] = 0x63636137; + p32[ 87] = 0x66386266; + p32[ 88] = 0x37366639; + p32[ 89] = 0x63326363; + p32[ 90] = 0x31303634; + p32[ 91] = 0x62653938; + p32[ 92] = 0x61616135; + p32[ 93] = 0x65323661; + p32[ 94] = 0x32323265; + p32[ 95] = 0x62316265; + p32[ 96] = 0x34353533; + p32[ 97] = 0x65666330; + p32[ 98] = 0x33323039; + p32[ 99] = 0x00363437; + for(i = 100; i <= 109; i++) + p32[i] = 0x00000000; + + p32[110] = 0x36336531; + p32[111] = 0x30353039; + p32[112] = 0x34633762; + p32[113] = 0x61323465; + p32[114] = 0x31616263; + p32[115] = 0x62636164; + p32[116] = 0x32343066; + p32[117] = 0x33633939; + p32[118] = 0x37303634; + p32[119] = 0x39663238; + p32[120] = 0x61653831; + p32[121] = 0x65373234; + p32[122] = 0x35323336; + p32[123] = 0x65353631; + p32[124] = 0x31616539; + p32[125] = 0x64336530; + p32[126] = 0x36663561; + p32[127] = 0x65323463; + p32[128] = 0x35356339; + p32[129] = 0x61353132; + p32[130] = 0x61633961; + p32[131] = 0x35613732; + p32[132] = 0x65333638; + p32[133] = 0x64383463; + p32[134] = 0x32306538; + p32[135] = 0x00623638; + for(i = 136; i <= 145; i++) + p32[i] = 0x00000000; + + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x0000007b; + p32[192] = 0x46464637; + for(i = 193; i <= 203; i++) + p32[i] = 0x46464646; + + p32[204] = 0x45464646; + p32[205] = 0x33384635; + p32[206] = 0x34443242; + p32[207] = 0x30324145; + p32[208] = 0x45303034; + p32[209] = 0x35353443; + p32[210] = 0x45354437; + p32[211] = 0x33453344; + p32[212] = 0x41433745; + p32[213] = 0x42344235; + p32[214] = 0x33384335; + p32[215] = 0x30453842; + p32[216] = 0x46354531; + p32[217] = 0x00004643; + for(i = 218; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x00000199; + p32[237] = 0x00000057; + p32[238] = 0x00000057; + p32[239] = 0x00000057; + p32[240] = 0x00000001; + return 0; + case CURVE_K_571: + p32[ 0] = 0x00000009; + p32[ 1] = 0x0000008f; + for(i = 2; i <= 36; i++) + p32[i] = 0x30303030; + + p32[ 37] = 0x00303030; + for(i = 38; i <= 72; i++) + p32[i] = 0x30303030; + + p32[ 73] = 0x00313030; + p32[ 74] = 0x62653632; + p32[ 75] = 0x35386137; + p32[ 76] = 0x33323939; + p32[ 77] = 0x38636266; + p32[ 78] = 0x39383132; + p32[ 79] = 0x66313336; + p32[ 80] = 0x33303138; + p32[ 81] = 0x61346566; + p32[ 82] = 0x61633963; + p32[ 83] = 0x30373932; + p32[ 84] = 0x64323130; + p32[ 85] = 0x36346435; + p32[ 86] = 0x38343230; + p32[ 87] = 0x30383430; + p32[ 88] = 0x31343831; + p32[ 89] = 0x34346163; + p32[ 90] = 0x39303733; + p32[ 91] = 0x39343835; + p32[ 92] = 0x30326233; + p32[ 93] = 0x34366535; + p32[ 94] = 0x33616437; + p32[ 95] = 0x62643430; + p32[ 96] = 0x62656334; + p32[ 97] = 0x62633830; + p32[ 98] = 0x62316462; + p32[ 99] = 0x34393361; + p32[100] = 0x37373439; + p32[101] = 0x39626636; + p32[102] = 0x34623838; + p32[103] = 0x34373137; + p32[104] = 0x38616364; + p32[105] = 0x65376338; + p32[106] = 0x35343932; + p32[107] = 0x61333832; + p32[108] = 0x38633130; + p32[109] = 0x00323739; + p32[110] = 0x64393433; + p32[111] = 0x37303863; + p32[112] = 0x62663466; + p32[113] = 0x34373366; + p32[114] = 0x65613466; + p32[115] = 0x33656461; + p32[116] = 0x39616362; + p32[117] = 0x34313335; + p32[118] = 0x38356464; + p32[119] = 0x39636563; + p32[120] = 0x37303366; + p32[121] = 0x66343561; + p32[122] = 0x31366366; + p32[123] = 0x30636665; + p32[124] = 0x38643630; + p32[125] = 0x39633261; + p32[126] = 0x37393464; + p32[127] = 0x61306339; + p32[128] = 0x61343463; + p32[129] = 0x34376165; + p32[130] = 0x62656266; + p32[131] = 0x66396262; + p32[132] = 0x61323737; + p32[133] = 0x62636465; + p32[134] = 0x62303236; + p32[135] = 0x37613130; + p32[136] = 0x61376162; + p32[137] = 0x33623166; + p32[138] = 0x33343032; + p32[139] = 0x35386330; + p32[140] = 0x38393139; + p32[141] = 0x30366634; + p32[142] = 0x34646331; + p32[143] = 0x33343163; + p32[144] = 0x63316665; + p32[145] = 0x00336137; + p32[146] = 0x00000044; + for(i = 147; i <= 154; i++) + p32[i] = 0x46464646; + + for(i = 155; i <= 159; i++) + p32[i] = 0x30303030; + + p32[160] = 0x31303030; + for(i = 161; i <= 190; i++) + p32[i] = 0x00000000; + + p32[191] = 0x000000ac; + p32[192] = 0x30303032; + for(i = 193; i <= 208; i++) + p32[i] = 0x30303030; + + p32[209] = 0x31303030; + p32[210] = 0x35383133; + p32[211] = 0x46314530; + p32[212] = 0x36413931; + p32[213] = 0x42344533; + p32[214] = 0x41313933; + p32[215] = 0x39424438; + p32[216] = 0x34463731; + p32[217] = 0x42383331; + p32[218] = 0x44303336; + p32[219] = 0x45423438; + p32[220] = 0x33364435; + p32[221] = 0x31383339; + p32[222] = 0x44313945; + p32[223] = 0x35344245; + p32[224] = 0x37454643; + p32[225] = 0x36463837; + p32[226] = 0x31433733; + p32[227] = 0x00313030; + for(i = 228; i <= 235; i++) + p32[i] = 0x00000000; + + p32[236] = 0x0000023b; + p32[237] = 0x0000000a; + p32[238] = 0x00000005; + p32[239] = 0x00000002; + p32[240] = 0x00000001; + return 0; + } + + return -1; +} + + + +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + if(CurveCpy((unsigned int *)&Curve_Copy, ecc_curve)) + return NULL; + else + return &Curve_Copy; + +} + + +#else +static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) +{ + uint32_t i; + ECC_CURVE *ret = NULL; + + for(i = 0UL; i < sizeof(_Curve) / sizeof(ECC_CURVE); i++) + { + if(ecc_curve == _Curve[i].curve_id) + { + memcpy((char *)&Curve_Copy, &_Curve[i], sizeof(ECC_CURVE)); + ret = &Curve_Copy; /* (ECC_CURVE *)&_Curve[i]; */ + } + if(ret != NULL) + { + break; + } + } + return ret; +} +#endif + + +/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group CRYPTO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/dac.c b/arch/riscv32/fe310/src/StdDriver/src/dac.c new file mode 100644 index 00000000..3c709f47 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/dac.c @@ -0,0 +1,94 @@ +/**************************************************************************//** + * @file dac.c + * @version V1.00 + * @brief M2351 series DAC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup DAC_Driver DAC Driver + @{ +*/ + +/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions + @{ +*/ + +/** + * @brief This function make DAC module be ready to convert. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @param[in] u32TrgSrc Decides the trigger source. Valid values are: + * - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger + * - \ref DAC_SOFTWARE_TRIGGER :Software trigger + * - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger + * - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger + * - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger + * - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger + * - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger + * - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger + * - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger + * - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger + * - \ref DAC_EPWM0_TRIGGER :EPWM0 trigger + * - \ref DAC_EPWM1_TRIGGER :EPWM1 trigger + * @return None + * @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger. + * When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register. + * When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1, + * external STDAC pin, timer event, or EPWM event. + */ +void DAC_Open(DAC_T *dac, + uint32_t u32Ch, + uint32_t u32TrgSrc) +{ + (void)u32Ch; + dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk); + + dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk); +} + +/** + * @brief Disable DAC analog power. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Ch Not used in M2351 Series DAC. + * @return None + * @details Disable DAC analog power for saving power consumption. + */ +void DAC_Close(DAC_T *dac, uint32_t u32Ch) +{ + (void)u32Ch; + dac->CTL &= (~DAC_CTL_DACEN_Msk); +} + +/** + * @brief Set delay time for DAC to become stable. + * @param[in] dac The pointer of the specified DAC module. + * @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds. + * @return Real DAC conversion settling time (micro second). + * @details For example, DAC controller clock speed is 64MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x40. + * @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed. + */ +uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay) +{ + + dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL); + + return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq()); +} + + + +/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group DAC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/eadc.c b/arch/riscv32/fe310/src/StdDriver/src/eadc.c new file mode 100644 index 00000000..b274ee68 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/eadc.c @@ -0,0 +1,145 @@ +/**************************************************************************//** + * @file eadc.c + * @version V2.00 + * @brief M2351 series EADC driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EADC_Driver EADC Driver + @{ +*/ + +/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions + @{ +*/ + +/** + * @brief This function make EADC_module be ready to convert. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32InputMode Decides the input mode. + * - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode. + * - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type. + * @return None + * @details This function is used to set analog input mode and enable A/D Converter. + * Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1. + * @note + */ +void EADC_Open(EADC_T *eadc, uint32_t u32InputMode) +{ + eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk)); + + eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk); + + while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk)) {} +} + +/** + * @brief Disable EADC_module. + * @param[in] eadc The pointer of the specified EADC module. + * @return None + * @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption. + */ +void EADC_Close(EADC_T *eadc) +{ + eadc->CTL &= ~EADC_CTL_ADCEN_Msk; +} + +/** + * @brief Configure the sample control logic module. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerSrc Decides the trigger source. Valid values are: + * - \ref EADC_SOFTWARE_TRIGGER : Disable trigger + * - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger + * - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger + * - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger + * - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger + * - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger + * - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger + * - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger + * - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger + * - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger + * - \ref EADC_PWM0TG0_TRIGGER : EPWM0TG0 trigger + * - \ref EADC_PWM0TG1_TRIGGER : EPWM0TG1 trigger + * - \ref EADC_PWM0TG2_TRIGGER : EPWM0TG2 trigger + * - \ref EADC_PWM0TG3_TRIGGER : EPWM0TG3 trigger + * - \ref EADC_PWM0TG4_TRIGGER : EPWM0TG4 trigger + * - \ref EADC_PWM0TG5_TRIGGER : EPWM0TG5 trigger + * - \ref EADC_PWM1TG0_TRIGGER : EPWM1TG0 trigger + * - \ref EADC_PWM1TG1_TRIGGER : EPWM1TG1 trigger + * - \ref EADC_PWM1TG2_TRIGGER : EPWM1TG2 trigger + * - \ref EADC_PWM1TG3_TRIGGER : EPWM1TG3 trigger + * - \ref EADC_PWM1TG4_TRIGGER : EPWM1TG4 trigger + * - \ref EADC_PWM1TG5_TRIGGER : EPWM1TG5 trigger + * - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger + * - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger + * @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15. + * @return None + * @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source. + * sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT). + */ +void EADC_ConfigSampleModule(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerSrc, \ + uint32_t u32Channel) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk); + eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel); +} + + +/** + * @brief Set trigger delay time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15. + * @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF. + * @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are: + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4 + * - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16 + * @return None + * @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15). + * Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period. + */ +void EADC_SetTriggerDelayTime(EADC_T *eadc, \ + uint32_t u32ModuleNum, \ + uint32_t u32TriggerDelayTime, \ + uint32_t u32DelayClockDivider) +{ + eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk); + eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider); +} + +/** + * @brief Set ADC extend sample time. + * @param[in] eadc The pointer of the specified EADC module. + * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18. + * @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF. + * @return None + * @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy, + * user can extend A/D sampling time after trigger source is coming to get enough sampling time. + */ +void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime) +{ + eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk; + + eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos); + +} + +/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EADC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/ebi.c b/arch/riscv32/fe310/src/StdDriver/src/ebi.c new file mode 100644 index 00000000..bd136b82 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/ebi.c @@ -0,0 +1,235 @@ +/**************************************************************************//** + * @file ebi.c + * @version V3.00 + * @brief External Bus Interface(EBI) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EBI_Driver EBI Driver + @{ +*/ + +/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions + @{ +*/ + +/** + * @brief Initialize EBI for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32DataWidth Data bus width. Valid values are: + * - \ref EBI_BUSWIDTH_8BIT + * - \ref EBI_BUSWIDTH_16BIT + * @param[in] u32TimingClass Default timing configuration. Valid values are: + * - \ref EBI_TIMING_FASTEST + * - \ref EBI_TIMING_VERYFAST + * - \ref EBI_TIMING_FAST + * - \ref EBI_TIMING_NORMAL + * - \ref EBI_TIMING_SLOW + * - \ref EBI_TIMING_VERYSLOW + * - \ref EBI_TIMING_SLOWEST + * @param[in] u32BusMode Set EBI bus operate mode. Valid values are: + * - \ref EBI_OPMODE_NORMAL + * - \ref EBI_OPMODE_CACCESS + * - \ref EBI_OPMODE_ADSEPARATE + * @param[in] u32CSActiveLevel CS is active High/Low. Valid values are: + * - \ref EBI_CS_ACTIVE_HIGH + * - \ref EBI_CS_ACTIVE_LOW + * + * @return None + * + * @details This function is used to open specify EBI bank with different bus width, timing setting and \n + * active level of CS pin to access EBI device. + * @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register. + */ +void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL, *pu32EBITCTL; + uint32_t pu32Index0, pu32Index1; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index0 = (u32Index0 + NS_OFFSET); + pu32Index1 = (u32Index1 + NS_OFFSET); + } + else + { + pu32Index0 = u32Index0; + pu32Index1 = u32Index1; + } + + pu32EBICTL = (uint32_t *)(pu32Index0); + pu32EBITCTL = (uint32_t *)(pu32Index1); + + if(u32DataWidth == EBI_BUSWIDTH_8BIT) + { + *pu32EBICTL &= ~EBI_CTL_DW16_Msk; + } + else + { + *pu32EBICTL |= EBI_CTL_DW16_Msk; + } + + *pu32EBICTL |= u32BusMode; + + switch(u32TimingClass) + { + case EBI_TIMING_FASTEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_VERYFAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_FAST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk; + *pu32EBITCTL = 0x0U; + break; + + case EBI_TIMING_NORMAL: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x3U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x03003318U; + break; + + case EBI_TIMING_SLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_VERYSLOW: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + case EBI_TIMING_SLOWEST: + *pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) | + (EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) | + (u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk | + (0x7U << EBI_CTL_TALE_Pos) ; + *pu32EBITCTL = 0x07007738U; + break; + + default: + *pu32EBICTL &= ~EBI_CTL_EN_Msk; + break; + } +} + +/** + * @brief Disable EBI on specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * + * @return None + * + * @details This function is used to close specify EBI function. + */ +void EBI_Close(uint32_t u32Bank) +{ + uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL; + uint32_t pu32Index; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index = (u32Index + NS_OFFSET); + } + else + { + pu32Index = u32Index; + } + + pu32EBICTL = (uint32_t *)(pu32Index); + + *pu32EBICTL &= ~EBI_CTL_EN_Msk; +} + +/** + * @brief Set EBI Bus Timing for specify Bank + * + * @param[in] u32Bank Bank number for EBI. Valid values are: + * - \ref EBI_BANK0 + * - \ref EBI_BANK1 + * - \ref EBI_BANK2 + * @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting. + * @param[in] u32MclkDiv Divider for MCLK. Valid values are: + * - \ref EBI_MCLKDIV_1 + * - \ref EBI_MCLKDIV_2 + * - \ref EBI_MCLKDIV_4 + * - \ref EBI_MCLKDIV_8 + * - \ref EBI_MCLKDIV_16 + * - \ref EBI_MCLKDIV_32 + * - \ref EBI_MCLKDIV_64 + * - \ref EBI_MCLKDIV_128 + * + * @return None + * + * @details This function is used to configure specify EBI bus timing for access EBI device. + */ +void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv) +{ + uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U; + uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U; + volatile uint32_t *pu32EBICTL, *pu32EBITCTL; + uint32_t pu32Index0, pu32Index1; + + if((__PC()&NS_OFFSET) == NS_OFFSET) + { + pu32Index0 = (u32Index0 + NS_OFFSET); + pu32Index1 = (u32Index1 + NS_OFFSET); + } + else + { + pu32Index0 = u32Index0; + pu32Index1 = u32Index1; + } + + pu32EBICTL = (uint32_t *)(pu32Index0); + pu32EBITCTL = (uint32_t *)(pu32Index1); + + *pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos); + *pu32EBITCTL = u32TimingConfig; +} + +/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EBI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/ecap.c b/arch/riscv32/fe310/src/StdDriver/src/ecap.c new file mode 100644 index 00000000..4d90c581 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/ecap.c @@ -0,0 +1,122 @@ +/**************************************************************************//** + * @file ecap.c + * @version V3.00 + + * @brief Enhanced Input Capture Timer (ECAP) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "M2351.h" + + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup ECAP_Driver ECAP Driver + @{ +*/ + +/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions + @{ +*/ + +/** + * @brief Enable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @param[in] u32FuncMask Input capture function select + * - \ref ECAP_DISABLE_COMPARE + * - \ref ECAP_COMPARE_FUNCTION + * @return None + * @details This macro enable input capture function and select compare and reload function. + */ +void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask) +{ + /* Clear Input capture mode*/ + ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_CMPEN_Msk); + + /* Enable Input Capture and set mode */ + ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk | (u32FuncMask); +} + + + +/** + * @brief Disable ECAP function + * @param[in] ecap The pointer of the specified ECAP module. + * @return None + * @details This macro disable input capture function. + */ +void ECAP_Close(ECAP_T* ecap) +{ + /* Disable Input Capture*/ + ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk; +} + +/** + * @brief This macro is used to enable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel Mask + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will enable the input channel_n interrupt. + */ +void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Enable input channel interrupt */ + ecap->CTL0 |= (u32Mask); + + /* Enable NVIC ECAP IRQ */ + if((ecap == ECAP0) || (ecap == ECAP0_NS)) + { + NVIC_EnableIRQ(ECAP0_IRQn); + } + else + { + NVIC_EnableIRQ(ECAP1_IRQn); + } +} + +/** + * @brief This macro is used to disable input channel interrupt + * @param[in] ecap Specify ECAP port + * @param[in] u32Mask The input channel number + * - \ref ECAP_CTL0_CAPIEN0_Msk + * - \ref ECAP_CTL0_CAPIEN1_Msk + * - \ref ECAP_CTL0_CAPIEN2_Msk + * - \ref ECAP_CTL0_OVIEN_Msk + * - \ref ECAP_CTL0_CMPIEN_Msk + * @return None + * @details This macro will disable the input channel_n interrupt. + */ +void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask) +{ + /* Disable input channel interrupt */ + (ecap->CTL0) &= ~(u32Mask); + + /* Disable NVIC ECAP IRQ */ + if((ecap == ECAP0) || (ecap == ECAP0_NS)) + { + NVIC_DisableIRQ(ECAP0_IRQn); + } + else + { + NVIC_DisableIRQ(ECAP1_IRQn); + } +} + +/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group ECAP_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/epwm.c b/arch/riscv32/fe310/src/StdDriver/src/epwm.c new file mode 100644 index 00000000..0626eab8 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/epwm.c @@ -0,0 +1,1399 @@ +/**************************************************************************//** + * @file epwm.c + * @version V3.00 + * @brief M2351 series EPWM driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup EPWM_Driver EPWM Driver + @{ +*/ + + +/** @addtogroup EPWM_EXPORTED_FUNCTIONS EPWM Exported Functions + @{ +*/ + +/** + * @brief Configure EPWM capture and get the nearest unit time. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32UnitTimeNsec The unit time of counter + * @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used + * @return The nearest unit time in nano second. + * @details This function is used to Configure EPWM capture and get the nearest unit time. + */ +uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) +{ + uint32_t u32PWMClockSrc; + uint32_t u32NearestUnitTimeNsec = 0U; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + uint8_t u8BreakLoop = 0U; + + (void)u32CaptureEdge; + /* clock source is from PCLK */ + if((epwm == EPWM0) || (epwm == EPWM0_NS)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + u32PWMClockSrc /= 1000UL; + for(u32Prescale = 1U; u32Prescale <= 0x1000U; u32Prescale++) + { + u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc; + if(u32NearestUnitTimeNsec < u32UnitTimeNsec) + { + if(u32Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ + { + u8BreakLoop = 1U; + } + if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) + { + u8BreakLoop = 1U; + } + } + else + { + u8BreakLoop = 1U; + } + if(u8BreakLoop) + { + break; + } + } + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* every two channels share a prescaler */ + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + + /* set EPWM to down count type(edge aligned) */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1)); + /* set EPWM to auto-reload mode */ + (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + + return (u32NearestUnitTimeNsec); +} + +/** + * @brief This function Configure EPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Frequency Target generator frequency + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%... + * @return Nearest frequency clock in nano second + * @note Since every two channels, (0 & 1), (2 & 3), shares a prescaler. Call this API to configure EPWM frequency may affect + * existing frequency of other channel. + * @note This function is used for initial stage. + * To change duty cycle later, it should get the configured period value and calculate the new comparator value. + */ +uint32_t EPWM_ConfigOutputChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockSrc; + uint32_t i; + uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU; + + /* clock source is from PCLK */ + if((epwm == EPWM0) || (epwm == EPWM0_NS)) + { + u32PWMClockSrc = CLK_GetPCLK0Freq(); + } + else /* if((epwm == EPWM1)||(epwm == EPWM1_NS)) */ + { + u32PWMClockSrc = CLK_GetPCLK1Freq(); + } + + for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */ + { + i = (u32PWMClockSrc / u32Frequency) / u32Prescale; + /* If target value is larger than CNR, need to use a larger prescaler */ + if(i <= (0x10000U)) + { + u32CNR = i; + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */ + i = u32PWMClockSrc / (u32Prescale * u32CNR); + + /* convert to real register value */ + u32Prescale = u32Prescale - 1U; + /* every two channels share a prescaler */ + EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale); + /* set EPWM to up counter type(edge aligned) and auto-reload mode */ + (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum))); + + u32CNR = u32CNR - 1U; + EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR); + EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL); + + (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ + (EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos)); + (epwm)->WGCTL1 = ((epwm)->WGCTL1 & ~((EPWM_WGCTL1_CMPDCTL0_Msk | EPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \ + (EPWM_OUTPUT_LOW << (u32ChannelNum << 1UL << EPWM_WGCTL1_CMPUCTL0_Pos)); + + return(i); +} + +/** + * @brief Start EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to start EPWM module. + */ +void EPWM_Start(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN |= u32ChannelMask; +} + +/** + * @brief Stop EPWM module + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM module. + */ +void EPWM_Stop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->PERIOD[i] = 0UL; + } + } +} + +/** + * @brief Stop EPWM generation immediately by clear channel enable bit + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to stop EPWM generation immediately by clear channel enable bit. + */ +void EPWM_ForceStop(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CNTEN &= ~u32ChannelMask; +} + +/** + * @brief Enable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger ADC. Combination of following conditions: + * - \ref EPWM_TRG_ADC_EVEN_ZERO + * - \ref EPWM_TRG_ADC_EVEN_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_UP + * - \ref EPWM_TRG_ADC_EVEN_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_ODD_ZERO + * - \ref EPWM_TRG_ADC_ODD_PERIOD + * - \ref EPWM_TRG_ADC_ODD_ZERO_PERIOD + * - \ref EPWM_TRG_ADC_ODD_COMPARE_UP + * - \ref EPWM_TRG_ADC_ODD_COMPARE_DOWN + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_0_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_2_FREE_CMP_DOWN + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_UP + * - \ref EPWM_TRG_ADC_CH_4_FREE_CMP_DOWN + * @return None + * @details This function is used to enable selected channel to trigger ADC. + */ +void EPWM_EnableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + if(u32ChannelNum < 4UL) + { + (epwm)->EADCTS0 &= ~((EPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum << 3)); + (epwm)->EADCTS0 |= ((EPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~((EPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4UL) << 3)); + (epwm)->EADCTS1 |= ((EPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Disable selected channel to trigger ADC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger ADC. + */ +void EPWM_DisableADCTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + if(u32ChannelNum < 4UL) + { + (epwm)->EADCTS0 &= ~(EPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum << 3)); + } + else + { + (epwm)->EADCTS1 &= ~(EPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4UL) << 3)); + } +} + +/** + * @brief Clear selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger ADC flag. + */ +void EPWM_ClearADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32Condition; + (epwm)->STATUS = (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum); +} + +/** + * @brief Get selected channel trigger ADC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 The specified channel trigger ADC to start of conversion flag is not set + * @retval 1 The specified channel trigger ADC to start of conversion flag is set + * @details This function is used to get EPWM trigger ADC to start of conversion flag for specified channel. + */ +uint32_t EPWM_GetADCTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_EADCTRGF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Enable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Condition The condition to trigger DAC. Combination of following conditions: + * - \ref EPWM_TRIGGER_DAC_ZERO + * - \ref EPWM_TRIGGER_DAC_PERIOD + * - \ref EPWM_TRIGGER_DAC_COMPARE_UP + * - \ref EPWM_TRIGGER_DAC_COMPARE_DOWN + * @return None + * @details This function is used to enable selected channel to trigger DAC. + */ +void EPWM_EnableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (epwm)->DACTRGEN |= (u32Condition << u32ChannelNum); +} + +/** + * @brief Disable selected channel to trigger DAC + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable selected channel to trigger DAC. + */ +void EPWM_DisableDACTrigger(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->DACTRGEN &= ~((EPWM_TRIGGER_DAC_ZERO | EPWM_TRIGGER_DAC_PERIOD | EPWM_TRIGGER_DAC_COMPARE_UP | EPWM_TRIGGER_DAC_COMPARE_DOWN) << u32ChannelNum); +} + +/** + * @brief Clear selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @param[in] u32Condition The condition to trigger DAC. This parameter is not used + * @return None + * @details This function is used to clear selected channel trigger DAC flag. + */ +void EPWM_ClearDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Condition) +{ + (void)u32ChannelNum; + (void)u32Condition; + (epwm)->STATUS = EPWM_STATUS_DACTRGF_Msk; +} + +/** + * @brief Get selected channel trigger DAC flag + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. This parameter is not used + * @retval 0 The specified channel trigger DAC to start of conversion flag is not set + * @retval 1 The specified channel trigger DAC to start of conversion flag is set + * @details This function is used to get selected channel trigger DAC flag. + */ +uint32_t EPWM_GetDACTriggerFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (void)u32ChannelNum; + return (((epwm)->STATUS & EPWM_STATUS_DACTRGF_Msk) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * @param[in] u32LevelMask Output high or low while fault brake occurs, each bit represent the level of a channel + * while fault brake occurs. Bit 0 represents channel 0, bit 1 represents channel 1... + * @param[in] u32BrakeSource Fault brake source, could be one of following source + * - \ref EPWM_FB_EDGE_ADCRM + * - \ref EPWM_FB_EDGE_ACMP0 + * - \ref EPWM_FB_EDGE_ACMP1 + * - \ref EPWM_FB_EDGE_BKP0 + * - \ref EPWM_FB_EDGE_BKP1 + * - \ref EPWM_FB_EDGE_SYS_CSS + * - \ref EPWM_FB_EDGE_SYS_BOD + * - \ref EPWM_FB_EDGE_SYS_RAM + * - \ref EPWM_FB_EDGE_SYS_COR + * - \ref EPWM_FB_LEVEL_ADCRM + * - \ref EPWM_FB_LEVEL_ACMP0 + * - \ref EPWM_FB_LEVEL_ACMP1 + * - \ref EPWM_FB_LEVEL_BKP0 + * - \ref EPWM_FB_LEVEL_BKP1 + * - \ref EPWM_FB_LEVEL_SYS_CSS + * - \ref EPWM_FB_LEVEL_SYS_BOD + * - \ref EPWM_FB_LEVEL_SYS_RAM + * - \ref EPWM_FB_LEVEL_SYS_COR + * @return None + * @details This function is used to enable fault brake of selected channel(s). + * The write-protection function should be disabled before using this function. + */ +void EPWM_EnableFaultBrake(EPWM_T *epwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource) +{ + uint32_t i; + + for(i = 0UL; i < EPWM_CHANNEL_NUM; i++) + { + if(u32ChannelMask & (1UL << i)) + { + if((u32BrakeSource == EPWM_FB_EDGE_SYS_CSS) || (u32BrakeSource == EPWM_FB_EDGE_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_EDGE_SYS_RAM) || (u32BrakeSource == EPWM_FB_EDGE_SYS_COR) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_CSS) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_BOD) || \ + (u32BrakeSource == EPWM_FB_LEVEL_SYS_RAM) || (u32BrakeSource == EPWM_FB_LEVEL_SYS_COR)) + { + (epwm)->BRKCTL[i >> 1] |= (u32BrakeSource & (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_BRKCTL0_1_SYSLBEN_Msk)); + (epwm)->FAILBRK |= (u32BrakeSource & 0xFUL); + } + else + { + (epwm)->BRKCTL[i >> 1] |= u32BrakeSource; + } + } + + if(u32LevelMask & (1UL << i)) + { + if((i & 0x1UL) == 0UL) + { + /* set brake action as high level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as high level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((3UL) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + else + { + if((i & 0x1UL) == 0UL) + { + /* set brake action as low level for even channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAEVEN_Msk; + (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAEVEN_Pos); + } + else + { + /* set brake action as low level for odd channel */ + (epwm)->BRKCTL[i >> 1] &= ~EPWM_BRKCTL0_1_BRKAODD_Msk; + (epwm)->BRKCTL[i >> 1] |= ((2UL) << EPWM_BRKCTL0_1_BRKAODD_Pos); + } + } + } +} + +/** + * @brief Enable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable capture of selected channel(s). + */ +void EPWM_EnableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN |= u32ChannelMask; + (epwm)->CAPCTL |= u32ChannelMask; +} + +/** + * @brief Disable capture of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable capture of selected channel(s). + */ +void EPWM_DisableCapture(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->CAPINEN &= ~u32ChannelMask; + (epwm)->CAPCTL &= ~u32ChannelMask; +} + +/** + * @brief Enables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output... + * @return None + * @details This function is used to enable EPWM output generation of selected channel(s). + */ +void EPWM_EnableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN |= u32ChannelMask; +} + +/** + * @brief Disables EPWM output generation of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel + * Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output... + * @return None + * @details This function is used to disable EPWM output generation of selected channel(s). + */ +void EPWM_DisableOutput(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + (epwm)->POEN &= ~u32ChannelMask; +} + +/** + * @brief Enables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @param[in] u32RisingFirst The capture order is rising, falling first. Every two channels share the same setting. Valid values are TRUE and FALSE. + * @param[in] u32Mode Captured data transferred by PDMA interrupt type. It could be either + * - \ref EPWM_CAPTURE_PDMA_RISING_LATCH + * - \ref EPWM_CAPTURE_PDMA_FALLING_LATCH + * - \ref EPWM_CAPTURE_PDMA_RISING_FALLING_LATCH + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + * @note This function can only selects even or odd channel of pairs to do PDMA transfer. + */ +void EPWM_EnablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode) +{ + uint32_t u32IsOddCh; + u32IsOddCh = u32ChannelNum & 0x1UL; + (epwm)->PDMACTL = ((epwm)->PDMACTL & ~((EPWM_PDMACTL_CHSEL0_1_Msk | EPWM_PDMACTL_CAPORD0_1_Msk | EPWM_PDMACTL_CAPMOD0_1_Msk) << ((u32ChannelNum >> 1) << 3))) | \ + (((u32IsOddCh << EPWM_PDMACTL_CHSEL0_1_Pos) | (u32RisingFirst << EPWM_PDMACTL_CAPORD0_1_Pos) | \ + u32Mode | EPWM_PDMACTL_CHEN0_1_Msk) << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Disables PDMA transfer of selected channel for EPWM capture + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. + * @return None + * @details This function is used to enable PDMA transfer of selected channel(s) for EPWM capture. + */ +void EPWM_DisablePDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->PDMACTL &= ~(EPWM_PDMACTL_CHEN0_1_Msk << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Enable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Duration Dead zone length in EPWM clock count, valid values are between 0~0xFFF, but 0 means there is no Dead zone. + * @return None + * @details This function is used to enable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Duration) +{ + /* every two channels share the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTCNT_Msk; + (epwm)->DTCTL[(u32ChannelNum) >> 1] |= EPWM_DTCTL0_1_DTEN_Msk | u32Duration; +} + +/** + * @brief Disable Dead zone of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable Dead zone of selected channel. + * The write-protection function should be disabled before using this function. + */ +void EPWM_DisableDeadZone(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + /* every two channels shares the same setting */ + (epwm)->DTCTL[(u32ChannelNum) >> 1] &= ~EPWM_DTCTL0_1_DTEN_Msk; +} + +/** + * @brief Enable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to enable capture interrupt of selected channel. + */ +void EPWM_EnableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN |= (u32Edge << u32ChannelNum); +} + +/** + * @brief Disable capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to disable capture interrupt of selected channel. + */ +void EPWM_DisableCaptureInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIEN &= ~(u32Edge << u32ChannelNum); +} + +/** + * @brief Clear capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32Edge Rising or falling edge to latch counter. + * - \ref EPWM_CAPTURE_INT_RISING_LATCH + * - \ref EPWM_CAPTURE_INT_FALLING_LATCH + * @return None + * @details This function is used to clear capture interrupt of selected channel. + */ +void EPWM_ClearCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32Edge) +{ + (epwm)->CAPIF = (u32Edge << u32ChannelNum); +} + +/** + * @brief Get capture interrupt of selected channel. + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 No capture interrupt + * @retval 1 Rising edge latch interrupt + * @retval 2 Falling edge latch interrupt + * @retval 3 Rising and falling latch interrupt + * @details This function is used to get capture interrupt of selected channel. + */ +uint32_t EPWM_GetCaptureIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + uint32_t u32CapIf = 0UL; + + u32CapIf = ((((epwm)->CAPIF & (EPWM_CAPIF_CFLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL) << 1); + u32CapIf |= (((epwm)->CAPIF & (EPWM_CAPIF_CRLIF0_Msk << u32ChannelNum)) ? 1UL : 0UL); + return u32CapIf; +} +/** + * @brief Enable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntDutyType Duty interrupt type, could be either + * - \ref EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP + * - \ref EPWM_DUTY_INT_UP_COUNT_MATCH_CMP + * @return None + * @details This function is used to enable duty interrupt of selected channel. + */ +void EPWM_EnableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType) +{ + (epwm)->INTEN0 |= (u32IntDutyType << u32ChannelNum); +} + +/** + * @brief Disable duty interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable duty interrupt of selected channel. + */ +void EPWM_DisableDutyInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~((EPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | EPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); +} + +/** + * @brief Clear duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear duty interrupt flag of selected channel. + */ +void EPWM_ClearDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_CMPUIF0_Msk | EPWM_INTSTS0_CMPDIF0_Msk) << u32ChannelNum; +} + +/** + * @brief Get duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Duty interrupt did not occur + * @retval 1 Duty interrupt occurred + * @details This function is used to get duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & ((EPWM_INTSTS0_CMPDIF0_Msk | EPWM_INTSTS0_CMPUIF0_Msk) << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief This function enable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to enable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_EnableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 |= (0x7UL << u32BrakeSource); +} + +/** + * @brief This function disable fault brake interrupt + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to disable fault brake interrupt. + * The write-protection function should be disabled before using this function. + * @note Every two channels share the same setting. + */ +void EPWM_DisableFaultBrakeInt(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTEN1 &= ~(0x7UL << u32BrakeSource); +} + +/** + * @brief This function clear fault brake interrupt of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source. + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return None + * @details This function is used to clear fault brake interrupt of selected source. + * The write-protection function should be disabled before using this function. + */ +void EPWM_ClearFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + (epwm)->INTSTS1 = (0x3fUL << u32BrakeSource); +} + +/** + * @brief This function get fault brake interrupt flag of selected source + * @param[in] epwm The pointer of the specified EPWM module + * @param[in] u32BrakeSource Fault brake source, could be either + * - \ref EPWM_FB_EDGE + * - \ref EPWM_FB_LEVEL + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * @details This function is used to get fault brake interrupt flag of selected source. + */ +uint32_t EPWM_GetFaultBrakeIntFlag(EPWM_T *epwm, uint32_t u32BrakeSource) +{ + return (((epwm)->INTSTS1 & (0x3fUL << u32BrakeSource)) ? 1UL : 0UL); +} + +/** + * @brief Enable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntPeriodType Period interrupt type. This parameter is not used. + * @return None + * @details This function is used to enable period interrupt of selected channel. + */ +void EPWM_EnablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType) +{ + (void)u32IntPeriodType; + (epwm)->INTEN0 |= (EPWM_INTEN0_PIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Disable period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable period interrupt of selected channel. + */ +void EPWM_DisablePeriodInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~(EPWM_INTEN0_PIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear period interrupt of selected channel. + */ +void EPWM_ClearPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum); +} + +/** + * @brief Get period interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Period interrupt flag of specified channel + * @retval 0 Period interrupt did not occur + * @retval 1 Period interrupt occurred + * @details This function is used to get period interrupt of selected channel. + */ +uint32_t EPWM_GetPeriodIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_PIF0_Msk << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable zero interrupt of selected channel. + */ +void EPWM_EnableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 |= (EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Disable zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable zero interrupt of selected channel. + */ +void EPWM_DisableZeroInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTEN0 &= ~(EPWM_INTEN0_ZIEN0_Msk << u32ChannelNum); +} + +/** + * @brief Clear zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear zero interrupt of selected channel. + */ +void EPWM_ClearZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->INTSTS0 = (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum); +} + +/** + * @brief Get zero interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Zero interrupt flag of specified channel + * @retval 0 Zero interrupt did not occur + * @retval 1 Zero interrupt occurred + * @details This function is used to get zero interrupt of selected channel. + */ +uint32_t EPWM_GetZeroIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return ((((epwm)->INTSTS0 & (EPWM_INTSTS0_ZIF0_Msk << u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32IntFlagCnt Interrupt flag counter. Valid values are between 0~65535. + * @param[in] u32IntAccSrc Interrupt flag accumulator source selection. + * - \ref EPWM_IFA_ZERO_POINT + * - \ref EPWM_IFA_PERIOD_POINT + * - \ref EPWM_IFA_COMPARE_UP_COUNT_POINT + * - \ref EPWM_IFA_COMPARE_DOWN_COUNT_POINT + * @return None + * @details This function is used to enable interrupt flag accumulator of selected channel. + */ +void EPWM_EnableAcc(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc) +{ + (epwm)->IFA[u32ChannelNum] = (((epwm)->IFA[u32ChannelNum] & ~((EPWM_IFA0_IFACNT_Msk | EPWM_IFA0_IFASEL_Msk))) | \ + (EPWM_IFA0_IFAEN_Msk | (u32IntAccSrc << EPWM_IFA0_IFASEL_Pos) | u32IntFlagCnt)); +} + +/** + * @brief Disable interrupt flag accumulator of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to Disable interrupt flag accumulator of selected channel. + */ +void EPWM_DisableAcc(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->IFA[u32ChannelNum] = ((epwm)->IFA[u32ChannelNum] & ~(EPWM_IFA0_IFAEN_Msk)); +} + +/** + * @brief Enable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_EnableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_DisableAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTEN &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear interrupt flag accumulator interrupt of selected channel. + */ +void EPWM_ClearAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->AINTSTS = (1UL << (u32ChannelNum)); +} + +/** + * @brief Get interrupt flag accumulator interrupt of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @retval 0 Accumulator interrupt did not occur + * @retval 1 Accumulator interrupt occurred + * @details This function is used to Get interrupt flag accumulator interrupt of selected channel. + */ +uint32_t EPWM_GetAccInt(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->AINTSTS & (1UL << (u32ChannelNum))) ? 1UL : 0UL); +} + +/** + * @brief Enable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to enable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_EnableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL |= (1UL << (u32ChannelNum)); +} + +/** + * @brief Disable accumulator PDMA of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to disable accumulator interrupt trigger PDMA of selected channel. + */ +void EPWM_DisableAccPDMA(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->APDMACTL &= ~(1UL << (u32ChannelNum)); +} + +/** + * @brief Clear free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear free trigger duty interrupt flag of selected channel. + */ +void EPWM_ClearFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->FTCI = ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1)); +} + +/** + * @brief Get free trigger duty interrupt flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Duty interrupt flag of specified channel + * @retval 0 Free trigger duty interrupt did not occur + * @retval 1 Free trigger duty interrupt occurred + * @details This function is used to get free trigger duty interrupt flag of selected channel. + */ +uint32_t EPWM_GetFTDutyIntFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->FTCI & ((EPWM_FTCI_FTCMU0_Msk | EPWM_FTCI_FTCMD0_Msk) << (u32ChannelNum >> 1))) ? 1UL : 0UL); +} + +/** + * @brief Enable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to enable load mode of selected channel. + */ +void EPWM_EnableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 |= (u32LoadMode << u32ChannelNum); +} + +/** + * @brief Disable load mode of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32LoadMode EPWM counter loading mode. + * - \ref EPWM_LOAD_MODE_IMMEDIATE + * - \ref EPWM_LOAD_MODE_WINDOW + * - \ref EPWM_LOAD_MODE_CENTER + * @return None + * @details This function is used to disable load mode of selected channel. + */ +void EPWM_DisableLoadMode(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32LoadMode) +{ + (epwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum); +} + +/** + * @brief Configure synchronization phase of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32SyncSrc EPWM synchronize source selection. + * - \ref EPWM_SYNC_OUT_FROM_SYNCIN_SWSYNC + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_ZERO + * - \ref EPWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR + * - \ref EPWM_SYNC_OUT_DISABLE + * @param[in] u32Direction Phase direction. Control EPWM counter count decrement or increment after synchronizing. + * - \ref EPWM_PHS_DIR_DECREMENT + * - \ref EPWM_PHS_DIR_INCREMENT + * @param[in] u32StartPhase Synchronous start phase value. Valid values are between 0~65535. + * @return None + * @details This function is used to configure synchronization phase of selected channel. + * @note Every two channels share the same setting. + */ +void EPWM_ConfigSyncPhase(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase) +{ + /* every two channels shares the same setting */ + u32ChannelNum >>= 1; + (epwm)->SYNC = (((epwm)->SYNC & ~((EPWM_SYNC_SINSRC0_Msk << (u32ChannelNum << 1)) | (EPWM_SYNC_PHSDIR0_Msk << u32ChannelNum))) | \ + (u32Direction << EPWM_SYNC_PHSDIR0_Pos << u32ChannelNum) | (u32SyncSrc << EPWM_SYNC_SINSRC0_Pos) << (u32ChannelNum << 1)); + (epwm)->PHS[(u32ChannelNum)] = u32StartPhase; +} + + +/** + * @brief Enable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to enable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_EnableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC |= (EPWM_SYNC_PHSEN0_Msk << (i >> 1)); + } + } +} + +/** + * @brief Disable SYNC phase of selected channel(s) + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel. + * Bit 0 is channel 0, bit 1 is channel 1... + * @return None + * @details This function is used to disable SYNC phase of selected channel(s). + * @note Every two channels share the same setting. + */ +void EPWM_DisableSyncPhase(EPWM_T *epwm, uint32_t u32ChannelMask) +{ + uint32_t i; + for(i = 0UL; i < EPWM_CHANNEL_NUM; i ++) + { + if(u32ChannelMask & (1UL << i)) + { + (epwm)->SYNC &= ~(EPWM_SYNC_PHSEN0_Msk << (i >> 1)); + } + } +} + +/** + * @brief Enable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector. + * The valid value is 0~7. + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM SYNC_IN noise filter function. + */ +void EPWM_EnableSyncNoiseFilter(EPWM_T *epwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->SYNC = ((epwm)->SYNC & ~(EPWM_SYNC_SFLTCNT_Msk | EPWM_SYNC_SFLTCSEL_Msk)) | \ + ((u32ClkCnt << EPWM_SYNC_SFLTCNT_Pos) | (u32ClkDivSel << EPWM_SYNC_SFLTCSEL_Pos) | EPWM_SYNC_SNFLTEN_Msk); +} + +/** + * @brief Disable EPWM SYNC_IN noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC_IN noise filter function. + */ +void EPWM_DisableSyncNoiseFilter(EPWM_T *epwm) +{ + (epwm)->SYNC &= ~EPWM_SYNC_SNFLTEN_Msk; +} + +/** + * @brief Enable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to enable EPWM SYNC input pin inverse function. + */ +void EPWM_EnableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC |= EPWM_SYNC_SINPINV_Msk; +} + +/** + * @brief Disable EPWM SYNC input pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @return None + * @details This function is used to Disable EPWM SYNC input pin inverse function. + */ +void EPWM_DisableSyncPinInverse(EPWM_T *epwm) +{ + (epwm)->SYNC &= (~EPWM_SYNC_SINPINV_Msk); +} + +/** + * @brief Set EPWM clock source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @param[in] u32ClkSrcSel EPWM external clock source. + * - \ref EPWM_CLKSRC_EPWM_CLK + * - \ref EPWM_CLKSRC_TIMER0 + * - \ref EPWM_CLKSRC_TIMER1 + * - \ref EPWM_CLKSRC_TIMER2 + * - \ref EPWM_CLKSRC_TIMER3 + * @return None + * @details This function is used to set EPWM clock source. + * @note Every two channels share the same setting. + * @note If the clock source of EPWM counter is selected from TIMERn interrupt events, the TRGEPWM(TIMERn_TRGCTL[1], n=0,1..3) bit must be set as 1. + */ +void EPWM_SetClockSource(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel) +{ + (epwm)->CLKSRC = ((epwm)->CLKSRC & ~(EPWM_CLKSRC_ECLKSRC0_Msk << ((u32ChannelNum >> 1) << 3))) | \ + (u32ClkSrcSel << ((u32ChannelNum >> 1) << 3)); +} + +/** + * @brief Enable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32ClkCnt SYNC Edge Detector Filter Count. This controls the counter number of edge detector + * @param[in] u32ClkDivSel SYNC Edge Detector Filter Clock Selection. + * - \ref EPWM_NF_CLK_DIV_1 + * - \ref EPWM_NF_CLK_DIV_2 + * - \ref EPWM_NF_CLK_DIV_4 + * - \ref EPWM_NF_CLK_DIV_8 + * - \ref EPWM_NF_CLK_DIV_16 + * - \ref EPWM_NF_CLK_DIV_32 + * - \ref EPWM_NF_CLK_DIV_64 + * - \ref EPWM_NF_CLK_DIV_128 + * @return None + * @details This function is used to enable EPWM brake noise filter function. + */ +void EPWM_EnableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel) +{ + (epwm)->BNF = ((epwm)->BNF & ~((EPWM_BNF_BRK0FCNT_Msk | EPWM_BNF_BRK0NFSEL_Msk) << (u32BrakePinNum << 3))) | \ + (((u32ClkCnt << EPWM_BNF_BRK0FCNT_Pos) | (u32ClkDivSel << EPWM_BNF_BRK0NFSEL_Pos) | EPWM_BNF_BRK0NFEN_Msk) << (u32BrakePinNum << 3)); +} + +/** + * @brief Disable EPWM brake noise filter function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake noise filter function. + */ +void EPWM_DisableBrakeNoiseFilter(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0NFEN_Msk << (u32BrakePinNum << 3)); +} + +/** + * @brief Enable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to enable EPWM brake pin inverse function. + */ +void EPWM_EnableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF |= (EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum << 3)); +} + +/** + * @brief Disable EPWM brake pin inverse function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @return None + * @details This function is used to disable EPWM brake pin inverse function. + */ +void EPWM_DisableBrakePinInverse(EPWM_T *epwm, uint32_t u32BrakePinNum) +{ + (epwm)->BNF &= ~(EPWM_BNF_BRK0PINV_Msk << (u32BrakePinNum * (uint32_t)EPWM_BNF_BRK1NFEN_Pos)); +} + +/** + * @brief Set EPWM brake pin source + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32BrakePinNum Brake pin selection. Valid values are 0 or 1. + * @param[in] u32SelAnotherModule Select to another module. Valid values are TRUE or FALSE. + * @return None + * @details This function is used to set EPWM brake pin source. + */ +void EPWM_SetBrakePinSource(EPWM_T *epwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule) +{ + (epwm)->BNF = ((epwm)->BNF & ~(EPWM_BNF_BK0SRC_Msk << (u32BrakePinNum << 3))) | (u32SelAnotherModule << ((uint32_t)EPWM_BNF_BK0SRC_Pos + (u32BrakePinNum << 3))); +} + +/** + * @brief Set EPWM leading edge blanking function + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32TrigSrcSel Leading edge blanking source selection. + * - \ref EPWM_LEBCTL_SRCEN0 + * - \ref EPWM_LEBCTL_SRCEN2 + * - \ref EPWM_LEBCTL_SRCEN4 + * - \ref EPWM_LEBCTL_SRCEN0_2 + * - \ref EPWM_LEBCTL_SRCEN0_4 + * - \ref EPWM_LEBCTL_SRCEN2_4 + * - \ref EPWM_LEBCTL_SRCEN0_2_4 + * @param[in] u32TrigType Leading edge blanking trigger type. + * - \ref EPWM_LEBCTL_TRGTYPE_RISING + * - \ref EPWM_LEBCTL_TRGTYPE_FALLING + * - \ref EPWM_LEBCTL_TRGTYPE_RISING_OR_FALLING + * @param[in] u32BlankingCnt Leading Edge Blanking Counter. Valid values are between 1~512. + This counter value decides leading edge blanking window size, and this counter clock base is ECLK. + * @param[in] u32BlankingEnable Enable EPWM leading edge blanking function. Valid values are TRUE (ENABLE) or FALSE (DISABLE). + * - \ref FALSE + * - \ref TRUE + * @return None + * @details This function is used to configure EPWM leading edge blanking function that blank the false trigger from ACMP brake source which may cause by EPWM output transition. + * @note EPWM leading edge blanking function is only used for brake source from ACMP. + */ +void EPWM_SetLeadingEdgeBlanking(EPWM_T *epwm, uint32_t u32TrigSrcSel, uint32_t u32TrigType, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable) +{ + (epwm)->LEBCTL = (u32TrigType) | (u32TrigSrcSel) | (u32BlankingEnable); + /* Blanking window size = LEBCNT + 1, so LEBCNT = u32BlankingCnt - 1 */ + (epwm)->LEBCNT = (u32BlankingCnt) - 1UL; +} + +/** + * @brief Get the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return Count to max interrupt flag of specified channel + * @retval 0 Count to max interrupt did not occur + * @retval 1 Count to max interrupt occurred + * @details This function is used to get the time-base counter reached its maximum value flag of selected channel. + */ +uint32_t EPWM_GetWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + return (((epwm)->STATUS & (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum)) ? 1UL : 0UL); +} + +/** + * @brief Clear the time-base counter reached its maximum value flag of selected channel + * @param[in] epwm The pointer of the specified EPWM module + * - EPWM0 : EPWM Group 0 + * - EPWM1 : EPWM Group 1 + * @param[in] u32ChannelNum EPWM channel number. Valid values are between 0~5 + * @return None + * @details This function is used to clear the time-base counter reached its maximum value flag of selected channel. + */ +void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum) +{ + (epwm)->STATUS = (EPWM_STATUS_CNTMAXF0_Msk << u32ChannelNum); +} + + +/*@}*/ /* end of group EPWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group EPWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/fmc.c b/arch/riscv32/fe310/src/StdDriver/src/fmc.c new file mode 100644 index 00000000..0a664e48 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/fmc.c @@ -0,0 +1,1057 @@ +/**************************************************************************//** + * @file fmc.c + * @version V3.00 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2351 Series Flash Memory Controller(FMC) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup FMC_Driver FMC Driver + @{ +*/ + +/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions + @{ +*/ + +/** + * @brief Run flash all one verification and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes. + * + * @retval READ_ALLONE_YES The contents of verified flash area are 0xA11FFFFF. + * @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xA1100000. + * @retval READ_ALLONE_CMD_FAIL Unexpected error occurred. + * + * @details Run ISP check all one command to check specify area is all one or not. + */ +uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret = READ_ALLONE_CMD_FAIL; + + FMC->ISPSTS = 0x80UL; /* clear check all one bit */ + + FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + do + { + FMC->ISPCMD = FMC_ISPCMD_READ_ALL1; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + } + while(FMC->ISPDAT == 0UL); + + if(FMC->ISPDAT == READ_ALLONE_YES) + { + ret = FMC->ISPDAT; + } + + if(FMC->ISPDAT == READ_ALLONE_NOT) + { + ret = FMC->ISPDAT; + } + + return ret; +} + +/** + * @brief Disable ISP Functions + * + * @param None + * + * @return None + * + * @details This function will clear ISPEN bit of ISPCON to disable ISP function + * + */ +void FMC_Close(void) +{ + FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk; +} + +/** + * @brief Config XOM Region + * @param[in] u32XomNum The XOM number(0~3) + * @param[in] u32XomBase The XOM region base address. + * @param[in] u8XomPage The XOM page number of region size. + * + * @retval 0 Success + * @retval 1 XOM is has already actived. + * @retval -1 Program failed. + * @retval -2 Invalid XOM number. + * + * @details Program XOM base address and XOM size(page) + */ +int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage) +{ + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret == 0) + { + ret = FMC_GetXOMState(u32XomNum); + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u); + FMC->ISPDAT = u32XomBase; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u); + FMC->ISPDAT = u8XomPage; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u); + FMC->ISPDAT = 0u; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/** + * @brief Execute Flash Page erase + * + * @param[in] u32PageAddr Address of the flash page to be erased. + * It must be a 2048 bytes aligned address. + * + * @return ISP page erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase a flash page. The page size is 2048 bytes. + */ +int32_t FMC_Erase(uint32_t u32PageAddr) +{ + int32_t ret = 0; + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32PageAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Execute Flash Bank erase + * + * @param[in] u32BankAddr Base address of the flash bank to be erased. + * + * @return ISP bank erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @details Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block. + */ +int32_t FMC_Erase_Bank(uint32_t u32BankAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE; + FMC->ISPADDR = u32BankAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute Flash Block erase + * + * @param[in] u32BlockAddr Address of the flash block to be erased. + * It must be a 4 pages aligned address. + * + * @return ISP block erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * + * @details Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages. + */ +int32_t FMC_Erase_Block(uint32_t u32BlockAddr) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE; + FMC->ISPADDR = u32BlockAddr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} + + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Execute Erase XOM Region + * + * @param[in] u32XomNum The XOMRn(n=0~3) + * + * @return XOM erase success or not. + * @retval 0 Success + * @retval -1 Erase failed + * @retval -2 Invalid XOM number. + * + * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. + */ +int32_t FMC_EraseXOM(uint32_t u32XomNum) +{ + uint32_t u32Addr; + int32_t i32Active, err = 0; + + if(u32XomNum >= 4UL) + { + err = -2; + } + + if(err == 0) + { + i32Active = FMC_GetXOMState(u32XomNum); + + if(i32Active) + { + u32Addr = ( ( (uint32_t)(&FMC->XOMR0STS)[u32XomNum] ) & 0xFFFFFF00u ) >> 8u; + + FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = 0x55aa03u; + FMC->ISPTRG = 0x1u; +#if ISBEN + __ISB(); +#endif + while(FMC->ISPTRG) {} + + /* Check ISPFF flag to know whether erase OK or fail. */ + if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) + { + FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk; + err = -1; + } + } + else + { + err = -1; + } + } + return err; +} + +/** + * @brief Get the current boot source + * + * @param None + * + * @return The current boot source. + * @retval 0 This chip is currently booting from APROM + * @retval 1 This chip is currently booting from LDROM + * + * @note This function only show the boot source. + * User need to read ISPSTA register to know if IAP mode supported or not in relative boot. + */ +int32_t FMC_GetBootSource(void) +{ + int32_t ret = 0; + + if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk) + { + ret = 1; + } + + return ret; +} + +/** + * @brief Run CRC32 checksum calculation and get result. + * + * @param[in] u32addr Starting flash address. It must be a page aligned address. + * @param[in] u32count Byte count of flash to be calculated. It must be multiple of 2048bytes. + * + * @return Success or not. + * @retval 0 Success. + * @retval 0xFFFFFFFF Invalid parameter. + * + * @details Run ISP CRC32 checksum command to calculate checksum then get and return checksum data. + */ +uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count) +{ + uint32_t ret; + + if((u32addr % 2048UL) || (u32count % 2048UL)) + { + ret = 0xFFFFFFFF; + } + else + { + FMC->ISPCMD = FMC_ISPCMD_RUN_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = u32count; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + FMC->ISPCMD = FMC_ISPCMD_READ_CKS; + FMC->ISPADDR = u32addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + ret = FMC->ISPDAT; + } + + return ret; +} + +/** + * @brief Check the OTP is locked or not. + * + * @param[in] u32OtpNum The OTP number. + * + * @retval 1 OTP is locked. + * @retval 0 OTP is not locked. + * @retval -1 Failed to read OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @details To get specify OTP lock status + */ +int32_t FMC_Is_OTP_Locked(uint32_t u32OtpNum) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + if(FMC->ISPDAT != 0xFFFFFFFFUL) + { + ret = 1; /* Lock work was progrmmed. OTP was locked. */ + } + } + } + return ret; +} + +/** + * @brief Check the XOM is actived or not. + * + * @param[in] u32XomNum The xom number(0~3). + * + * @retval 1 XOM is actived. + * @retval 0 XOM is not actived. + * @retval -2 Invalid XOM number. + * + * @details To get specify XOMRn(n=0~3) active status + */ +int32_t FMC_GetXOMState(uint32_t u32XomNum) +{ + uint32_t u32act; + int32_t ret = 0; + + if(u32XomNum >= 4UL) + { + ret = -2; + } + + if(ret >= 0) + { + u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum; + ret = (int32_t)u32act; + } + return ret; +} + +/** + * @brief Lock the specified OTP. + * + * @param[in] u32OtpNum The OTP number. + * + * @retval 0 Success + * @retval -1 Failed to write OTP lock bits. + * @retval -2 Invalid OTP number. + * + * @details To lock specified OTP number + */ +int32_t FMC_Lock_OTP(uint32_t u32OtpNum) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL; + FMC->ISPDAT = 0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + return ret; +} + +/** + * @brief Enable FMC ISP function + * + * @param None + * + * @return None + * + * @details ISPEN bit of ISPCON must be set before we can use ISP commands. + * Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions. + * + * @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions. + * + */ +void FMC_Open(void) +{ + FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk; +} + + +/** + * @brief Read a word bytes from flash + * + * @param[in] u32Addr Address of the flash location to be read. + * It must be a word aligned address. + * + * @return The word data read from specified flash address. + * + * @details Execute FMC_ISPCMD_READ command to read a word from flash. + */ +uint32_t FMC_Read(uint32_t u32Addr) +{ + FMC->ISPCMD = FMC_ISPCMD_READ; + FMC->ISPADDR = u32Addr; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + return FMC->ISPDAT; +} + +/** + * @brief Read a double-word bytes from flash + * + * @param[in] u32addr Address of the flash location to be read. + * It must be a double-word aligned address. + * + * @param[out] u32data0 Place holder of word 0 read from flash address u32addr. + * @param[out] u32data1 Place holder of word 0 read from flash address u32addr+4. + * + * @return 0 Success + * @return -1 Failed + * + * @details Execute FMC_ISPCMD_READ_64 command to read a double-word from flash. + */ +int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = u32addr; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32data0 = FMC->MPDAT0; + *u32data1 = FMC->MPDAT1; + } + return ret; +} + +/** + * @brief Read data from OTP + * + * @param[in] u32OtpNum The OTP number(0~255). + * @param[in] u32LowWord Low word of the 64-bits data. + * @param[in] u32HighWord High word of the 64-bits data. + * + * @retval 0 Success + * @retval -1 Read failed. + * @retval -2 Invalid OTP number. + * + * @details Read the 64-bits data from the specified OTP. + */ +int32_t FMC_Read_OTP(uint32_t u32OtpNum, uint32_t *u32LowWord, uint32_t *u32HighWord) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_READ_64; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL ; + FMC->ISPDAT = 0x0UL; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {} + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + else + { + *u32LowWord = FMC->MPDAT0; + *u32HighWord = FMC->MPDAT1; + } + } + return ret; +} + +/** + * @brief Read the User Configuration words. + * + * @param[out] u32Config[] The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to be read. + * + * @return Success or not. + * @retval 0 Success + * @retval -1 Failed + * + * @details This function is used to read the settings of user configuration. + * if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config. + * if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned. + */ +int32_t FMC_ReadConfig(uint32_t u32Config[], uint32_t u32Count) +{ + uint32_t i; + + for(i = 0u; i < u32Count; i++) + { + u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4u); + } + return 0; +} + +/** + * @brief Set boot source from LDROM or APROM after next software reset + * + * @param[in] i32BootSrc + * 1: Boot from LDROM + * 0: Boot from APROM + * + * @return None + * + * @details This function is used to switch APROM boot or LDROM boot. User need to call + * FMC_SetBootSource to select boot source first, then use CPU reset or + * System Reset Request to reset system. + * + */ +void FMC_SetBootSource(int32_t i32BootSrc) +{ + if(i32BootSrc) + { + FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */ + } + else + { + FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */ + } +} + +/** + * @brief Execute Security Key Comparison. + * + * @param[in] key Key 0~2 to be compared. + * + * @retval 0 Key matched. + * @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count. + * @retval -2 Key mismatched. + * @retval -3 No KPROM key lock. Key comparison is not required. + * + * @ details Input a keys to compare with security key + */ +int32_t FMC_CompareSPKey(uint32_t key[3]) +{ + uint32_t u32KeySts; + int32_t ret = 0; + + if(FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) + { + /* FMC_SKey_Compare - FORBID! */ + ret = -1; + } + + if(!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* FMC_SKey_Compare - key is not locked! */ + ret = -3; + } + + if(ret == 0) + { + FMC->KPKEY0 = key[0]; + FMC->KPKEY1 = key[1]; + FMC->KPKEY2 = key[2]; + FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk; + + while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if(!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) + { + /* Key mismatched! */ + ret = -2; + } + else if(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) + { + /* Key matched, but still be locked! */ + ret = -2; + } + } + return ret; +} + +/** + * @brief Setup Security Key. + * + * @param[in] au32Key Key 0~2 to be setup. + * @param[in] u32Kpmax Maximum unmatched power-on counting number. + * @param[in] u32Kemax Maximum unmatched counting number. + * @param[in] i32LockCONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG. + * @param[in] i32LockSPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. (This param is not supported on M2351) + * + * @retval 0 Success. + * @retval -1 Key is locked. Cannot overwrite the current key. + * @retval -2 Failed to erase flash. + * @retval -3 Failed to program key. + * @retval -4 Key lock function failed. + * @retval -5 CONFIG lock function failed. + * @retval -6 SPROM lock function failed. (This status is not supported on M2351) + * @retval -7 KPMAX function failed. + * @retval -8 KEMAX function failed. + * + * @details Set secure keys and setup key compare count. The secure key also can protect user config. + */ +int32_t FMC_SetSPKey(uint32_t au32Key[3], uint32_t u32Kpmax, uint32_t u32Kemax, + const int32_t i32LockCONFIG, const int32_t i32LockSPROM) +{ + uint32_t lock_ctrl = 0UL; + uint32_t u32KeySts; + int32_t ret = 0; + + if(FMC->KPKEYSTS != 0x200UL) + { + ret = -1; + } + + if(FMC_Erase(FMC_KPROM_BASE)) + { + ret = -2; + } + + if(FMC_Erase(FMC_KPROM_BASE + 0x200UL)) + { + ret = -3; + } + + if(!i32LockCONFIG) + { + lock_ctrl |= 0x1UL; + } + + if(!i32LockSPROM) + { + lock_ctrl |= 0x2UL; + } + + if(ret == 0) + { + FMC_Write(FMC_KPROM_BASE, au32Key[0]); + FMC_Write(FMC_KPROM_BASE + 0x4UL, au32Key[1]); + FMC_Write(FMC_KPROM_BASE + 0x8UL, au32Key[2]); + FMC_Write(FMC_KPROM_BASE + 0xCUL, u32Kpmax); + FMC_Write(FMC_KPROM_BASE + 0x10UL, u32Kemax); + FMC_Write(FMC_KPROM_BASE + 0x14UL, lock_ctrl); + + while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } + + u32KeySts = FMC->KPKEYSTS; + + if(!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) + { + /* Security key lock failed! */ + ret = -4; + } + else if((i32LockCONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) || + ((!i32LockCONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) + { + /* CONFIG lock failed! */ + ret = -5; + } + else if(((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != u32Kpmax) + { + /* KPMAX failed! */ + ret = -7; + } + else if(((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != u32Kemax) + { + /* KEMAX failed! */ + ret = -8; + } + } + return ret; +} + +/** + * @brief Write a word bytes to flash. + * + * @param[in] u32Addr Address of the flash location to be programmed. + * It must be a word aligned address. + * @param[in] u32Data The word data to be programmed. + * + * @return None + * + * @ details Execute ISP FMC_ISPCMD_PROGRAM to program a word to flash. + */ +void FMC_Write(uint32_t u32Addr, uint32_t u32Data) +{ + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = u32Addr; + FMC->ISPDAT = u32Data; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } +} + +/** + * @brief Write a double-word bytes to flash + * + * @param[in] u32addr Address of the flash location to be programmed. + * It must be a double-word aligned address. + * @param[in] u32data0 The word data to be programmed to flash address u32addr. + * @param[in] u32data1 The word data to be programmed to flash address u32addr+4. + * + * @return 0 Success + * @return -1 Failed + * + * @ details Execute ISP FMC_ISPCMD_PROGRAM_64 to program a double-word to flash. + */ +int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1) +{ + int32_t ret = 0; + + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_64; + FMC->ISPADDR = u32addr; + FMC->MPDAT0 = u32data0; + FMC->MPDAT1 = u32data1; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + return ret; +} + +/** + * @brief Write User Configuration + * + * @param[in] au32Config[] The word buffer to store the User Configuration data. + * @param[in] u32Count The word count to program to User Configuration. + * + * @retval 0 Success + * @retval -1 Failed + * + * @details User must enable User Configuration update before writing it. + * User must erase User Configuration before writing it. + * User Configuration is also be page erase. User needs to backup necessary data + * before erase User Configuration. + */ +int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count) +{ + int32_t ret = 0; + uint32_t i; + + FMC_ENABLE_CFG_UPDATE(); + for(i = 0u; i < u32Count; i++) + { + FMC_Write(FMC_CONFIG_BASE + i * 4u, au32Config[i]); + if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != au32Config[i]) + { + ret = -1; + } + } + FMC_DISABLE_CFG_UPDATE(); + return ret; +} + +/** + * @brief Write Multi-Word bytes to flash + * + * @param[in] u32Addr Start flash address in APROM where the data chunk to be programmed into. + * This address must be 8-bytes aligned to flash address. + * @param[in] pu32Buf Buffer that carry the data chunk. + * @param[in] u32Len Length of the data chunk in bytes. + * + * @retval >=0 Number of data bytes were programmed. + * @return -1 Invalid address. + * + * @details Program Multi-Word data into specified address of flash. + */ + +int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) +{ + + uint32_t i, idx, u32OnProg; + int32_t err, retval = 0; + + if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) + { + return -1; + } + + idx = 0u; + FMC->ISPCMD = FMC_ISPCMD_PROGRAM_MUL; + FMC->ISPADDR = u32Addr; + retval += 16; + do + { + err = 0; + u32OnProg = 1u; + FMC->MPDAT0 = pu32Buf[idx + 0u]; + FMC->MPDAT1 = pu32Buf[idx + 1u]; + FMC->MPDAT2 = pu32Buf[idx + 2u]; + FMC->MPDAT3 = pu32Buf[idx + 3u]; + FMC->ISPTRG = 0x1u; + idx += 4u; + + for(i = idx; i < (u32Len / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/ + { + __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/ + do + { + if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while((FMC->MPSTS & (3u << FMC_MPSTS_D0_Pos)) && (err == 0)); + + if(err == 0) + { + retval += 8; + + /* Update new data for D0 */ + FMC->MPDAT0 = pu32Buf[i]; + FMC->MPDAT1 = pu32Buf[i + 1u]; + do + { + if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0u) + { + __set_PRIMASK(0u); + FMC->ISPADDR = FMC->MPADDR & (~0xful); + idx = (FMC->ISPADDR - u32Addr) / 4u; + err = -1; + } + } + while((FMC->MPSTS & (3u << FMC_MPSTS_D2_Pos)) && (err == 0)); + + if(err == 0) + { + retval += 8; + + /* Update new data for D2*/ + FMC->MPDAT2 = pu32Buf[i + 2u]; + FMC->MPDAT3 = pu32Buf[i + 3u]; + __set_PRIMASK(0u); + } + } + + if(err < 0) + { + break; + } + } + if(err == 0) + { + u32OnProg = 0u; + while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) {} + } + } + while(u32OnProg); + + return retval; +} + +/** + * @brief Write data to OTP + * + * @param[in] u32OtpNum The OTP number(0~255). + * @param[in] u32LowWord Low word of the 64-bits data. + * @param[in] u32HighWord High word of the 64-bits data. + * + * @retval 0 Success + * @retval -1 Program failed. + * @retval -2 Invalid OTP number. + * + * @details Program a 64-bits data to the specified OTP. + */ +int32_t FMC_Write_OTP(uint32_t u32OtpNum, uint32_t u32LowWord, uint32_t u32HighWord) +{ + int32_t ret = 0; + + if(u32OtpNum > 255UL) + { + ret = -2; + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL; + FMC->ISPDAT = u32LowWord; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + if(ret == 0) + { + FMC->ISPCMD = FMC_ISPCMD_PROGRAM; + FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL + 4UL; + FMC->ISPDAT = u32HighWord; + FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; + + while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } + + if(FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) + { + FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk; + ret = -1; + } + } + + return ret; +} + +/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group FMC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + + diff --git a/arch/riscv32/fe310/src/StdDriver/src/gpio.c b/arch/riscv32/fe310/src/StdDriver/src/gpio.c new file mode 100644 index 00000000..9f101aaf --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/gpio.c @@ -0,0 +1,191 @@ +/**************************************************************************//** + * @file gpio.c + * @version V3.00 + * @brief M2351 series General Purpose I/O (GPIO) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup GPIO_Driver GPIO Driver + @{ +*/ + +/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions + @{ +*/ + +/** + * @brief Set GPIO operation mode + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode Operation mode. It could be + * - \ref GPIO_MODE_INPUT + * - \ref GPIO_MODE_OUTPUT + * - \ref GPIO_MODE_OPEN_DRAIN + * - \ref GPIO_MODE_QUASI + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx)) + { + port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Enable GPIO interrupt + * + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be + * - \ref GPIO_INT_RISING + * - \ref GPIO_INT_FALLING + * - \ref GPIO_INT_BOTH_EDGE + * - \ref GPIO_INT_HIGH + * - \ref GPIO_INT_LOW + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); + + /* Enable interrupt function of specified pin */ + port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); +} + + +/** + * @brief Disable GPIO interrupt + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32Pin The pin of specified GPIO port. \n + * It could be 0 ~ 15 for PA, PB and PE. \n + * It could be 0 ~ 13 for PC GPIO port. \n + * It could be 0 ~ 14 for PD GPIO port. \n + * It could be 0 ~ 11 for PF GPIO port. \n + * It could be 2 ~ 4, 9 ~ 15 for PG GPIO port. \n + * It could be 4 ~ 11 for PH GPIO port. + * + * @return None + * + * @details This function is used to enable specified GPIO pin interrupt. + */ +void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin) +{ + /* Configure interrupt mode of specified pin */ + port->INTTYPE &= ~(1UL << u32Pin); + + /* Disable interrupt function of specified pin */ + port->INTEN &= ~((0x00010001UL) << u32Pin); +} + +/** + * @brief Set GPIO slew rate control + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode Slew rate mode. It could be + * - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V) + * - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V) + * - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V) + * + * @return None + * + * @details This function is used to set specified GPIO operation mode. + */ +void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/** + * @brief Set GPIO Pull-up and Pull-down control + * + + * @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF, PG or PH. + * @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n + * It could be BIT0 ~ BIT15 for PA, PB and PE. \n + * It could be BIT0 ~ BIT13 for PC. \n + * It could be BIT0 ~ BIT14 for PD. \n + * It could be BIT0 ~ BIT11 for PF. \n + * It could be BIT2 ~ BIT3, BIT9 ~ BIT15 for PG. \n + * It could be BIT4 ~ BIT11 for PH. + * @param[in] u32Mode The pin mode of specified GPIO pin. It could be + * - \ref GPIO_PUSEL_DISABLE + * - \ref GPIO_PUSEL_PULL_UP + * - \ref GPIO_PUSEL_PULL_DOWN + * + * @return None + * + * @details Set the pin mode of specified GPIO pin. + */ +void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) +{ + uint32_t u32Idx; + + for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++) + { + if(u32PinMask & (1ul << u32Idx)) + { + port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1)); + } + } +} + +/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group GPIO_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/i2c.c b/arch/riscv32/fe310/src/StdDriver/src/i2c.c new file mode 100644 index 00000000..1bbbb9e7 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/i2c.c @@ -0,0 +1,1463 @@ +/**************************************************************************//** + * @file i2c.c + * @version V3.00 + * $Revision: 2 $ + * $Date: 16/08/02 6:02p $ + * @brief M2351 series I2C Serial Interface Controller(I2C) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2C_Driver I2C Driver + @{ +*/ + + +/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions + @{ +*/ + +/** + * @brief Enable specify I2C Controller and set Clock Divider + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C bus clock in Hz + * + * @return Actual I2C bus clock frequency + * + * @details The function enable the specify I2C Controller and set proper Clock Divider + * in I2C CLOCK DIVIDED REGISTER (I2CLK) according to the target I2C Bus clock. + * I2C Bus clock = PCLK / (4*(divider+1). + * + */ +uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + /* Enable I2C */ + i2c->CTL0 |= I2C_CTL0_I2CEN_Msk; + + return (u32Pclk / ((u32Div + 1u) << 2u)); +} + +/** + * @brief Disable specify I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Reset I2C Controller and disable specify I2C port. + * + */ + +void I2C_Close(I2C_T *i2c) +{ + if(!(__PC() & NS_OFFSET)) + { + /* Reset I2C Controller */ + if(i2c == I2C0) + { + SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; + } + else if(i2c == I2C1) + { + SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk; + } + else if(i2c == I2C2) + { + SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk; + } + } + /* Disable I2C */ + i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; +} + +/** + * @brief Clear Time-out Counter flag + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details When Time-out flag will be set, use this function to clear I2C Bus Time-out counter flag . + * + */ +void I2C_ClearTimeoutFlag(I2C_T *i2c) +{ + i2c->TOCTL |= I2C_TOCTL_TOIF_Msk; +} + +/** + * @brief Set Control bit of I2C Controller + * + * @param[in] i2c Specify I2C port + * @param[in] u8Start Set I2C START condition + * @param[in] u8Stop Set I2C STOP condition + * @param[in] u8Si Clear SI flag + * @param[in] u8Ack Set I2C ACK bit + * + * @return None + * + * @details The function set I2C Control bit of I2C Bus protocol. + * + */ +void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack) +{ + uint32_t u32Reg = 0u; + + if(u8Start) + { + u32Reg |= I2C_CTL_STA; + } + if(u8Stop) + { + u32Reg |= I2C_CTL_STO; + } + if(u8Si) + { + u32Reg |= I2C_CTL_SI; + } + if(u8Ack) + { + u32Reg |= I2C_CTL_AA; + } + + i2c->CTL0 = (i2c->CTL0 & ~0x3Cu) | u32Reg; +} + +/** + * @brief Disable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for disable I2C interrupt + * + */ +void I2C_DisableInt(I2C_T *i2c) +{ + i2c->CTL0 &= ~I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Enable Interrupt of I2C Controller + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details The function is used for enable I2C interrupt + * + */ +void I2C_EnableInt(I2C_T *i2c) +{ + i2c->CTL0 |= I2C_CTL0_INTEN_Msk; +} + +/** + * @brief Get I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * + * @return The actual I2C Bus clock in Hz + * + * @details To get the actual I2C Bus Clock frequency. + */ +uint32_t I2C_GetBusClockFreq(I2C_T *i2c) +{ + uint32_t u32Divider = i2c->CLKDIV; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + return (u32Pclk / ((u32Divider + 1u) << 2u)); +} + +/** + * @brief Set I2C Bus Clock + * + * @param[in] i2c Specify I2C port + * @param[in] u32BusClock The target I2C Bus Clock in Hz + * + * @return The actual I2C Bus Clock in Hz + * + * @details To set the actual I2C Bus Clock frequency. + */ +uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock) +{ + uint32_t u32Div; + uint32_t u32Pclk; + + if((i2c == I2C1) || (i2c == I2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32Div = (uint32_t)(((u32Pclk * 10u) / (u32BusClock * 4u) + 5u) / 10u - 1u); /* Compute proper divider for I2C clock */ + i2c->CLKDIV = u32Div; + + return (u32Pclk / ((u32Div + 1u) << 2u)); +} + +/** + * @brief Get Interrupt Flag + * + * @param[in] i2c Specify I2C port + * + * @return I2C interrupt flag status + * + * @details To get I2C Bus interrupt flag. + */ +uint32_t I2C_GetIntFlag(I2C_T *i2c) +{ + return ((i2c->CTL0 & I2C_CTL0_SI_Msk) == I2C_CTL0_SI_Msk ? 1ul : 0ul); +} + +/** + * @brief Get I2C Bus Status Code + * + * @param[in] i2c Specify I2C port + * + * @return I2C Status Code + * + * @details To get I2C Bus Status Code. + */ +uint32_t I2C_GetStatus(I2C_T *i2c) +{ + return (i2c->STATUS0); +} + +/** + * @brief Read a Byte from I2C Bus + * + * @param[in] i2c Specify I2C port + * + * @return I2C Data + * + * @details To read a bytes data from specify I2C port. + */ +uint8_t I2C_GetData(I2C_T *i2c) +{ + return (uint8_t)(i2c->DAT); +} + +/** + * @brief Send a byte to I2C Bus + * + * @param[in] i2c Specify I2C port + * @param[in] u8Data The data to send to I2C bus + * + * @return None + * + * @details This function is used to write a byte to specified I2C port + */ +void I2C_SetData(I2C_T *i2c, uint8_t u8Data) +{ + i2c->DAT = u8Data; +} + +/** + * @brief Set 7-bit Slave Address and GC Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address register (0~3) + * @param[in] u8SlaveAddr 7-bit slave address + * @param[in] u8GCMode Enable/Disable GC mode (I2C_GCMODE_ENABLE / I2C_GCMODE_DISABLE) + * + * @return None + * + * @details This function is used to set 7-bit slave addresses in I2C SLAVE ADDRESS REGISTER (I2CADDR0~3) + * and enable GC Mode. + * + */ +void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDR1 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 2: + i2c->ADDR2 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 3: + i2c->ADDR3 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + case 0: + default: + i2c->ADDR0 = ((uint32_t)u8SlaveAddr << 1) | u8GCMode; + break; + } +} + +/** + * @brief Configure the mask bits of 7-bit Slave Address + * + * @param[in] i2c Specify I2C port + * @param[in] u8SlaveNo Set the number of I2C address mask register (0~3) + * @param[in] u8SlaveAddrMask A byte for slave address mask + * + * @return None + * + * @details This function is used to set 7-bit slave addresses. + * + */ +void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask) +{ + switch(u8SlaveNo) + { + case 1: + i2c->ADDRMSK1 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 2: + i2c->ADDRMSK2 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 3: + i2c->ADDRMSK3 = (uint32_t)u8SlaveAddrMask << 1; + break; + case 0: + default: + i2c->ADDRMSK0 = (uint32_t)u8SlaveAddrMask << 1; + break; + } +} + +/** + * @brief Enable Time-out Counter Function and support Long Time-out + * + * @param[in] i2c Specify I2C port + * @param[in] u8LongTimeout Configure DIV4 to enable Long Time-out (0/1) + * + * @return None + * + * @details This function enable Time-out Counter function and configure DIV4 to support Long + * Time-out. + * + */ +void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout) +{ + if(u8LongTimeout) + { + i2c->TOCTL |= I2C_TOCTL_TOCDIV4_Msk; + } + else + { + i2c->TOCTL &= ~I2C_TOCTL_TOCDIV4_Msk; + } + + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Disable Time-out Counter Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Time-out Counter function in I2CTOC register. + * + */ +void I2C_DisableTimeout(I2C_T *i2c) +{ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; +} + +/** + * @brief Enable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To enable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_EnableWakeup(I2C_T *i2c) +{ + i2c->WKCTL |= I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable I2C Wake-up Function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details To disable Wake-up function of I2C Wake-up control register. + * + */ +void I2C_DisableWakeup(I2C_T *i2c) +{ + i2c->WKCTL &= ~I2C_WKCTL_WKEN_Msk; +} + +/** + * @brief To get SMBus Status + * + * @param[in] i2c Specify I2C port + * + * @return SMBus status + * + * @details To get the Bus Management status of I2C_BUSSTS register + * + */ +uint32_t I2C_SMBusGetStatus(I2C_T *i2c) +{ + return (i2c->BUSSTS); +} + +/** + * @brief Clear SMBus Interrupt Flag + * + * @param[in] i2c Specify I2C port + * @param[in] u8SMBusIntFlag Specify SMBus interrupt flag + * + * @return None + * + * @details To clear flags of I2C_BUSSTS status register if interrupt set. + * + */ +void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8SMBusIntFlag) +{ + i2c->BUSSTS = u8SMBusIntFlag; +} + +/** + * @brief Set SMBus Bytes Counts of Transmission or Reception + * + * @param[in] i2c Specify I2C port + * @param[in] u32PktSize Transmit / Receive bytes + * + * @return None + * + * @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes. + * + */ +void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize) +{ + i2c->PKTSIZE = u32PktSize; +} + +/** + * @brief Init SMBus Host/Device Mode + * + * @param[in] i2c Specify I2C port + * @param[in] u8HostDevice Init SMBus port mode(I2C_SMBH_ENABLE(1)/I2C_SMBD_ENABLE(0)) + * + * @return None + * + * @details Using SMBus communication must specify the port is a Host or a Device. + * + */ +void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice) +{ + /* Clear BMHEN, BMDEN of BUSCTL Register */ + i2c->BUSCTL &= ~(I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BMDEN_Msk); + + /* Set SMBus Host/Device Mode, and enable Bus Management*/ + if(u8HostDevice == (uint8_t)I2C_SMBH_ENABLE) + { + i2c->BUSCTL |= (I2C_BUSCTL_BMHEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } + else + { + i2c->BUSCTL |= (I2C_BUSCTL_BMDEN_Msk | I2C_BUSCTL_BUSEN_Msk); + } +} + +/** + * @brief Disable SMBus function + * + * @param[in] i2c Specify I2C port + * + * @return None + * + * @details Disable all SMBus function include Bus disable, CRC check, Acknowledge by manual, Host/Device Mode. + * + */ +void I2C_SMBusClose(I2C_T *i2c) +{ + + i2c->BUSCTL = 0x00U; +} + +/** + * @brief Enable SMBus PEC Transmit Function + * + * @param[in] i2c Specify I2C port + * @param[in] u8PECTxEn CRC transmit enable(PECTX_ENABLE) or disable(PECTX_DISABLE) + * + * @return None + * + * @details When enable CRC check function, the Host or Device needs to transmit CRC byte. + * + */ +void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn) +{ + i2c->BUSCTL &= ~I2C_BUSCTL_PECTXEN_Msk; + + if(u8PECTxEn) + { + i2c->BUSCTL |= (I2C_BUSCTL_PECEN_Msk | I2C_BUSCTL_PECTXEN_Msk); + } + else + { + i2c->BUSCTL |= I2C_BUSCTL_PECEN_Msk; + } +} + +/** + * @brief Get SMBus CRC value + * + * @param[in] i2c Specify I2C port + * + * @return A byte is packet error check value + * + * @details The CRC check value after a transmission or a reception by count by using CRC8 + * + */ +uint8_t I2C_SMBusGetPECValue(I2C_T *i2c) +{ + return (uint8_t)i2c->PKTCRC; +} + +/** + * @brief Calculate Time-out of SMBus idle period + * + * @param[in] i2c Specify I2C port + * @param[in] u32Us Time-out length(us) + * @param[in] u32Hclk I2C peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Idle state. + * + */ + +void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk) +{ + uint32_t u32Div, u32HclkKHz; + + i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; + u32HclkKHz = u32Hclk / 1000U; + u32Div = (((u32Us * u32HclkKHz) / 1000U) >> 2U) - 1U; + if(u32Div > 255U) + { + i2c->BUSTOUT = 0xFFU; + } + else + { + i2c->BUSTOUT = u32Div; + } + +} + +/** + * @brief Calculate Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in active state. + * Time-out length is calculate the SCL line "one clock" pull low timing. + * + */ + +void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->BUSTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->BUSTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Calculate Cumulative Clock low Time-out of SMBus active period + * + * @param[in] i2c Specify I2C port + * @param[in] ms Time-out length(ms) + * @param[in] u32Pclk peripheral clock frequency + * + * @return None + * + * @details This function is used to set SMBus Time-out length when bus is in Active state. + * Time-out length is calculate the SCL line "clocks" low cumulative timing. + * + */ + +void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk) +{ + uint32_t u32Div, u32Pclk_kHz; + + i2c->BUSCTL &= ~I2C_BUSCTL_TIDLE_Msk; + + /* DIV4 disabled */ + i2c->TOCTL &= ~I2C_TOCTL_TOCEN_Msk; + u32Pclk_kHz = u32Pclk / 1000U; + u32Div = ((ms * u32Pclk_kHz) / (16U * 1024U)) - 1U; + if(u32Div <= 0xFFU) + { + i2c->CLKTOUT = u32Div; + } + else + { + /* DIV4 enabled */ + i2c->TOCTL |= I2C_TOCTL_TOCEN_Msk; + i2c->CLKTOUT = (((ms * u32Pclk_kHz) / (16U * 1024U * 4U)) - 1U) & 0xFFU; /* The max value is 255 */ + } +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master write a byte data to Slave. + * + */ + +uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + + I2C_START(i2c); + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8Data); /* Write data to I2CDAT */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *au8Data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master write multi bytes data to Slave. + * + */ + +uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write Data to I2CDAT */ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] u8Data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Send Slave address with write bit */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < 1u) + { + I2C_SET_DATA(i2c, u8Data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *au8Data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u32txLen < u32wLen) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] u8Data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < 1u) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, u8Data); + u32txLen++; + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] au8Data[] A data array for write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32txLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else if((u32txLen < u32wLen) && (u8Addr == 0u)) + { + I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write data to Register I2CDAT*/ + } + else + { + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + } + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master to read a byte data from Slave. + * + */ +uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + rdata = 0u; /* If occurs error, return 0 */ + } + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + u8Rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + u8Rdata = 0u; /* If occurs error, return 0 */ + } + return u8Rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, u8DataAddr); /* Write Lo byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ + break; + case 0x10u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify an address(2 bytes) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x58u: + u8Rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + if(u8Err) + { + u8Rdata = 0u; /* If occurs error, return 0 */ + } + return u8Rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *i2c Point to I2C peripheral + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] au8Rdata[] A data array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen) +{ + uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; + uint32_t u32rxLen = 0u; + + I2C_START(i2c); /* Send START */ + while(u8Xfering && (u8Err == 0u)) + { + I2C_WAIT_READY(i2c) {} + switch(I2C_GET_STATUS(i2c)) + { + case 0x08u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x18u: /* Slave Address ACK */ + I2C_SET_DATA(i2c, (uint8_t)((u16DataAddr & 0xFF00u) >> 8u)); /* Write Hi byte address of register */ + break; + case 0x20u: /* Slave Address NACK */ + case 0x30u: /* Master transmit data NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x28u: + if(u8Addr) + { + I2C_SET_DATA(i2c, (uint8_t)(u16DataAddr & 0xFFu)); /* Write Lo byte address of register */ + u8Addr = 0u; + } + else + { + u8Ctrl = I2C_CTL_STA_SI; /* Clear SI and send repeat START */ + } + break; + case 0x10u: + I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + break; + case 0x40u: /* Slave Address ACK */ + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + break; + case 0x48u: /* Slave Address NACK */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + case 0x50u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + if(u32rxLen < (u32rLen - 1u)) + { + u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ + } + else + { + u8Ctrl = I2C_CTL_SI; /* Clear SI */ + } + break; + case 0x58u: + au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Xfering = 0u; + break; + case 0x38u: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ + u8Err = 1u; + break; + } + I2C_SET_CONTROL_REG(i2c, u8Ctrl); /* Write controlbit to I2C_CTL register */ + } + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/i2s.c b/arch/riscv32/fe310/src/StdDriver/src/i2s.c new file mode 100644 index 00000000..7d312929 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/i2s.c @@ -0,0 +1,266 @@ +/**************************************************************************//** + * @file i2s.c + * @version V3.00 + * @brief M2351 series I2S driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup I2S_Driver I2S Driver + @{ +*/ + +/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions + @{ +*/ + +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s); + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The base address of I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of I2S0_SEL (CLK_CLKSEL3[17:16]). + */ +static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s) +{ + (void)i2s; + uint32_t u32Freq, u32ClkSrcSel; + + u32ClkSrcSel = CLK_GetModuleClockSource(I2S0_MODULE) << CLK_CLKSEL3_I2S0SEL_Pos; + + switch(u32ClkSrcSel) + { + case CLK_CLKSEL3_I2S0SEL_HXT: + u32Freq = __HXT; + break; + + case CLK_CLKSEL3_I2S0SEL_PLL: + u32Freq = CLK_GetPLLClockFreq(); + break; + + case CLK_CLKSEL3_I2S0SEL_HIRC: + u32Freq = __HIRC; + break; + + case CLK_CLKSEL3_I2S0SEL_PCLK0: + u32Freq = CLK_GetPCLK0Freq(); + break; + + default: + u32Freq = __HXT; + break; + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The base address of I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are: + * - \ref I2S_MODE_MASTER + * - \ref I2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are: + * - \ref I2S_DATABIT_8 + * - \ref I2S_DATABIT_16 + * - \ref I2S_DATABIT_24 + * - \ref I2S_DATABIT_32 + * @param[in] u32MonoData: Set audio data to mono or not. Valid values are: + * - \ref I2S_ENABLE_MONO + * - \ref I2S_DISABLE_MONO + * @param[in] u32DataFormat Data format. This is also used to select I2S or PCM(TDM) function. Valid values are: + * - \ref I2S_FORMAT_I2S + * - \ref I2S_FORMAT_I2S_MSB + * - \ref I2S_FORMAT_I2S_LSB + * - \ref I2S_FORMAT_PCM + * - \ref I2S_FORMAT_PCM_MSB + * - \ref I2S_FORMAT_PCM_LSB + * @return Real sample rate. + * @details Set TX and RX FIFO threshold to middle value. + * The sample rate may not be used from the parameter, it depends on system's clock settings, + * but real sample rate used by system will be returned for reference. + * @note I2S will be reset in initialization only for Secure. + */ +uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32MonoData, uint32_t u32DataFormat) +{ + uint16_t u16Divider; + uint32_t u32BitRate, u32SrcClk; + + if(!(__PC() & NS_OFFSET)) + { + /* Reset I2S */ + SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk; + } + + /* Configure I2S controller according to input parameters. */ + i2s->CTL0 = u32MasterSlave | u32WordWidth | u32MonoData | u32DataFormat; + i2s->CTL1 = I2S_FIFO_TX_LEVEL_WORD_8 | I2S_FIFO_RX_LEVEL_WORD_8; + + /* Get I2S source clock frequency */ + u32SrcClk = I2S_GetSourceClockFreq(i2s); + + /* Calculate bit clock rate */ + u32BitRate = u32SampleRate * (((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL; + u16Divider = (uint16_t)((((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL); /* Round to the nearest integer */ + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | ((uint32_t)u16Divider << 8UL); + + /* Calculate real sample rate */ + u32BitRate = u32SrcClk / (((uint32_t)u16Divider + 1UL) * 2UL); + u32SampleRate = u32BitRate / ((((u32WordWidth >> 4UL) & 0x3UL) + 1UL) * 16UL); + + /* Enable I2S controller */ + i2s->CTL0 |= I2S_CTL0_I2SEN_Msk; + + return u32SampleRate; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The base address of I2S module. + * @return None + * @details Clear I2SEN (I2S_CTL0[0]) to disable I2S function. + */ +void I2S_Close(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The base address of I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function enables the interrupt according to the mask parameter. + */ +void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN |= u32Mask; +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The base address of I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * @return None + * @details This function disables the interrupt according to the mask parameter. + */ +void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask) +{ + i2s->IEN &= ~u32Mask; +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The base address of I2S module. + * @param[in] u32BusClock The target MCLK clock. + * @return Actual MCLK clock + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock) +{ + uint8_t u8Divider; + uint32_t u32SrcClk, u32Reg, u32Clock; + + u32SrcClk = I2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u8Divider = (uint8_t)0UL; + } + else + { + u8Divider = (uint8_t)(u32SrcClk / u32BusClock) >> 1UL; + } + + i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider; + + i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk; + + u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk; + + if(u32Reg == 0UL) + { + u32Clock = u32SrcClk; + } + else + { + u32Clock = ((u32SrcClk >> 1UL) / u32Reg); + } + + return u32Clock; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The base address of I2S module. + * @return None + * @details Disable master clock output. + */ +void I2S_DisableMCLK(I2S_T *i2s) +{ + i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 15. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 15. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) | + (u32TxThreshold << I2S_CTL1_TXTH_Pos) | + (u32RxThreshold << I2S_CTL1_RXTH_Pos); +} + +/** + * @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32ChannelWidth Channel width. Valid values are: + * - \ref I2S_TDM_WIDTH_8BIT + * - \ref I2S_TDM_WIDTH_16BIT + * - \ref I2S_TDM_WIDTH_24BIT + * - \ref I2S_TDM_WIDTH_32BIT + * @param[in] u32ChannelNum Channel number. Valid values are: + * - \ref I2S_TDM_2CH + * - \ref I2S_TDM_4CH + * - \ref I2S_TDM_6CH + * - \ref I2S_TDM_8CH + * @param[in] u32SyncWidth Width for sync pulse. Valid values are: + * - \ref I2S_TDM_SYNC_ONE_BCLK + * - \ref I2S_TDM_SYNC_ONE_CHANNEL + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth) +{ + i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) | + (u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) | + (u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) | + (u32SyncWidth << I2S_CTL0_PCMSYNC_Pos); +} + +/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group I2S_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/libmkrom.a b/arch/riscv32/fe310/src/StdDriver/src/libmkrom.a new file mode 100644 index 00000000..de0d55a5 Binary files /dev/null and b/arch/riscv32/fe310/src/StdDriver/src/libmkrom.a differ diff --git a/arch/riscv32/fe310/src/StdDriver/src/pdma.c b/arch/riscv32/fe310/src/StdDriver/src/pdma.c new file mode 100644 index 00000000..7bf18038 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/pdma.c @@ -0,0 +1,436 @@ +/**************************************************************************//** + * @file pdma.c + * @version V3.00 + * @brief M2351 series PDMA driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +static uint8_t au8ChSelect[PDMA_CH_MAX]; + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup PDMA_Driver PDMA Driver + @{ +*/ + + +/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions + @{ +*/ + +/** + * @brief PDMA Open + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable the PDMA channels. + */ +void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask) +{ + uint32_t i; + + for(i = 0UL; i < (int)PDMA_CH_MAX; i++) + { + if((1 << i) & u32Mask) + { + (pdma)->DSCT[i].CTL = 0UL; + au8ChSelect[i] = (uint8_t)PDMA_MEM; + } + } + + (pdma)->CHCTL |= u32Mask; +} + +/** + * @brief PDMA Close + * + * @param[in] pdma The pointer of the specified PDMA module + * + * @return None + * + * @details This function disable all PDMA channels. + */ +void PDMA_Close(PDMA_T *pdma) +{ + (pdma)->CHCTL = 0UL; +} + +/** + * @brief Set PDMA Transfer Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Width Data width. Valid values are + * - \ref PDMA_WIDTH_8 + * - \ref PDMA_WIDTH_16 + * - \ref PDMA_WIDTH_32 + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected channel data width and transfer count. + */ +void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos)); +} + +/** + * @brief Set PDMA Stride Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32DestLen Destination stride count + * @param[in] u32SrcLen Source stride count + * @param[in] u32TransCount Transfer count + * + * @return None + * + * @details This function set the selected stride mode. + */ +void PDMA_SetStride(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32DestLen, uint32_t u32SrcLen, uint32_t u32TransCount) +{ + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_STRIDEEN_Msk; + (pdma)->STRIDE[u32Ch].ASOCR = (u32DestLen << 16) | u32SrcLen; + (pdma)->STRIDE[u32Ch].STCR = u32TransCount; +} + +/** + * @brief Set PDMA Transfer Address + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32SrcAddr Source address + * @param[in] u32SrcCtrl Source control attribute. Valid values are + * - \ref PDMA_SAR_INC + * - \ref PDMA_SAR_FIX + * @param[in] u32DstAddr destination address + * @param[in] u32DstCtrl destination control attribute. Valid values are + * - \ref PDMA_DAR_INC + * - \ref PDMA_DAR_FIX + * + * @return None + * + * @details This function set the selected channel source/destination address and attribute. + */ +void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl) +{ + (pdma)->DSCT[u32Ch].SA = u32SrcAddr; + (pdma)->DSCT[u32Ch].DA = u32DstAddr; + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl); +} + +/** + * @brief Set PDMA Transfer Mode + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Peripheral The selected peripheral. Valid values are + * - \ref PDMA_MEM + * - \ref PDMA_USB_TX + * - \ref PDMA_USB_RX + * - \ref PDMA_UART0_TX + * - \ref PDMA_UART0_RX + * - \ref PDMA_UART1_TX + * - \ref PDMA_UART1_RX + * - \ref PDMA_UART2_TX + * - \ref PDMA_UART2_RX + * - \ref PDMA_UART3_TX + * - \ref PDMA_UART3_RX + * - \ref PDMA_UART4_TX + * - \ref PDMA_UART4_RX + * - \ref PDMA_UART5_TX + * - \ref PDMA_UART5_RX + * - \ref PDMA_USCI0_TX + * - \ref PDMA_USCI0_RX + * - \ref PDMA_USCI1_TX + * - \ref PDMA_USCI1_RX + * - \ref PDMA_QSPI0_TX + * - \ref PDMA_QSPI0_RX + * - \ref PDMA_SPI0_TX + * - \ref PDMA_SPI0_RX + * - \ref PDMA_SPI1_TX + * - \ref PDMA_SPI1_RX + * - \ref PDMA_SPI2_TX + * - \ref PDMA_SPI2_RX + * - \ref PDMA_SPI3_TX + * - \ref PDMA_SPI3_RX + * - \ref PDMA_EPWM0_P1_RX + * - \ref PDMA_EPWM0_P2_RX + * - \ref PDMA_EPWM0_P3_RX + * - \ref PDMA_EPWM1_P1_RX + * - \ref PDMA_EPWM1_P2_RX + * - \ref PDMA_EPWM1_P3_RX + * - \ref PDMA_I2C0_TX + * - \ref PDMA_I2C0_RX + * - \ref PDMA_I2C1_TX + * - \ref PDMA_I2C1_RX + * - \ref PDMA_I2C2_TX + * - \ref PDMA_I2C2_RX + * - \ref PDMA_I2S0_TX + * - \ref PDMA_I2S0_RX + * - \ref PDMA_TMR0 + * - \ref PDMA_TMR1 + * - \ref PDMA_TMR2 + * - \ref PDMA_TMR3 + * - \ref PDMA_ADC_RX + * - \ref PDMA_DAC0_TX + * - \ref PDMA_DAC1_TX + * @param[in] u32ScatterEn Scatter-gather mode enable + * @param[in] u32DescAddr Scatter-gather descriptor address + * + * @return None + * + * @details This function set the selected channel transfer mode. Include peripheral setting. + */ +void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr) +{ + au8ChSelect[u32Ch] = (uint8_t)u32Peripheral; + switch(u32Ch) + { + case 0UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral; + break; + case 1UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos); + break; + case 2UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos); + break; + case 3UL: + (pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos); + break; + case 4UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral; + break; + case 5UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos); + break; + case 6UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos); + break; + case 7UL: + (pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos); + break; + default: + break; + } + + if(u32ScatterEn) + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER; + (pdma)->DSCT[u32Ch].NEXT = u32DescAddr - ((pdma)->SCATBA); + } + else + { + (pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC; + } +} + +/** + * @brief Set PDMA Burst Type and Size + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32BurstType Burst mode or single mode. Valid values are + * - \ref PDMA_REQ_SINGLE + * - \ref PDMA_REQ_BURST + * @param[in] u32BurstSize Set the size of burst mode. Valid values are + * - \ref PDMA_BURST_128 + * - \ref PDMA_BURST_64 + * - \ref PDMA_BURST_32 + * - \ref PDMA_BURST_16 + * - \ref PDMA_BURST_8 + * - \ref PDMA_BURST_4 + * - \ref PDMA_BURST_2 + * - \ref PDMA_BURST_1 + * + * @return None + * + * @details This function set the selected channel burst type and size. + */ +void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize) +{ + (pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk); + (pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize); +} + +/** + * @brief Enable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function enable timeout function of the selected channel(s). + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + (pdma)->TOUTEN |= u32Mask; +} + +/** + * @brief Disable timeout function + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Mask Channel enable bits. + * + * @return None + * + * @details This function disable timeout function of the selected channel(s). + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask) +{ + (pdma)->TOUTEN &= ~u32Mask; +} + +/** + * @brief Set PDMA Timeout Count + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32OnOff Enable/disable timeout function + * @param[in] u32TimeOutCnt Timeout count + * + * @return None + * + * @details This function set the timeout count. + * @note This function is only supported in channel 0 and channel 1. + */ +void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt) +{ + switch(u32Ch) + { + case 0UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt; + break; + case 1UL: + (pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos); + break; + + default: + break; + } + if(u32OnOff) + { + (pdma)->TOUTEN |= (1UL << u32Ch); + } + else + { + (pdma)->TOUTEN &= ~(1UL << u32Ch); + } +} + +/** + * @brief Trigger PDMA + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * + * @return None + * + * @details This function trigger the selected channel. + */ +void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch) +{ + if(au8ChSelect[u32Ch] == PDMA_MEM) + { + (pdma)->SWREQ = (1UL << u32Ch); + } +} + +/** + * @brief Enable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TABLE + * - \ref PDMA_INT_TIMEOUT + * - \ref PDMA_INT_ALIGN + * + * @return None + * + * @details This function enable the selected channel interrupt. + * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1. + */ +void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + case PDMA_INT_ALIGN: + (pdma)->INTEN |= (1UL << u32Ch); + break; + case PDMA_INT_TABLE: + (pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN |= (1UL << u32Ch); + break; + + default: + break; + } +} + +/** + * @brief Disable Interrupt + * + * @param[in] pdma The pointer of the specified PDMA module + * @param[in] u32Ch The selected channel + * @param[in] u32Mask The Interrupt Type. Valid values are + * - \ref PDMA_INT_TRANS_DONE + * - \ref PDMA_INT_TABLE + * - \ref PDMA_INT_TIMEOUT + * - \ref PDMA_INT_ALIGN + * + * @return None + * + * @details This function disable the selected channel interrupt. + * @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1. + * @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY). + */ +void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask) +{ + switch(u32Mask) + { + case PDMA_INT_TRANS_DONE: + case PDMA_INT_ALIGN: + (pdma)->INTEN &= ~(1UL << u32Ch); + break; + case PDMA_INT_TABLE: + (pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk; + break; + case PDMA_INT_TIMEOUT: + (pdma)->TOUTIEN &= ~(1UL << u32Ch); + break; + + default: + break; + } +} + +/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group PDMA_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/qei.c b/arch/riscv32/fe310/src/StdDriver/src/qei.c new file mode 100644 index 00000000..f8c0f2f4 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/qei.c @@ -0,0 +1,147 @@ +/**************************************************************************//** + * @file qei.c + * @version V3.00 + * $Revision: 2 $ + * $Date: 17/09/20 9:33a $ + * @brief Quadrature Encoder Interface (QEI) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "M2351.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QEI_Driver QEI Driver + @{ +*/ + +/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions + @{ +*/ + +/** + * @brief Close QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function reset QEI configuration and stop QEI counting. + */ +void QEI_Close(QEI_T* qei) +{ + /* Reset QEI configuration */ + qei->CTL = 0UL; +} + +/** + * @brief Disable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function disable QEI specified interrupt. + */ +void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Disable QEI specified interrupt */ + QEI_DISABLE_INT(qei, u32IntSel); + + /* Disable NVIC QEI IRQ */ + if((qei == QEI0) || (qei == QEI0_NS)) + { + NVIC_DisableIRQ(QEI0_IRQn); + } + else + { + NVIC_DisableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Enable QEI interrupt + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32IntSel Interrupt type selection. + * - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt + * - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt + * - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt + * - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt + * @return None + * @details This function enable QEI specified interrupt. + */ +void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel) +{ + /* Enable QEI specified interrupt */ + QEI_ENABLE_INT(qei, u32IntSel); + + /* Enable NVIC QEI IRQ */ + if((qei == QEI0) || (qei == QEI0_NS)) + { + NVIC_EnableIRQ(QEI0_IRQn); + } + else + { + NVIC_EnableIRQ(QEI1_IRQn); + } +} + +/** + * @brief Open QEI in specified mode and enable input + * @param[in] qei The pointer of the specified QEI module. + * @param[in] u32Mode QEI counting mode. + * - \ref QEI_CTL_X4_FREE_COUNTING_MODE + * - \ref QEI_CTL_X2_FREE_COUNTING_MODE + * - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE + * - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE + * @param[in] u32Value The counter maximum value in compare-counting mode. + * @return None + * @details This function set QEI in specified mode and enable input. + */ +void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value) +{ + /* Set QEI function configuration */ + /* Set QEI counting mode */ + /* Enable IDX, QEA and QEB input to QEI controller */ + qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk); + + /* Set QEI maximum count value in in compare-counting mode */ + qei->CNTMAX = u32Value; +} + +/** + * @brief Start QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function enable QEI function and start QEI counting. + */ +void QEI_Start(QEI_T* qei) +{ + /* Enable QEI controller function */ + qei->CTL |= QEI_CTL_QEIEN_Msk; +} + +/** + * @brief Stop QEI function + * @param[in] qei The pointer of the specified QEI module. + * @return None + * @details This function disable QEI function and stop QEI counting. + */ +void QEI_Stop(QEI_T* qei) +{ + /* Disable QEI controller function */ + qei->CTL &= (~QEI_CTL_QEIEN_Msk); +} + + +/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QEI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/qspi.c b/arch/riscv32/fe310/src/StdDriver/src/qspi.c new file mode 100644 index 00000000..e1689da7 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/qspi.c @@ -0,0 +1,832 @@ +/**************************************************************************//** + * @file qspi.c + * @version V3.00 + * @brief M2351 series QSPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup QSPI_Driver QSPI Driver + @{ +*/ + + +/** @addtogroup QSPI_EXPORTED_FUNCTIONS QSPI Exported Functions + @{ +*/ + +/** + * @brief This function make QSPI module be ready to transfer. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32MasterSlave Decides the QSPI module is operating in master mode or in slave mode. (QSPI_SLAVE, QSPI_MASTER) + * @param[in] u32QSPIMode Decides the transfer timing. (QSPI_MODE_0, QSPI_MODE_1, QSPI_MODE_2, QSPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a QSPI transaction. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI peripheral clock. + * @details By default, the QSPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the QSPI clock divider setting will be 0. + * The actual clock rate may be different from the target QSPI clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the + * actual QSPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode for Secure, the QSPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the QSPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t QSPI_Open(QSPI_T *qspi, + uint32_t u32MasterSlave, + uint32_t u32QSPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32RetValue = 0UL; + + if(u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + + if(u32MasterSlave == QSPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + } + } + + /* Check clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the QSPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + qspi->SSCTL = QSPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + qspi->CTL = u32MasterSlave | (u32DataWidth << QSPI_CTL_DWIDTH_Pos) | (u32QSPIMode) | QSPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + } + else + { + /* Check clock source of QSPI */ + if((qspi == QSPI0) || (qspi == QSPI0_NS)) + { + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + } + } + + return u32RetValue; +} + +/** + * @brief Disable QSPI controller. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details Clear SPIEN bit of QSPI_CTL register to disable QSPI transfer control. + */ +void QSPI_Close(QSPI_T *qspi) +{ + qspi->CTL &= ~QSPI_CTL_SPIEN_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI RX FIFO buffer. The RXEMPTY (QSPI_STATUS[8]) will be set to 1. + */ +void QSPI_ClearRxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will clear QSPI TX FIFO buffer. The TXEMPTY (QSPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void QSPI_ClearTxFIFO(QSPI_T *qspi) +{ + qspi->FIFOCTL |= QSPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void QSPI_DisableAutoSS(QSPI_T *qspi) +{ + qspi->SSCTL &= ~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (QSPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (QSPI_SS_ACTIVE_HIGH, QSPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void QSPI_EnableAutoSS(QSPI_T *qspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + qspi->SSCTL = (qspi->SSCTL & (~(QSPI_SSCTL_AUTOSS_Msk | QSPI_SSCTL_SSACTPOL_Msk | QSPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | QSPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the QSPI bus clock. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32BusClock The expected frequency of QSPI bus clock in Hz. + * @return Actual frequency of QSPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target QSPI bus clock rate. + * For example, if the QSPI source clock rate is 12 MHz and the target QSPI bus clock rate is 7 MHz, the actual QSPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, QSPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * QSPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= QSPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t QSPI_SetBusClock(QSPI_T *qspi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Check if valid QSPI exist */ + if(!((qspi == QSPI0) || (qspi == QSPI0_NS))) + { + return 0ul; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of QSPI */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_QSPI0SEL_Msk)) | CLK_CLKSEL2_QSPI0SEL_PCLK0; + } + } + + /* Check clock source of QSPI */ + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + qspi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + qspi->CLKDIV |= QSPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + qspi->CLKDIV = (qspi->CLKDIV & (~QSPI_CLKDIV_DIVIDER_Msk)) | (u32Div << QSPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void QSPI_SetFIFO(QSPI_T *qspi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + qspi->FIFOCTL = (qspi->FIFOCTL & ~(QSPI_FIFOCTL_TXTH_Msk | QSPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << QSPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << QSPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of QSPI bus clock. Only available in Master mode. + * @param[in] qspi The pointer of the specified QSPI module. + * @return Actual QSPI bus clock frequency in Hz. + * @details This function will calculate the actual QSPI bus clock rate according to the QQSPISEL/QSPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t QSPI_GetBusClock(QSPI_T *qspi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Check if valid QSPI exist */ + if(!((qspi == QSPI0) || (qspi == QSPI0_NS))) + { + return 0ul; + } + + /* Get DIVIDER setting */ + u32Div = (qspi->CLKDIV & QSPI_CLKDIV_DIVIDER_Msk) >> QSPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of QSPI */ + if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(QSPI0_MODULE) << CLK_CLKSEL2_QSPI0SEL_Pos) == CLK_CLKSEL2_QSPI0SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + + /* Return QSPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_EnableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL |= QSPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL |= QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL |= QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable QSPI related interrupts specified by u32Mask parameter. + */ +void QSPI_DisableInt(QSPI_T *qspi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) == QSPI_UNIT_INT_MASK) + { + qspi->CTL &= ~QSPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) == QSPI_SSACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) == QSPI_SSINACT_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) == QSPI_SLVUR_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) == QSPI_SLVBE_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) == QSPI_SLVTO_INT_MASK) + { + qspi->SSCTL &= ~QSPI_SSCTL_SLVTOIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) == QSPI_TXUF_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) == QSPI_FIFO_TXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) == QSPI_FIFO_RXTH_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) == QSPI_FIFO_RXOV_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) == QSPI_FIFO_RXTO_INT_MASK) + { + qspi->FIFOCTL &= ~QSPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_TXTH_INT_MASK + * - \ref QSPI_FIFO_RXTH_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get QSPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t QSPI_GetIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32IntStatus; + uint32_t u32IntFlag = 0UL; + + u32IntStatus = qspi->STATUS; + + /* Check unit transfer interrupt flag */ + if((u32Mask & QSPI_UNIT_INT_MASK) && (u32IntStatus & QSPI_STATUS_UNITIF_Msk)) + { + u32IntFlag |= QSPI_UNIT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & QSPI_SSACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSACTIF_Msk)) + { + u32IntFlag |= QSPI_SSACT_INT_MASK; + } + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & QSPI_SSINACT_INT_MASK) && (u32IntStatus & QSPI_STATUS_SSINAIF_Msk)) + { + u32IntFlag |= QSPI_SSINACT_INT_MASK; + } + + /* Check slave TX under run interrupt flag */ + if((u32Mask & QSPI_SLVUR_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVURIF_Msk)) + { + u32IntFlag |= QSPI_SLVUR_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & QSPI_SLVBE_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVBEIF_Msk)) + { + u32IntFlag |= QSPI_SLVBE_INT_MASK; + } + + /* Check slave mode time-out interrupt flag */ + if((u32Mask & QSPI_SLVTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_SLVTOIF_Msk)) + { + u32IntFlag |= QSPI_SLVTO_INT_MASK; + } + + /* Check slave TX underflow interrupt flag */ + if((u32Mask & QSPI_TXUF_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXUFIF_Msk)) + { + u32IntFlag |= QSPI_TXUF_INT_MASK; + } + + /* Check TX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_TXTHIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_TXTH_INT_MASK; + } + + /* Check RX threshold interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTHIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXTH_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & QSPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXOVIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXOV_INT_MASK; + } + + /* Check RX time-out interrupt flag */ + if((u32Mask & QSPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & QSPI_STATUS_RXTOIF_Msk)) + { + u32IntFlag |= QSPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref QSPI_UNIT_INT_MASK + * - \ref QSPI_SSACT_INT_MASK + * - \ref QSPI_SSINACT_INT_MASK + * - \ref QSPI_SLVUR_INT_MASK + * - \ref QSPI_SLVBE_INT_MASK + * - \ref QSPI_SLVTO_INT_MASK + * - \ref QSPI_TXUF_INT_MASK + * - \ref QSPI_FIFO_RXOV_INT_MASK + * - \ref QSPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear QSPI related interrupt flags specified by u32Mask parameter. + */ +void QSPI_ClearIntFlag(QSPI_T *qspi, uint32_t u32Mask) +{ + if(u32Mask & QSPI_UNIT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & QSPI_SSACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & QSPI_SSINACT_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & QSPI_SLVUR_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & QSPI_SLVBE_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & QSPI_SLVTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_SLVTOIF_Msk; /* Clear slave mode time-out interrupt flag */ + } + + if(u32Mask & QSPI_TXUF_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXOV_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & QSPI_FIFO_RXTO_INT_MASK) + { + qspi->STATUS = QSPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get QSPI status. + * @param[in] qspi The pointer of the specified QSPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref QSPI_BUSY_MASK + * - \ref QSPI_RX_EMPTY_MASK + * - \ref QSPI_RX_FULL_MASK + * - \ref QSPI_TX_EMPTY_MASK + * - \ref QSPI_TX_FULL_MASK + * - \ref QSPI_TXRX_RESET_MASK + * - \ref QSPI_SPIEN_STS_MASK + * - \ref QSPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get QSPI related status specified by u32Mask parameter. + */ +uint32_t QSPI_GetStatus(QSPI_T *qspi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Flag = 0UL; + + u32TmpStatus = qspi->STATUS; + + /* Check busy status */ + if((u32Mask & QSPI_BUSY_MASK) && (u32TmpStatus & QSPI_STATUS_BUSY_Msk)) + { + u32Flag |= QSPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & QSPI_RX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_RXEMPTY_Msk)) + { + u32Flag |= QSPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & QSPI_RX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_RXFULL_Msk)) + { + u32Flag |= QSPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & QSPI_TX_EMPTY_MASK) && (u32TmpStatus & QSPI_STATUS_TXEMPTY_Msk)) + { + u32Flag |= QSPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & QSPI_TX_FULL_MASK) && (u32TmpStatus & QSPI_STATUS_TXFULL_Msk)) + { + u32Flag |= QSPI_TX_FULL_MASK; + } + + /* Check TX/RX reset flag */ + if((u32Mask & QSPI_TXRX_RESET_MASK) && (u32TmpStatus & QSPI_STATUS_TXRXRST_Msk)) + { + u32Flag |= QSPI_TXRX_RESET_MASK; + } + + /* Check SPIEN flag */ + if((u32Mask & QSPI_SPIEN_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SPIENSTS_Msk)) + { + u32Flag |= QSPI_SPIEN_STS_MASK; + } + + /* Check QSPIx_SS line status */ + if((u32Mask & QSPI_SSLINE_STS_MASK) && (u32TmpStatus & QSPI_STATUS_SSLINE_Msk)) + { + u32Flag |= QSPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/*@}*/ /* end of group QSPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group QSPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/retarget.c b/arch/riscv32/fe310/src/StdDriver/src/retarget.c new file mode 100644 index 00000000..d4bb9921 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/retarget.c @@ -0,0 +1,884 @@ +/**************************************************************************//** + * @file retarget.c + * @version V3.00 + * @brief Debug Port and Semihost Setting Source File + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + * + ******************************************************************************/ + + +#include +#include "NuMicro.h" + +#if defined (__ICCARM__) +# pragma diag_suppress=Pm150 +#endif + + +#if defined ( __CC_ARM ) +#if (__ARMCC_VERSION < 400000) +#else +/* Insist on keeping widthprec, to avoid X propagation by benign code in C-lib */ +#pragma import _printf_widthprec +#endif +#endif + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global variables */ +/*---------------------------------------------------------------------------------------------------------*/ +#if !(defined(__ICCARM__) && (__VER__ >= 6010000)) +# if (__ARMCC_VERSION < 6040000) +struct __FILE +{ + int handle; /* Add whatever you need here */ +}; +# endif +#elif(__VER__ >= 8000000) +struct __FILE +{ + int handle; /* Add whatever you need here */ +}; +#endif +FILE __stdout; +FILE __stdin; + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION > 6040000) +# if !defined(__MICROLIB) +__asm(".global __ARM_use_no_argv\n\t" "__ARM_use_no_argv:\n\t"); +# endif +#endif + + +#if (defined(__ARMCC_VERSION) || defined(__ICCARM__)) +extern int32_t SH_DoCommand(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0); + +#if defined( __ICCARM__ ) +__WEAK +#else +__attribute__((weak)) +#endif +uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp); + +#endif + +#pragma pack(push) +#pragma pack(1) +typedef struct { + char *name; + uint32_t u32Addr; + uint8_t u8NSIdx; +} IP_T; +#pragma pack(pop) + +#ifndef DEBUG_ENABLE_SEMIHOST +static IP_T s_IpTbl[] = { +{"SYS",SYS_BASE,0}, +{"CLK",CLK_BASE,0}, +{"INT",INT_BASE,0}, +{"GPIOA",GPIOA_BASE,224+0}, +{"GPIOB",GPIOB_BASE,224+1}, +{"GPIOC",GPIOC_BASE,224+2}, +{"GPIOD",GPIOD_BASE,224+3}, +{"GPIOE",GPIOE_BASE,224+4}, +{"GPIOF",GPIOF_BASE,224+5}, +{"GPIOG",GPIOG_BASE,224+6}, +{"GPIOH",GPIOH_BASE,224+7}, +{"GPIO_DBCTL",GPIO_DBCTL_BASE,0}, +{"PA",GPIO_PIN_DATA_BASE ,224+0}, +{"PB",GPIO_PIN_DATA_BASE+16*4 ,224+0}, +{"PC",GPIO_PIN_DATA_BASE+2*16*4,224+0}, +{"PD",GPIO_PIN_DATA_BASE+3*16*4,224+0}, +{"PE",GPIO_PIN_DATA_BASE+4*16*4,224+0}, +{"PF",GPIO_PIN_DATA_BASE+5*16*4,224+0}, +{"PG",GPIO_PIN_DATA_BASE+6*16*4,224+0}, +{"PH",GPIO_PIN_DATA_BASE+7*16*4,224+0}, +{"PDMA0",PDMA0_BASE,0}, +{"PDMA1",PDMA1_BASE,PDMA1_Attr}, +{"USBH",USBH_BASE,USBH_Attr}, +{"FMC",FMC_BASE,0}, +{"SDH0",SDH0_BASE,SDH0_Attr}, +{"EBI",EBI_BASE,EBI_Attr}, +{"SCU",SCU_BASE,0}, +{"CRC",CRC_BASE,CRC_Attr}, +{"CRPT",CRPT_BASE,CRPT_Attr}, +{"WDT",WDT_BASE,0}, +{"WWDT",WWDT_BASE,0}, +{"RTC",RTC_BASE,RTC_Attr}, +{"EADC",EADC_BASE,EADC_Attr}, +{"ACMP01",ACMP01_BASE,ACMP01_Attr}, +{"DAC0",DAC0_BASE,DAC_Attr}, +{"DAC1",DAC1_BASE,DAC_Attr}, +{"I2S0",I2S0_BASE,I2S0_Attr}, +{"OTG",OTG_BASE,OTG_Attr}, +{"TMR01",TMR01_BASE,0}, +{"TMR23",TMR23_BASE,TMR23_Attr}, +{"EPWM0",EPWM0_BASE,EPWM0_Attr}, +{"EPWM1",EPWM1_BASE,EPWM1_Attr}, +{"BPWM0",BPWM0_BASE,BPWM0_Attr}, +{"BPWM1",BPWM1_BASE,BPWM1_Attr}, +{"QSPI0",QSPI0_BASE,QSPI0_Attr}, +{"SPI0",SPI0_BASE,SPI0_Attr}, +{"SPI1",SPI1_BASE,SPI1_Attr}, +{"SPI2",SPI2_BASE,SPI2_Attr}, +{"SPI3",SPI3_BASE,SPI3_Attr}, +{"UART0",UART0_BASE,UART0_Attr}, +{"UART1",UART1_BASE,UART1_Attr}, +{"UART2",UART2_BASE,UART2_Attr}, +{"UART3",UART3_BASE,UART3_Attr}, +{"UART4",UART4_BASE,UART4_Attr}, +{"UART5",UART5_BASE,UART5_Attr}, +{"I2C0",I2C0_BASE,I2C0_Attr}, +{"I2C1",I2C1_BASE,I2C1_Attr}, +{"I2C2",I2C2_BASE,I2C2_Attr}, +{"SC0",SC0_BASE,SC0_Attr}, +{"SC1",SC1_BASE,SC1_Attr}, +{"SC2",SC2_BASE,SC2_Attr}, +{"CAN0",CAN0_BASE,CAN0_Attr}, +{"QEI0",QEI0_BASE,QEI0_Attr}, +{"QEI1",QEI1_BASE,QEI1_Attr}, +{"ECAP0",ECAP0_BASE,ECAP0_Attr}, +{"ECAP1",ECAP1_BASE,ECAP1_Attr}, +{"TRNG",TRNG_BASE,TRNG_Attr}, +{"USBD",USBD_BASE,USBD_Attr}, +{"USCI0",USCI0_BASE, USCI0_Attr}, +{"USCI1",USCI1_BASE, USCI1_Attr}, +{0,USCI1_BASE+4096, 0}, +}; +#endif + +int kbhit(void); +int IsDebugFifoEmpty(void); +void _ttywrch(int ch); +int fputc(int ch, FILE *stream); + +#if (defined(__ARMCC_VERSION) || defined(__ICCARM__)) +int fgetc(FILE *stream); +int ferror(FILE *stream); +#endif + +char GetChar(void); +void SendChar_ToUART(int ch); +void SendChar(int ch); +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0); +void _sys_exit(int return_code)__attribute__((noreturn)); + +#if (defined(DEBUG_ENABLE_SEMIHOST) || defined(OS_USE_SEMIHOSTING)) +#if (defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)) +/* The static buffer is used to speed up the semihost */ +static char g_buf[16]; +static char g_buf_len = 0; +static volatile int32_t g_ICE_Conneced = 1; + +/** + * @brief This function is called by Hardfault handler. + * @param None + * @returns None + * @details This function is called by Hardfault handler and check if it is caused by __BKPT or not. + * + */ + +uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp) +{ + uint32_t *sp = 0; + uint32_t inst; + + /* Check the used stack */ + if(lr & 0x40) + { + /* Secure stack used */ + if(lr & 4) + sp = (uint32_t *)psp; + else + sp = (uint32_t *)msp; + + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + else + { + /* Non-secure stack used */ + if(lr & 4) + sp = (uint32_t *)__TZ_get_PSP_NS(); + else + sp = (uint32_t *)__TZ_get_MSP_NS(); + + } +#endif + + if (sp != 0) + { + /* Get the instruction caused the hardfault */ + inst = M16(sp[6]); + + + if(inst == 0xBEAB) + { + /* + If the instruction is 0xBEAB, it means it is caused by BKPT without ICE connected. + We still return for output/input message to UART. + */ + g_ICE_Conneced = 0; // Set a flag for ICE offline + sp[6] += 2; // return to next instruction + return lr; // Keep lr in R0 + } + } + + /* It is casued by hardfault (Not semihost). Just process the hard fault here. */ + /* TODO: Implement your hardfault handle code here */ + + /* + printf(" HardFault!\n\n"); + printf("r0 = 0x%x\n", sp[0]); + printf("r1 = 0x%x\n", sp[1]); + printf("r2 = 0x%x\n", sp[2]); + printf("r3 = 0x%x\n", sp[3]); + printf("r12 = 0x%x\n", sp[4]); + printf("lr = 0x%x\n", sp[5]); + printf("pc = 0x%x\n", sp[6]); + printf("psr = 0x%x\n", sp[7]); + */ + + while(1){} + +} + + + +/** + * + * @brief The function to process semihosted command + * @param[in] n32In_R0 : semihost register 0 + * @param[in] n32In_R1 : semihost register 1 + * @param[out] pn32Out_R0: semihost register 0 + * @retval 0: No ICE debug + * @retval 1: ICE debug + * + */ + +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + (void)n32In_R1; + if(g_ICE_Conneced) + { + if(pn32Out_R0) + *pn32Out_R0 = n32In_R0; + + return 1; + } + return 0; +} + + + +#endif +#else // defined(DEBUG_ENABLE_SEMIHOST) + +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0); + +#if defined( __ICCARM__ ) +__WEAK +#else +__attribute__((weak)) +#endif +uint32_t ProcessHardFault(uint32_t lr, uint32_t msp, uint32_t psp) +{ + extern void SCU_IRQHandler(void); + uint32_t *sp = 0ul; + uint32_t i; + uint32_t inst, addr,taddr = 0ul,tdata; + int32_t secure; + uint32_t rm,rn,rt, imm5, imm8; + int32_t eFlag; + uint8_t idx, bit; + int32_t s; + + /* Check the used stack */ + secure = (lr & 0x40ul)?1ul:0ul; + if(secure) + { + /* Secure stack used */ + if(lr & 4UL) + { + sp = (uint32_t *)psp; + } + else + { + sp = (uint32_t *)msp; + } + + } +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3) + else + { + /* Non-secure stack used */ + if(lr & 4) + sp = (uint32_t *)(uint32_t)__TZ_get_PSP_NS(); + else + sp = (uint32_t *)(uint32_t)__TZ_get_MSP_NS(); + + } +#endif + + /* + r0 = sp[0] + r1 = sp[1] + r2 = sp[2] + r3 = sp[3] + r12 = sp[4] + lr = sp[5] + pc = sp[6] + psr = sp[7] + */ + + printf("!!---------------------------------------------------------------!!\n"); + printf(" <<< HardFault >>>\n"); + /* Get the instruction caused the hardfault */ + addr = sp[6]; + inst = M16(addr); + eFlag = 0; + if((!secure) && ((addr & NS_OFFSET) == 0) ) + { + printf(" Non-secure CPU try to fetch secure code in 0x%x\n", addr); + printf(" Try to check NSC region or SAU settings.\n"); + + eFlag = 1; + }else if(inst == 0xBEAB) + { + printf(" Execute BKPT without ICE connected\n"); + eFlag = 2; + } + else if((inst >> 12) == 5) + { + eFlag = 3; + /* 0101xx Load/store (register offset) on page C2-327 of armv8m ref */ + rm = (inst >> 6) & 0x7; + rn = (inst >> 3) & 0x7; + rt = inst & 0x7; + + taddr = sp[rn] + sp[rm]; + tdata = sp[rt]; + if(rn == rt) + { + printf(" [0x%08x] 0x%04x %s R%d [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",rt, taddr); + } + else + { + printf(" [0x%08x] 0x%04x %s 0x%x [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",tdata, taddr); + } + + } + else if((inst >> 13) == 3) + { + eFlag = 3; + /* 011xxx Load/store word/byte (immediate offset) on page C2-327 of armv8m ref */ + imm5 = (inst >> 6) & 0x1f; + rn = (inst >> 3) & 0x7; + rt = inst & 0x7; + + taddr = sp[rn] + imm5; + tdata = sp[rt]; + if(rt == rn) + { + printf(" [0x%08x] 0x%04x %s R%d [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",rt, taddr); + } + else + { + printf(" [0x%08x] 0x%04x %s 0x%x [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",tdata, taddr); + } + } + else if((inst >> 12) == 8) + { + eFlag = 3; + /* 1000xx Load/store halfword (immediate offset) on page C2-328 */ + imm5 = (inst >> 6) & 0x1f; + rn = (inst >> 3) & 0x7; + rt = inst & 0x7; + + taddr = sp[rn] + imm5; + tdata = sp[rt]; + if(rt == rn) + { + printf(" [0x%08x] 0x%04x %s R%d [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",rt, taddr); + } + else + { + printf(" [0x%08x] 0x%04x %s 0x%x [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",tdata, taddr); + } + + } + else if((inst >> 12) == 9) + { + eFlag = 3; + /* 1001xx Load/store (SP-relative) on page C2-328 */ + imm8 = inst & 0xff; + rt = (inst >> 8) & 0x7; + + taddr = sp[6] + imm8; + tdata = sp[rt]; + printf(" [0x%08x] 0x%04x %s 0x%x [0x%x]\n",addr, inst, + (inst&BIT11)?"LDR":"STR",tdata, taddr); + } + else + { + eFlag = 4; + printf(" Unexpected instruction: 0x%04x \n", inst); + } + + if(eFlag == 3) + { + /* It is LDR/STR hardfault */ + if(!secure) + { + /* It is happened in Nonsecure code */ + + for(i=0;i< (uint32_t)(sizeof(s_IpTbl)/sizeof(IP_T)-1);i++) + { + /* Case 1: Nonsecure code try to access secure IP. It also causes SCU violation */ + if((taddr >= s_IpTbl[i].u32Addr) && (taddr < (s_IpTbl[i+1].u32Addr))) + { + idx = s_IpTbl[i].u8NSIdx; + bit = idx & 0x1f; + idx = idx >> 5; + s = (SCU->PNSSET[idx] >> bit) & 1ul; + printf(" Illegal access to %s %s in Nonsecure code.\n",(s)?"Nonsecure":"Secure", s_IpTbl[i].name); + break; + } + + /* Case 2: Nonsecure code try to access Nonsecure IP but the IP is secure IP */ + if((taddr >= (s_IpTbl[i].u32Addr+NS_OFFSET)) && (taddr < (s_IpTbl[i+1].u32Addr+NS_OFFSET))) + { + idx = s_IpTbl[i].u8NSIdx; + bit = idx & 0x1f; + idx = idx >> 5; + s = (SCU->PNSSET[idx] >> bit) & 1ul; + printf(" Illegal access to %s %s in Nonsecure code.\nIt may be set as secure IP here.\n",(s)?"Nonsecure":"Secure", s_IpTbl[i].name); + break; + } + } + } + else + { + /* It is happened in secure code */ + + + if(taddr > NS_OFFSET) + { + /* Case 3: Secure try to access secure IP through Nonsecure address. It also causes SCU violation */ + for(i=0;i< (uint32_t)(sizeof(s_IpTbl)/sizeof(IP_T)-1);i++) + { + if((taddr >= (s_IpTbl[i].u32Addr+NS_OFFSET)) && (taddr < (s_IpTbl[i+1].u32Addr+NS_OFFSET))) + { + idx = s_IpTbl[i].u8NSIdx; + bit = idx & 0x1f; + idx = idx >> 5; + s = (SCU->PNSSET[idx] >> bit) & 1ul; + printf(" Illegal to use Nonsecure address to access %s %s in Secure code\n",(s)?"Nonsecure":"Secure", s_IpTbl[i].name); + break; + } + } + } + + + } + } + + SCU_IRQHandler(); + + printf("!!---------------------------------------------------------------!!\n"); + + /* Or *sp to remove compiler warning */ + while(1U|*sp){} + + return lr; +} + + +int32_t SH_Return(int32_t n32In_R0, int32_t n32In_R1, int32_t *pn32Out_R0) +{ + (void)n32In_R0; + (void)n32In_R1; + (void)pn32Out_R0; + return 0; +} + +#endif /* defined(DEBUG_ENABLE_SEMIHOST) */ + + +/** + * @brief Routine to send a char + * + * @param[in] ch A character data writes to debug port + * + * @returns Send value from UART debug port + * + * @details Send a target char to UART debug port . + */ +#ifndef NONBLOCK_PRINTF +void SendChar_ToUART(int ch) +{ + + while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){} + if((char)ch == '\n') + { + DEBUG_PORT->DAT = '\r'; + while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk){} + } + DEBUG_PORT->DAT = (uint32_t)ch; +} + +#else +/* Non-block implement of send char */ +# define BUF_SIZE 512 +void SendChar_ToUART(int ch) +{ + static uint8_t u8Buf[BUF_SIZE] = {0}; + static int32_t i32Head = 0; + static int32_t i32Tail = 0; + int32_t i32Tmp; + + /* Only flush the data in buffer to UART when ch == 0 */ + if(ch) + { + // Push char + if(ch == '\n') + { + i32Tmp = i32Head+1; + if(i32Tmp > BUF_SIZE) i32Tmp = 0; + if(i32Tmp != i32Tail) + { + u8Buf[i32Head] = '\r'; + i32Head = i32Tmp; + } + } + + i32Tmp = i32Head+1; + if(i32Tmp > BUF_SIZE) i32Tmp = 0; + if(i32Tmp != i32Tail) + { + u8Buf[i32Head] = ch; + i32Head = i32Tmp; + } + } + else + { + if(i32Tail == i32Head) + return; + } + + // pop char + do + { + i32Tmp = i32Tail + 1; + if(i32Tmp > BUF_SIZE) i32Tmp = 0; + + if((DEBUG_PORT->FSR & UART_FSR_TX_FULL_Msk) == 0) + { + DEBUG_PORT->DATA = u8Buf[i32Tail]; + i32Tail = i32Tmp; + } + else + break; // FIFO full + }while(i32Tail != i32Head); +} +#endif + +/** + * @brief Routine to send a char + * + * @param[in] ch A character data writes to debug port + * + * @returns Send value from UART debug port or semihost + * + * @details Send a target char to UART debug port or semihost. + */ +void SendChar(int ch) +{ +#if defined(DEBUG_ENABLE_SEMIHOST) + + g_buf[(uint8_t)g_buf_len++] = (char)ch; + g_buf[(uint8_t)g_buf_len] = '\0'; + if(g_buf_len + 1 >= sizeof(g_buf) || ch == '\n' || ch == '\0') + { + /* Send the char */ + if(g_ICE_Conneced) + { + + if(SH_DoCommand(0x04, (int)g_buf, NULL) != 0) + { + g_buf_len = 0; + + return; + } + } + else + { +# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2 + int i; + + for(i = 0; i < g_buf_len; i++) + SendChar_ToUART(g_buf[i]); + g_buf_len = 0; +# endif + } + } +#else + SendChar_ToUART(ch); +#endif +} + +/** + * @brief Routine to get a char + * + * @param None + * + * @returns Get value from UART debug port or semihost + * + * @details Wait UART debug port or semihost to input a char. + */ +char GetChar(void) +{ +#ifdef DEBUG_ENABLE_SEMIHOST +# if defined (__ICCARM__) + int nRet; + while(SH_DoCommand(0x7, 0, &nRet) != 0) + { + if(nRet != 0) + return (char)nRet; + } +# else + int nRet; + while(SH_DoCommand(0x101, 0, &nRet) != 0) + { + if(nRet != 0) + { + SH_DoCommand(0x07, 0, &nRet); + return (char)nRet; + } + } + + +# if (DEBUG_ENABLE_SEMIHOST == 2) // Re-direct to UART Debug Port only when DEBUG_ENABLE_SEMIHOST=2 + + /* Use debug port when ICE is not connected at semihost mode */ + while(!g_ICE_Conneced) + { + if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0) + { + return (DEBUG_PORT->DAT); + } + } +# endif + +# endif + return (0); +#else + + while(1) + { + if((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U) + { + return ((char)DEBUG_PORT->DAT); + } + } + +#endif +} + +/** + * @brief Check any char input from UART + * + * @param None + * + * @retval 1: No any char input + * @retval 0: Have some char input + * + * @details Check UART RSR RX EMPTY or not to determine if any char input from UART + */ + +int kbhit(void) +{ + return !((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) == 0U); +} +/** + * @brief Check if debug message finished + * + * @param None + * + * @retval 1: Message is finished + * @retval 0: Message is transmitting. + * + * @details Check if message finished (FIFO empty of debug port) + */ + +int IsDebugFifoEmpty(void) +{ + return ((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) != 0U); +} + +/** + * @brief C library retargetting + * + * @param[in] ch Write a character data + * + * @returns None + * + * @details Check if message finished (FIFO empty of debug port) + */ + +void _ttywrch(int ch) +{ + SendChar(ch); + return; +} + + +/** + * @brief Write character to stream + * + * @param[in] ch Character to be written. The character is passed as its int promotion. + * @param[in] stream Pointer to a FILE object that identifies the stream where the character is to be written. + * + * @returns If there are no errors, the same character that has been written is returned. + * If an error occurs, EOF is returned and the error indicator is set (see ferror). + * + * @details Writes a character to the stream and advances the position indicator.\n + * The character is written at the current position of the stream as indicated \n + * by the internal position indicator, which is then advanced one character. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/fputc/. + * + * + */ + +int fputc(int ch, FILE *stream) +{ + (void)stream; + SendChar(ch); + return ch; +} + + +#if (defined(__GNUC__) && !defined(__ARMCC_VERSION)) + +#if !defined(OS_USE_SEMIHOSTING) +int _write (int fd, char *ptr, int len) +{ + int i = len; +#ifdef DEBUG_OUT_PREFIX + char fnt_clr[] = {'\e','[','3','1','m'}; + char *ptr1 = fnt_clr; + int cnt = 5; + fnt_clr[3] = '0' + DEBUG_OUT_PREFIX; + while(cnt--) { + while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk); + DEBUG_PORT->DAT = *ptr1++; + } +#endif + + while(i--) { + while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk); + + if(*ptr == '\n') { + DEBUG_PORT->DAT = '\r'; + while(DEBUG_PORT->FIFOSTS & UART_FIFOSTS_TXFULL_Msk); + } + + DEBUG_PORT->DAT = *ptr++; + } + return len; +} + +int _read (int fd, char *ptr, int len) +{ + + while((DEBUG_PORT->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) != 0); + *ptr = DEBUG_PORT->DAT; + return 1; + + +} +#endif + +#else +/** + * @brief Get character from UART debug port or semihosting input + * + * @param[in] stream Pointer to a FILE object that identifies the stream on which the operation is to be performed. + * + * @returns The character read from UART debug port or semihosting + * + * @details For get message from debug port or semihosting. + * + */ + +int fgetc(FILE *stream) +{ + (void)stream; + return ((int)GetChar()); +} + +/** + * @brief Check error indicator + * + * @param[in] stream Pointer to a FILE object that identifies the stream. + * + * @returns If the error indicator associated with the stream was set, the function returns a nonzero value. + * Otherwise, it returns a zero value. + * + * @details Checks if the error indicator associated with stream is set, returning a value different + * from zero if it is. This indicator is generally set by a previous operation on the stream that failed. + * + * @note The above descriptions are copied from http://www.cplusplus.com/reference/clibrary/cstdio/ferror/. + * + */ + +int ferror(FILE *stream) +{ + (void)stream; + return EOF; +} +#endif + +#ifdef DEBUG_ENABLE_SEMIHOST +# ifdef __ICCARM__ +void __exit(int return_code) +{ + + /* Check if link with ICE */ + if(SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while(IsDebugFifoEmpty() == 0); + } +label: + goto label; /* endless loop */ +} +# else +void _sys_exit(int return_code) +{ + (void)return_code; + /* Check if link with ICE */ + if(SH_DoCommand(0x18, 0x20026, NULL) == 0) + { + /* Make sure all message is print out */ + while(IsDebugFifoEmpty() == 0); + } +label: + goto label; /* endless loop */ +} +# endif +#endif + + + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + + diff --git a/arch/riscv32/fe310/src/StdDriver/src/rtc.c b/arch/riscv32/fe310/src/StdDriver/src/rtc.c new file mode 100644 index 00000000..3af97f59 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/rtc.c @@ -0,0 +1,1067 @@ +/**************************************************************************//** + * @file rtc.c + * @version V3.00 + * @brief Real Time Clock(RTC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @cond HIDDEN_SYMBOLS */ + +/*---------------------------------------------------------------------------------------------------------*/ +/* Macro, type and constant definitions */ +/*---------------------------------------------------------------------------------------------------------*/ +#define RTC_GLOBALS + +/*---------------------------------------------------------------------------------------------------------*/ +/* Global file scope (static) variables */ +/*---------------------------------------------------------------------------------------------------------*/ +static volatile uint32_t g_u32hiYear, g_u32loYear, g_u32hiMonth, g_u32loMonth, g_u32hiDay, g_u32loDay; +static volatile uint32_t g_u32hiHour, g_u32loHour, g_u32hiMin, g_u32loMin, g_u32hiSec, g_u32loSec; + +/** @endcond HIDDEN_SYMBOLS */ + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup RTC_Driver RTC Driver + @{ +*/ + +/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions + @{ +*/ + +/** + * @brief Initialize RTC module and start counting + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This function is used to: \n + * 1. Write initial key to let RTC start count. \n + * 2. Input parameter indicates start date/time. \n + * 3. User has to make sure that parameters of RTC date/time are reasonable. \n + * @note Null pointer for using default starting date/time. + */ +void RTC_Open(S_RTC_TIME_DATA_T *sPt) +{ + RTC->INIT = RTC_INIT_KEY; + + if(RTC->INIT != RTC_INIT_ACTIVE_Msk) + { + RTC->INIT = RTC_INIT_KEY; + while(RTC->INIT != RTC_INIT_ACTIVE_Msk) {} + } + + if(sPt != 0) + { + /* Set RTC date and time */ + RTC_SetDateAndTime(sPt); + } +} + +/** + * @brief Disable RTC Clock + * + * @param None + * + * @return None + * + * @details This API will disable RTC peripheral clock and stops RTC counting. + */ +void RTC_Close(void) +{ + if((__PC()&NS_OFFSET) == 0) + { + /* Disable RTC clock in secure mode only */ + CLK->APBCLK0 &= ~CLK_APBCLK0_RTCCKEN_Msk; + } +} + +/** + * @brief Set 32k Frequency Compensation Data + * + * @param[in] i32FrequencyX10000 Specify the RTC clock X10000, ex: 327736512 means 32773.6512. + * + * @return None + * + * @details This API is used to compensate the 32 kHz frequency by current LXT frequency for RTC application. + */ +void RTC_32KCalibration(int32_t i32FrequencyX10000) +{ + uint64_t u64Compensate; + + /* u64Compensate = (uint64_t)(0x64000000000); */ + u64Compensate = (uint64_t)(0x2710000000000); + u64Compensate = (uint64_t)(u64Compensate / (uint64_t)i32FrequencyX10000); + /* + Formula for 32K compensation is + FREQADJ = 0x200000 * (32768 / LXT_freq) + */ + if(u64Compensate >= (uint64_t)0x400000) + { + u64Compensate = (uint64_t)0x3FFFFF; + } + + RTC_WaitAccessEnable(); + RTC->FREQADJ = (uint32_t)u64Compensate; +} + +/** + * @brief Get Current RTC Date and Time + * + * @param[out] sPt The returned pointer is specified the current RTC value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the current RTC date and time value. + */ +void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get [Date digit] data */ + g_u32hiYear = (RTC->CAL & RTC_CAL_TENYEAR_Msk) >> RTC_CAL_TENYEAR_Pos; + g_u32loYear = (RTC->CAL & RTC_CAL_YEAR_Msk) >> RTC_CAL_YEAR_Pos; + g_u32hiMonth = (RTC->CAL & RTC_CAL_TENMON_Msk) >> RTC_CAL_TENMON_Pos; + g_u32loMonth = (RTC->CAL & RTC_CAL_MON_Msk) >> RTC_CAL_MON_Pos; + g_u32hiDay = (RTC->CAL & RTC_CAL_TENDAY_Msk) >> RTC_CAL_TENDAY_Pos; + g_u32loDay = (RTC->CAL & RTC_CAL_DAY_Msk) >> RTC_CAL_DAY_Pos; + + /* Get [Time digit] data */ + g_u32hiHour = (RTC->TIME & RTC_TIME_TENHR_Msk) >> RTC_TIME_TENHR_Pos; + g_u32loHour = (RTC->TIME & RTC_TIME_HR_Msk) >> RTC_TIME_HR_Pos; + g_u32hiMin = (RTC->TIME & RTC_TIME_TENMIN_Msk) >> RTC_TIME_TENMIN_Pos; + g_u32loMin = (RTC->TIME & RTC_TIME_MIN_Msk) >> RTC_TIME_MIN_Pos; + g_u32hiSec = (RTC->TIME & RTC_TIME_TENSEC_Msk) >> RTC_TIME_TENSEC_Pos; + g_u32loSec = (RTC->TIME & RTC_TIME_SEC_Msk) >> RTC_TIME_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Get RTC Alarm Date and Time + * + * @param[out] sPt The returned pointer is specified the RTC alarm value. It includes: \n + * u32Year: Year value \n + * u32Month: Month value \n + * u32Day: Day value \n + * u32DayOfWeek: Day of week \n + * u32Hour: Hour value \n + * u32Minute: Minute value \n + * u32Second: Second value \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to get the RTC alarm date and time setting. + */ +void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32Tmp; + + sPt->u32TimeScale = RTC->CLKFMT & RTC_CLKFMT_24HEN_Msk; /* 12/24-hour */ + sPt->u32DayOfWeek = RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk; /* Day of the week */ + + /* Get alarm [Date digit] data */ + RTC_WaitAccessEnable(); + g_u32hiYear = (RTC->CALM & RTC_CALM_TENYEAR_Msk) >> RTC_CALM_TENYEAR_Pos; + g_u32loYear = (RTC->CALM & RTC_CALM_YEAR_Msk) >> RTC_CALM_YEAR_Pos; + g_u32hiMonth = (RTC->CALM & RTC_CALM_TENMON_Msk) >> RTC_CALM_TENMON_Pos; + g_u32loMonth = (RTC->CALM & RTC_CALM_MON_Msk) >> RTC_CALM_MON_Pos; + g_u32hiDay = (RTC->CALM & RTC_CALM_TENDAY_Msk) >> RTC_CALM_TENDAY_Pos; + g_u32loDay = (RTC->CALM & RTC_CALM_DAY_Msk) >> RTC_CALM_DAY_Pos; + + /* Get alarm [Time digit] data */ + RTC_WaitAccessEnable(); + g_u32hiHour = (RTC->TALM & RTC_TALM_TENHR_Msk) >> RTC_TALM_TENHR_Pos; + g_u32loHour = (RTC->TALM & RTC_TALM_HR_Msk) >> RTC_TALM_HR_Pos; + g_u32hiMin = (RTC->TALM & RTC_TALM_TENMIN_Msk) >> RTC_TALM_TENMIN_Pos; + g_u32loMin = (RTC->TALM & RTC_TALM_MIN_Msk) >> RTC_TALM_MIN_Pos; + g_u32hiSec = (RTC->TALM & RTC_TALM_TENSEC_Msk) >> RTC_TALM_TENSEC_Pos; + g_u32loSec = (RTC->TALM & RTC_TALM_SEC_Msk) >> RTC_TALM_SEC_Pos; + + /* Compute to 20XX year */ + u32Tmp = (g_u32hiYear * 10UL); + u32Tmp += g_u32loYear; + sPt->u32Year = u32Tmp + (uint32_t)RTC_YEAR2000; + + /* Compute 0~12 month */ + u32Tmp = (g_u32hiMonth * 10UL); + sPt->u32Month = u32Tmp + g_u32loMonth; + + /* Compute 0~31 day */ + u32Tmp = (g_u32hiDay * 10UL); + sPt->u32Day = u32Tmp + g_u32loDay; + + /* Compute 12/24 hour */ + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; /* AM: 1~12. PM: 21~32. */ + + if(sPt->u32Hour >= 21UL) + { + sPt->u32AmPm = (uint32_t)RTC_PM; + sPt->u32Hour -= 20UL; + } + else + { + sPt->u32AmPm = (uint32_t)RTC_AM; + } + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } + else + { + u32Tmp = (g_u32hiHour * 10UL); + u32Tmp += g_u32loHour; + sPt->u32Hour = u32Tmp; + + u32Tmp = (g_u32hiMin * 10UL); + u32Tmp += g_u32loMin; + sPt->u32Minute = u32Tmp; + + u32Tmp = (g_u32hiSec * 10UL); + u32Tmp += g_u32loSec; + sPt->u32Second = u32Tmp; + } +} + +/** + * @brief Update Current RTC Date and Time + * + * @param[in] sPt Specify the time property and current date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update current date and time to RTC. + */ +void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCAL, u32RegTIME; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set Day of the Week */ + RTC->WEEKDAY = sPt->u32DayOfWeek; + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Current Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCAL = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((sPt->u32Month / 10UL) << 12); + u32RegCAL |= ((sPt->u32Month % 10UL) << 8); + u32RegCAL |= ((sPt->u32Day / 10UL) << 4); + u32RegCAL |= (sPt->u32Day % 10UL); + + u32RegTIME = ((sPt->u32Hour / 10UL) << 20); + u32RegTIME |= ((sPt->u32Hour % 10UL) << 16); + u32RegTIME |= ((sPt->u32Minute / 10UL) << 12); + u32RegTIME |= ((sPt->u32Minute % 10UL) << 8); + u32RegTIME |= ((sPt->u32Second / 10UL) << 4); + u32RegTIME |= (sPt->u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Calender and Time Loading */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; + } +} + +/** + * @brief Update RTC Alarm Date and Time + * + * @param[in] sPt Specify the time property and alarm date and time. It includes: \n + * u32Year: Year value, range between 2000 ~ 2099. \n + * u32Month: Month value, range between 1 ~ 12. \n + * u32Day: Day value, range between 1 ~ 31. \n + * u32DayOfWeek: Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] \n + * u32Hour: Hour value, range between 0 ~ 23. \n + * u32Minute: Minute value, range between 0 ~ 59. \n + * u32Second: Second value, range between 0 ~ 59. \n + * u32TimeScale: [RTC_CLOCK_12 / RTC_CLOCK_24] \n + * u8AmPm: [RTC_AM / RTC_PM] \n + * + * @return None + * + * @details This API is used to update alarm date and time setting to RTC. + */ +void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt) +{ + uint32_t u32RegCALM, u32RegTALM; + + if(sPt != 0) + { + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(sPt->u32TimeScale == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + + /*-------------------------------------------------------------------------------------------------*/ + /* Important, range of 12-hour PM mode is 21 up to 32 */ + /*-------------------------------------------------------------------------------------------------*/ + if(sPt->u32AmPm == (uint32_t)RTC_PM) + { + sPt->u32Hour += 20UL; + } + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC Alarm Date and Time */ + /*-----------------------------------------------------------------------------------------------------*/ + u32RegCALM = ((sPt->u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((sPt->u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((sPt->u32Month / 10UL) << 12); + u32RegCALM |= ((sPt->u32Month % 10UL) << 8); + u32RegCALM |= ((sPt->u32Day / 10UL) << 4); + u32RegCALM |= (sPt->u32Day % 10UL); + + u32RegTALM = ((sPt->u32Hour / 10UL) << 20); + u32RegTALM |= ((sPt->u32Hour % 10UL) << 16); + u32RegTALM |= ((sPt->u32Minute / 10UL) << 12); + u32RegTALM |= ((sPt->u32Minute % 10UL) << 8); + u32RegTALM |= ((sPt->u32Second / 10UL) << 4); + u32RegTALM |= (sPt->u32Second % 10UL); + + RTC_WaitAccessEnable(); + RTC->CALM = (uint32_t)u32RegCALM; + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; + } +} + +/** + * @brief Update RTC Current Date + * + * @param[in] u32Year The year calendar digit of current RTC setting. + * @param[in] u32Month The month calendar digit of current RTC setting. + * @param[in] u32Day The day calendar digit of current RTC setting. + * @param[in] u32DayOfWeek The Day of the week. [RTC_SUNDAY / RTC_MONDAY / RTC_TUESDAY / + * RTC_WEDNESDAY / RTC_THURSDAY / RTC_FRIDAY / + * RTC_SATURDAY] + * + * @return None + * + * @details This API is used to update current date to RTC. + */ +void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek) +{ + uint32_t u32RegCAL; + + u32RegCAL = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCAL |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCAL |= ((u32Month / 10UL) << 12); + u32RegCAL |= ((u32Month % 10UL) << 8); + u32RegCAL |= ((u32Day / 10UL) << 4); + u32RegCAL |= (u32Day % 10UL); + + /* Set Day of the Week */ + RTC_WaitAccessEnable(); + RTC->WEEKDAY = u32DayOfWeek & RTC_WEEKDAY_WEEKDAY_Msk; + + /* Set RTC Calender Loading */ + RTC_WaitAccessEnable(); + RTC->CAL = (uint32_t)u32RegCAL; +} + +/** + * @brief Update RTC Current Time + * + * @param[in] u32Hour The hour time digit of current RTC setting. + * @param[in] u32Minute The minute time digit of current RTC setting. + * @param[in] u32Second The second time digit of current RTC setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update current time to RTC. + */ +void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTIME; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTIME = ((u32Hour / 10UL) << 20); + u32RegTIME |= ((u32Hour % 10UL) << 16); + u32RegTIME |= ((u32Minute / 10UL) << 12); + u32RegTIME |= ((u32Minute % 10UL) << 8); + u32RegTIME |= ((u32Second / 10UL) << 4); + u32RegTIME |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + RTC_WaitAccessEnable(); + RTC->TIME = (uint32_t)u32RegTIME; +} + +/** + * @brief Update RTC Alarm Date + * + * @param[in] u32Year The year calendar digit of RTC alarm setting. + * @param[in] u32Month The month calendar digit of RTC alarm setting. + * @param[in] u32Day The day calendar digit of RTC alarm setting. + * + * @return None + * + * @details This API is used to update alarm date setting to RTC. + */ +void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day) +{ + uint32_t u32RegCALM; + + u32RegCALM = ((u32Year - (uint32_t)RTC_YEAR2000) / 10UL) << 20; + u32RegCALM |= (((u32Year - (uint32_t)RTC_YEAR2000) % 10UL) << 16); + u32RegCALM |= ((u32Month / 10UL) << 12); + u32RegCALM |= ((u32Month % 10UL) << 8); + u32RegCALM |= ((u32Day / 10UL) << 4); + u32RegCALM |= (u32Day % 10UL); + + /* Set RTC Alarm Date */ + RTC_WaitAccessEnable(); + RTC->CALM = (uint32_t)u32RegCALM; +} + +/** + * @brief Update RTC Alarm Time + * + * @param[in] u32Hour The hour time digit of RTC alarm setting. + * @param[in] u32Minute The minute time digit of RTC alarm setting. + * @param[in] u32Second The second time digit of RTC alarm setting. + * @param[in] u32TimeMode The 24-Hour / 12-Hour Time Scale Selection. [RTC_CLOCK_12 / RTC_CLOCK_24] + * @param[in] u32AmPm 12-hour time scale with AM and PM indication. Only Time Scale select 12-hour used. [RTC_AM / RTC_PM] + * + * @return None + * + * @details This API is used to update alarm time setting to RTC. + */ +void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm) +{ + uint32_t u32RegTALM; + + /* Important, range of 12-hour PM mode is 21 up to 32 */ + if((u32TimeMode == (uint32_t)RTC_CLOCK_12) && (u32AmPm == (uint32_t)RTC_PM)) + { + u32Hour += 20UL; + } + + u32RegTALM = ((u32Hour / 10UL) << 20); + u32RegTALM |= ((u32Hour % 10UL) << 16); + u32RegTALM |= ((u32Minute / 10UL) << 12); + u32RegTALM |= ((u32Minute % 10UL) << 8); + u32RegTALM |= ((u32Second / 10UL) << 4); + u32RegTALM |= (u32Second % 10UL); + + /*-----------------------------------------------------------------------------------------------------*/ + /* Set RTC 24/12 hour setting and Day of the Week */ + /*-----------------------------------------------------------------------------------------------------*/ + RTC_WaitAccessEnable(); + if(u32TimeMode == (uint32_t)RTC_CLOCK_12) + { + RTC->CLKFMT &= ~RTC_CLKFMT_24HEN_Msk; + } + else + { + RTC->CLKFMT |= RTC_CLKFMT_24HEN_Msk; + } + + /* Set RTC Alarm Time */ + RTC_WaitAccessEnable(); + RTC->TALM = (uint32_t)u32RegTALM; +} + +/** + * @brief Set RTC Alarm Date Mask Function + * + * @param[in] u8IsTenYMsk 1: enable 10-Year digit alarm mask; 0: disabled. + * @param[in] u8IsYMsk 1: enable 1-Year digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Mon digit alarm mask; 0: disabled. + * @param[in] u8IsTenDMsk 1: enable 10-Day digit alarm mask; 0: disabled. + * @param[in] u8IsDMsk 1: enable 1-Day digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm date mask function. + */ +void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk) +{ + RTC_WaitAccessEnable(); + RTC->CAMSK = ((uint32_t)u8IsTenYMsk << RTC_CAMSK_MTENYEAR_Pos) | + ((uint32_t)u8IsYMsk << RTC_CAMSK_MYEAR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_CAMSK_MTENMON_Pos) | + ((uint32_t)u8IsMMsk << RTC_CAMSK_MMON_Pos) | + ((uint32_t)u8IsTenDMsk << RTC_CAMSK_MTENDAY_Pos) | + ((uint32_t)u8IsDMsk << RTC_CAMSK_MDAY_Pos); +} + +/** + * @brief Set RTC Alarm Time Mask Function + * + * @param[in] u8IsTenHMsk 1: enable 10-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsHMsk 1: enable 1-Hour digit alarm mask; 0: disabled. + * @param[in] u8IsTenMMsk 1: enable 10-Min digit alarm mask; 0: disabled. + * @param[in] u8IsMMsk 1: enable 1-Min digit alarm mask; 0: disabled. + * @param[in] u8IsTenSMsk 1: enable 10-Sec digit alarm mask; 0: disabled. + * @param[in] u8IsSMsk 1: enable 1-Sec digit alarm mask; 0: disabled. + * + * @return None + * + * @details This API is used to enable or disable RTC alarm time mask function. + */ +void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk) +{ + RTC_WaitAccessEnable(); + RTC->TAMSK = ((uint32_t)u8IsTenHMsk << RTC_TAMSK_MTENHR_Pos) | + ((uint32_t)u8IsHMsk << RTC_TAMSK_MHR_Pos) | + ((uint32_t)u8IsTenMMsk << RTC_TAMSK_MTENMIN_Pos) | + ((uint32_t)u8IsMMsk << RTC_TAMSK_MMIN_Pos) | + ((uint32_t)u8IsTenSMsk << RTC_TAMSK_MTENSEC_Pos) | + ((uint32_t)u8IsSMsk << RTC_TAMSK_MSEC_Pos); +} + +/** + * @brief Get Day of the Week + * + * @param None + * + * @retval 0 Sunday + * @retval 1 Monday + * @retval 2 Tuesday + * @retval 3 Wednesday + * @retval 4 Thursday + * @retval 5 Friday + * @retval 6 Saturday + * + * @details This API is used to get day of the week of current RTC date. + */ +uint32_t RTC_GetDayOfWeek(void) +{ + return (RTC->WEEKDAY & RTC_WEEKDAY_WEEKDAY_Msk); +} + +/** + * @brief Set RTC Tick Period Time + * + * @param[in] u32TickSelection It is used to set the RTC tick period time for Periodic Time Tick request. \n + * It consists of: + * - \ref RTC_TICK_1_SEC : Time tick is 1 second + * - \ref RTC_TICK_1_2_SEC : Time tick is 1/2 second + * - \ref RTC_TICK_1_4_SEC : Time tick is 1/4 second + * - \ref RTC_TICK_1_8_SEC : Time tick is 1/8 second + * - \ref RTC_TICK_1_16_SEC : Time tick is 1/16 second + * - \ref RTC_TICK_1_32_SEC : Time tick is 1/32 second + * - \ref RTC_TICK_1_64_SEC : Time tick is 1/64 second + * - \ref RTC_TICK_1_128_SEC : Time tick is 1/128 second + * + * @return None + * + * @details This API is used to set RTC tick period time for each tick interrupt. + */ +void RTC_SetTickPeriod(uint32_t u32TickSelection) +{ + RTC_WaitAccessEnable(); + + RTC->TICK = (RTC->TICK & ~RTC_TICK_TICK_Msk) | u32TickSelection; +} + +/** + * @brief Enable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt + * - \ref RTC_INTEN_CLKSPIEN_Msk : LXT Clock Frequency Monitor Stop interrupt + * + * @return None + * + * @details This API is used to enable the specify RTC interrupt function. + */ +void RTC_EnableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN |= u32IntFlagMask; +} + +/** + * @brief Disable RTC Interrupt + * + * @param[in] u32IntFlagMask Specify the interrupt source. It consists of: + * - \ref RTC_INTEN_ALMIEN_Msk : Alarm interrupt + * - \ref RTC_INTEN_TICKIEN_Msk : Tick interrupt + * - \ref RTC_INTEN_TAMP0IEN_Msk : Tamper 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP1IEN_Msk : Tamper 1 or Pair 0 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP2IEN_Msk : Tamper 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP3IEN_Msk : Tamper 3 or Pair 1 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP4IEN_Msk : Tamper 4 Pin Event Detection interrupt + * - \ref RTC_INTEN_TAMP5IEN_Msk : Tamper 5 or Pair 2 Pin Event Detection interrupt + * - \ref RTC_INTEN_CLKFIEN_Msk : LXT Clock Frequency Monitor Fail interrupt + * - \ref RTC_INTEN_CLKSPIEN_Msk : LXT Clock Frequency Monitor Stop interrupt + * + * @return None + * + * @details This API is used to disable the specify RTC interrupt function. + */ +void RTC_DisableInt(uint32_t u32IntFlagMask) +{ + RTC->INTEN &= ~u32IntFlagMask; + RTC->INTSTS = u32IntFlagMask; +} + +/** + * @brief Enable Spare Registers Access + * + * @param None + * + * @return None + * + * @details This API is used to enable the spare registers 0~19 can be accessed. + */ +void RTC_EnableSpareAccess(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL |= RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Disable Spare Register + * + * @param None + * + * @return None + * + * @details This API is used to disable the spare register 0~19 cannot be accessed. + */ +void RTC_DisableSpareRegister(void) +{ + RTC_WaitAccessEnable(); + + RTC->SPRCTL &= ~RTC_SPRCTL_SPRRWEN_Msk; +} + +/** + * @brief Static Tamper Detect + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @param[in] u32DetecLevel Tamper pin detection level select. Possible options are + * - \ref RTC_TAMPER_HIGH_LEVEL_DETECT + * - \ref RTC_TAMPER_LOW_LEVEL_DETECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @return None + * + * @details This API is used to enable the tamper pin detect function with specify trigger condition. + * User need disable dynamic tamper function before use this API. + */ +void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | (u32DetecLevel << RTC_TAMPCTL_TAMP0LV_Pos) | + (u32DebounceEn << RTC_TAMPCTL_TAMP0DBEN_Pos)); + + for(i = 0UL; i < (uint32_t)MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP0LV_Msk | RTC_TAMPCTL_TAMP0DBEN_Msk) << (i * 4UL)); + u32Reg |= (u32TmpReg << (i * 4UL)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; + +} + +/** + * @brief Static Tamper Disable + * + * @param[in] u32TamperSelect Tamper pin select. Possible options are + * - \ref RTC_TAMPER5_SELECT + * - \ref RTC_TAMPER4_SELECT + * - \ref RTC_TAMPER3_SELECT + * - \ref RTC_TAMPER2_SELECT + * - \ref RTC_TAMPER1_SELECT + * - \ref RTC_TAMPER0_SELECT + * + * @return None + * + * @details This API is used to disable the static tamper pin detect. + */ +void RTC_StaticTamperDisable(uint32_t u32TamperSelect) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk); + + for(i = 0UL; i < (uint32_t)MAX_TAMPER_PIN_NUM; i++) + { + if(u32TamperSelect & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << (i * 4UL)); + } + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Detect + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @param[in] u32DebounceEn Tamper pin de-bounce enable + * - \ref RTC_TAMPER_DEBOUNCE_ENABLE + * - \ref RTC_TAMPER_DEBOUNCE_DISABLE + * + * @param[in] u32Pair1Source Dynamic Pair 1 Input Source Select + * 0: Pair 1 source select tamper 2 + * 1: Pair 1 source select tamper 0 + * + * @param[in] u32Pair2Source Dynamic Pair 2 Input Source Select + * 0: Pair 2 source select tamper 4 + * 1: Pair 2 source select tamper 0 + * + * @return None + * + * @details This API is used to enable the dynamic tamper. + */ +void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2Debounce, u32Tamper4Debounce; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + + u32Tamper2Debounce = u32Reg & RTC_TAMPCTL_TAMP2DBEN_Msk; + u32Tamper4Debounce = u32Reg & RTC_TAMPCTL_TAMP4DBEN_Msk; + + u32Reg &= ~(RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_TAMP2EN_Msk | + RTC_TAMPCTL_TAMP3EN_Msk | RTC_TAMPCTL_TAMP4EN_Msk | RTC_TAMPCTL_TAMP5EN_Msk); + u32Reg &= ~(RTC_TAMPCTL_DYN1ISS_Msk | RTC_TAMPCTL_DYN2ISS_Msk); + u32Reg |= ((u32Pair1Source & 0x1UL) << RTC_TAMPCTL_DYN1ISS_Pos) | ((u32Pair2Source & 0x1UL) << RTC_TAMPCTL_DYN2ISS_Pos); + + if(u32DebounceEn) + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | + RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + else + { + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + } + + for(i = 0UL; i < (uint32_t)MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~((RTC_TAMPCTL_TAMP0DBEN_Msk | RTC_TAMPCTL_TAMP1DBEN_Msk) << (i * 8UL)); + u32Reg |= (u32TmpReg << (i * 8UL)); + } + } + + if((u32Pair1Source) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP2EN_Msk; + u32Reg |= u32Tamper2Debounce; + } + + if((u32Pair2Source) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Reg &= ~RTC_TAMPCTL_TAMP4EN_Msk; + u32Reg |= u32Tamper4Debounce; + } + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Dynamic Tamper Disable + * + * @param[in] u32PairSel Tamper pin detection enable. Possible options are + * - \ref RTC_PAIR0_SELECT + * - \ref RTC_PAIR1_SELECT + * - \ref RTC_PAIR2_SELECT + * + * @return None + * + * @details This API is used to disable the dynamic tamper. + */ +void RTC_DynamicTamperDisable(uint32_t u32PairSel) +{ + uint32_t i; + uint32_t u32Reg; + uint32_t u32TmpReg; + uint32_t u32Tamper2En = 0UL, u32Tamper4En = 0UL; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN1ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR1_SELECT)) + { + u32Tamper2En = u32Reg & RTC_TAMPCTL_TAMP2EN_Msk; + } + + if((u32Reg & (uint32_t)RTC_TAMPCTL_DYN2ISS_Msk) && (u32PairSel & (uint32_t)RTC_PAIR2_SELECT)) + { + u32Tamper4En = u32Reg & RTC_TAMPCTL_TAMP4EN_Msk; + } + + u32TmpReg = (RTC_TAMPCTL_TAMP0EN_Msk | RTC_TAMPCTL_TAMP1EN_Msk | RTC_TAMPCTL_DYNPR0EN_Msk); + + for(i = 0UL; i < (uint32_t)MAX_PAIR_NUM; i++) + { + if(u32PairSel & (0x1UL << i)) + { + u32Reg &= ~(u32TmpReg << ((i * 8UL))); + } + } + + u32Reg |= (u32Tamper2En | u32Tamper4En); + + RTC_WaitAccessEnable(); + RTC->TAMPCTL = u32Reg; +} + +/** + * @brief Config dynamic tamper + * + * @param[in] u32ChangeRate The dynamic tamper output change rate + * - \ref RTC_2POW10_CLK + * - \ref RTC_2POW11_CLK + * - \ref RTC_2POW12_CLK + * - \ref RTC_2POW13_CLK + * - \ref RTC_2POW14_CLK + * - \ref RTC_2POW15_CLK + * - \ref RTC_2POW16_CLK + * - \ref RTC_2POW17_CLK + * + * @param[in] u32SeedReload Reload new seed or not + * 0: not reload new seed + * 1: reload new seed + * + * @param[in] u32RefPattern Reference pattern + * - \ref REF_RANDOM_PATTERN + * - \ref REF_PREVIOUS_PATTERN + * - \ref REF_SEED + * + * @param[in] u32Seed Seed Value (0x0 ~ 0xFFFFFFFF) + * + * @return None + * + * @details This API is used to config dynamic tamper setting. + */ +void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed) +{ + uint32_t u32Reg; + + RTC_WaitAccessEnable(); + u32Reg = RTC->TAMPCTL; + + u32Reg &= ~(RTC_TAMPCTL_DYNSRC_Msk | RTC_TAMPCTL_SEEDRLD_Msk | RTC_TAMPCTL_DYNRATE_Msk); + + u32Reg |= (u32ChangeRate) | ((u32SeedReload & 0x1UL) << RTC_TAMPCTL_SEEDRLD_Pos) | + ((u32RefPattern & 0x3UL) << RTC_TAMPCTL_DYNSRC_Pos); + + RTC_WaitAccessEnable(); + RTC->TAMPSEED = u32Seed; /* need set seed value before re-loade seed */ + RTC->TAMPCTL = u32Reg; +} + +/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group RTC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/sc.c b/arch/riscv32/fe310/src/StdDriver/src/sc.c new file mode 100644 index 00000000..26f27f61 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/sc.c @@ -0,0 +1,428 @@ +/**************************************************************************//** + * @file sc.c + * @version V3.00 + * @brief Smartcard(SC) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. + *****************************************************************************/ +#include "NuMicro.h" + +/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */ +/** @cond HIDDEN_SYMBOLS */ +static uint32_t g_u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL}; + +/** @endcond HIDDEN_SYMBOLS */ + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SC_Driver SC Driver + @{ +*/ + +/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions + @{ +*/ + +/** + * @brief Indicates specified smartcard slot status + * + * @param[in] sc The pointer of smartcard module. + * + * @return Card insert status + * @retval TRUE Card insert + * @retval FALSE Card remove + * + * @details This function is used to check if specified smartcard slot is presented. + */ +uint32_t SC_IsCardInserted(SC_T *sc) +{ + uint32_t u32Ret; + + /* put conditions into two variable to remove IAR compilation warning */ + uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos); + uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos); + + if(((sc == SC0) || (sc == SC0_NS)) && (g_u32CardStateIgnore[0] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(((sc == SC1) || (sc == SC1_NS)) && (g_u32CardStateIgnore[1] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(((sc == SC2) || (sc == SC2_NS)) && (g_u32CardStateIgnore[2] == 1UL)) + { + u32Ret = (uint32_t)TRUE; + } + else if(cond1 != cond2) + { + u32Ret = (uint32_t)FALSE; + } + else + { + u32Ret = (uint32_t)TRUE; + } + + return u32Ret; +} + +/* + * @brief Reset the Tx and Rx FIFO of smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset both transmit and receive FIFO of specified smartcard module. + */ +void SC_ClearFIFO(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk); +} + +/** + * @brief Disable specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function disable specified smartcard module, and force all transition to IDLE state. + */ +void SC_Close(SC_T *sc) +{ + sc->INTEN = 0UL; + while(sc->PINCTL & SC_PINCTL_SYNC_Msk) {} + + sc->PINCTL = 0UL; + sc->ALTCTL = 0UL; + while(sc->CTL & SC_CTL_SYNC_Msk) {} + + sc->CTL = 0UL; +} + +/** + * @brief Initialized smartcard module + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CardDet Card detect polarity, select the SC_CD pin state which indicates card absent. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present. + * @param[in] u32PWR Power off polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be: + * -\ref SC_PIN_STATE_HIGH + * -\ref SC_PIN_STATE_LOW + * + * @return None + * + * @details This function initialized smartcard module. + */ +void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR) +{ + uint32_t u32Reg = 0UL, u32Intf; + + if((sc == SC0) || (sc == SC0_NS)) + { + u32Intf = 0UL; + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + if(u32CardDet != SC_PIN_STATE_IGNORE) + { + u32Reg = u32CardDet ? 0UL : SC_CTL_CDLV_Msk; + g_u32CardStateIgnore[u32Intf] = 0UL; + } + else + { + g_u32CardStateIgnore[u32Intf] = 1UL; + } + sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk; + while(sc->CTL & SC_CTL_SYNC_Msk) {} + + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_TMRSEL_Msk | u32Reg; +} + +/** + * @brief Reset specified smartcard module + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @details This function reset specified smartcard module to its default state for activate smartcard. + */ +void SC_ResetReader(SC_T *sc) +{ + uint32_t u32Intf; + + if((sc == SC0) || (sc == SC0_NS)) + { + u32Intf = 0UL; + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Intf = 1UL; + } + else + { + u32Intf = 2UL; + } + + /* Reset FIFO, enable auto de-activation while card removal */ + sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk); + /* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */ + while(sc->CTL & SC_CTL_SYNC_Msk) {} + + sc->CTL &= ~(SC_CTL_RXTRGLV_Msk | + SC_CTL_CDDBSEL_Msk | + SC_CTL_TXRTY_Msk | + SC_CTL_TXRTYEN_Msk | + SC_CTL_RXRTY_Msk | + SC_CTL_RXRTYEN_Msk); + while(sc->CTL & SC_CTL_SYNC_Msk) {} + + /* Enable auto convention, and all three smartcard internal timers */ + sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk; + /* Disable Rx timeout */ + sc->RXTOUT = 0UL; + /* 372 clocks per ETU by default */ + sc->ETUCTL = 371UL; + + /* Enable necessary interrupt for smartcard operation */ + if(g_u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */ + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk); + } + else + { + sc->INTEN = (SC_INTEN_RDAIEN_Msk | + SC_INTEN_TERRIEN_Msk | + SC_INTEN_TMR0IEN_Msk | + SC_INTEN_TMR1IEN_Msk | + SC_INTEN_TMR2IEN_Msk | + SC_INTEN_BGTIEN_Msk | + SC_INTEN_ACERRIEN_Msk | + SC_INTEN_CDIEN_Msk); + } + + return; +} + +/** + * @brief Set Block Guard Time (BGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32. + * + * @return None + * + * @details This function is used to configure block guard time (BGT) of specified smartcard module. + */ +void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT) +{ + sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos); +} + +/** + * @brief Set Character Guard Time (CGT) + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267. + * + * @return None + * + * @details This function is used to configure character guard time (CGT) of specified smartcard module. + * @note Before using this API, user should set the correct stop bit length first. + */ +void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT) +{ + /* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */ + u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL; + sc->EGT = u32CGT; +} + +/** + * @brief Stop all smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * + * @return None + * + * @note This function stop the timers within specified smartcard module, \b not timer module. + */ +void SC_StopAllTimer(SC_T *sc) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk); +} + +/** + * @brief Configure and start smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to start. Valid values are 0, 1, 2. + * @param[in] u32Mode Timer operating mode, valid values are: + * - \ref SC_TMR_MODE_0 + * - \ref SC_TMR_MODE_1 + * - \ref SC_TMR_MODE_2 + * - \ref SC_TMR_MODE_3 + * - \ref SC_TMR_MODE_4 + * - \ref SC_TMR_MODE_5 + * - \ref SC_TMR_MODE_6 + * - \ref SC_TMR_MODE_7 + * - \ref SC_TMR_MODE_8 + * - \ref SC_TMR_MODE_F + * @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs. + * For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs. + * + * @return None + * + * @note This function start the timer within specified smartcard module, \b not timer module. + * @note Depend on the timer operating mode, timer may not start counting immediately and starts when condition match. + */ +void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount) +{ + uint32_t u32Reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL)); + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + if(u32TimerNum == 0UL) + { + while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk) {} + sc->TMRCTL0 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) + { + while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk) {} + sc->TMRCTL1 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk) {} + sc->TMRCTL2 = u32Reg; + sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Stop a smartcard timer + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TimerNum Timer to stop. Valid values are 0, 1, 2. + * + * @return None + * + * @note This function stop the timer within specified smartcard module, \b not timer module. + */ +void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum) +{ + while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk) {} + + if(u32TimerNum == 0UL) /* timer 0 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk; + } + else if(u32TimerNum == 1UL) /* timer 1 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk; + } + else /* timer 2 */ + { + sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk; + } +} + +/** + * @brief Get smartcard clock frequency + * + * @param[in] sc The pointer of smartcard module. + * + * @return Smartcard frequency in kHZ + * + * @details This function is used to get specified smartcard module clock frequency in kHz. + */ +uint32_t SC_GetInterfaceClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div; + + /* Get smartcard module clock source and divider */ + if((sc == SC0) || (sc == SC0_NS)) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if((sc == SC2) || (sc == SC2_NS)) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + return 0UL; + } + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (u32Div + 1UL) * 1000UL; + + return u32Clk; +} + +/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SC_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/scuart.c b/arch/riscv32/fe310/src/StdDriver/src/scuart.c new file mode 100644 index 00000000..dd23bfee --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/scuart.c @@ -0,0 +1,269 @@ +/**************************************************************************//** + * @file scuart.c + * @version V3.00 + * @brief Smartcard UART mode (SCUART) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +static uint32_t SCUART_GetClock(SC_T *sc); + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SCUART_Driver SCUART Driver + @{ +*/ + +/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions + @{ +*/ + +/** + * @brief Disable smartcard interface + * + * @param sc The pointer of smartcard module. + * + * @return None + * + * @details The function is used to disable smartcard interface UART mode. + */ +void SCUART_Close(SC_T* sc) +{ + sc->INTEN = 0UL; + sc->UARTCTL = 0UL; + sc->CTL = 0UL; +} + +/** @cond HIDDEN_SYMBOLS */ +/** + * @brief Returns module clock of specified SC interface + * + * @param[in] sc The pointer of smartcard module. + * + * @return Module clock of specified SC interface. + */ +static uint32_t SCUART_GetClock(SC_T *sc) +{ + uint32_t u32ClkSrc, u32Num, u32Clk = __HIRC, u32Div; + + /* Get smartcard module clock source and divider */ + if((sc == SC0) || (sc == SC0_NS)) + { + u32Num = 0UL; + u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE); + u32Div = CLK_GetModuleClockDivider(SC0_MODULE); + } + else if((sc == SC1) || (sc == SC1_NS)) + { + u32Num = 1UL; + u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE); + u32Div = CLK_GetModuleClockDivider(SC1_MODULE); + } + else if((sc == SC2) || (sc == SC2_NS)) + { + u32Num = 2UL; + u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE); + u32Div = CLK_GetModuleClockDivider(SC2_MODULE); + } + else + { + return 0UL; + } + + /* Get smartcard module clock */ + if(u32ClkSrc == 0UL) + { + u32Clk = __HXT; + } + else if(u32ClkSrc == 1UL) + { + u32Clk = CLK_GetPLLClockFreq(); + } + else if(u32ClkSrc == 2UL) + { + if(u32Num == 1UL) + { + u32Clk = CLK_GetPCLK1Freq(); + } + else + { + u32Clk = CLK_GetPCLK0Freq(); + } + } + else + { + u32Clk = __HIRC; + } + + u32Clk /= (u32Div + 1UL); + + return u32Clk; +} +/** @endcond HIDDEN_SYMBOLS */ + +/** + * @brief Enable smartcard module UART mode and set baudrate + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART module. + * + * @return Actual baudrate of smartcard UART mode + * + * @details This function use to enable smartcard module UART mode and set baudrate. + * + * @note This function configures character width to 8 bits, 1 stop bit, and no parity. + * And can use \ref SCUART_SetLineConfig function to update these settings. + * The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + /* Calculate divider for target baudrate */ + u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL; + + sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; /* Enable smartcard interface and stop bit = 1 */ + sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; /* Enable UART mode, disable parity and 8 bit per character */ + sc->ETUCTL = u32Div; + + return(u32Clk / (u32Div + 1UL)); +} + +/** + * @brief Read Rx data from Rx FIFO + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8RxBuf The buffer to store receive the data. + * @param[in] u32ReadBytes Target number of characters to receive + * + * @return Actual character number reads to buffer + * + * @details The function is used to read data from Rx FIFO. + * + * @note This function does not block and return immediately if there's no data available. + */ +uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++) + { + if(SCUART_GET_RX_EMPTY(sc)) /* no data available */ + { + break; + } + pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */ + } + + return u32Count; +} + +/** + * @brief Configure smartcard UART mode line setting + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32Baudrate Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change. + * @param[in] u32DataWidth The data length, could be: + * - \ref SCUART_CHAR_LEN_5 + * - \ref SCUART_CHAR_LEN_6 + * - \ref SCUART_CHAR_LEN_7 + * - \ref SCUART_CHAR_LEN_8 + * @param[in] u32Parity The parity setting, could be: + * - \ref SCUART_PARITY_NONE + * - \ref SCUART_PARITY_ODD + * - \ref SCUART_PARITY_EVEN + * @param[in] u32StopBits The stop bit length, could be: + * - \ref SCUART_STOP_BIT_1 + * - \ref SCUART_STOP_BIT_2 + * + * @return Actual baudrate of smartcard UART mode + * + * @details The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled + * by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1 + * register. Since the baudrate divider is 12-bit wide and must be larger than 4, + * (clock source / baudrate) must be larger or equal to 5 and smaller or equal to + * 4096. Otherwise this function cannot configure SCUART to work with target baudrate. + */ +uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits) +{ + uint32_t u32Clk = SCUART_GetClock(sc), u32Div; + + if(u32Baudrate == 0UL) + { + /* Keep original baudrate setting */ + u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk; + } + else + { + /* Calculate divider for target baudrate */ + u32Div = ((u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate) - 1UL; + sc->ETUCTL = u32Div; + } + + sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; /* Set stop bit */ + sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; /* Set character width and parity */ + + return (u32Clk / (u32Div + 1UL)); +} + +/** + * @brief Set receive timeout count + * + * @param[in] sc The pointer of smartcard module. + * @param[in] u32TOC Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF, + * set this value to 0 will disable time-out counter. + * + * @return None + * + * @details The time-out counter resets and starts counting whenever the Rx buffer received a + * new data word. Once the counter decrease to 1 and no new data is received or CPU + * does not read any data from FIFO, a receiver time-out interrupt will be generated. + */ +void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC) +{ + sc->RXTOUT = u32TOC; +} + +/** + * @brief Write data into transmit FIFO to send data out + * + * @param[in] sc The pointer of smartcard module. + * @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO. + * @param[in] u32WriteBytes Number of data to send. + * + * @return None + * + * @details This function is used to write data into Tx FIFO to send data out. + * + * @note This function blocks until all data write into FIFO. + */ +void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count; + + for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++) + { + /* Wait 'til FIFO not full */ + while(SCUART_GET_TX_FULL(sc)) {} + + /* Write 1 byte to FIFO */ + sc->DAT = pu8TxBuf[u32Count]; /* Write 1 byte to FIFO */ + } +} + + +/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SCUART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/sdh.c b/arch/riscv32/fe310/src/StdDriver/src/sdh.c new file mode 100644 index 00000000..ec9a3554 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/sdh.c @@ -0,0 +1,1147 @@ +/**************************************************************************//** + * @file SDH.c + * @version V1.00 + * @brief M2351 SDH driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include +#include +#include +#include "NuMicro.h" + +#if defined (__ICCARM__) +# pragma diag_suppress=Pm073, Pm143 /* Misra C 2004 rule 14.7 */ +#endif + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SDH_Driver SDH Driver + @{ +*/ + +/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions + @{ +*/ + +#define SDH_BLOCK_SIZE 512UL + +/* #define DEBUG_PRINTF printf */ +#define DEBUG_PRINTF(...) + +/** @cond HIDDEN_SYMBOLS */ + +/* global variables */ +/* For response R3 (such as ACMD41, CRC-7 is invalid; but SD controller will still */ +/* calculate CRC-7 and get an error result, software should ignore this error and clear SDISR [CRC_IF] flag */ +/* _sd_uR3_CMD is the flag for it. 1 means software should ignore CRC-7 error */ +uint8_t g_u8R3Flag = 0UL; +uint8_t volatile g_u8SDDataReadyFlag = (uint8_t)FALSE; +int SDH_ok = 0; + +static uint32_t _SDH_uR7_CMD = 0UL; +static uint32_t _SDH_ReferenceClock; + +#if defined ( __ICCARM__ ) /*!< IAR Compiler */ +#pragma data_alignment = 4 +static uint8_t _SDH_ucSDHCBuffer[512]; +#else +static __attribute__((aligned)) uint8_t _SDH_ucSDHCBuffer[512]; +#endif + +/* Declare these functions here to avoid MISRA C 2004 rule 8.1 error */ +void SDH_CheckRB(SDH_T *sdh); +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg); +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount); +uint32_t SDH_Swap32(uint32_t u32Val); +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]); +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg); +void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz); +uint32_t SDH_CardDetection(SDH_T *sdh); +uint32_t SDH_Init(SDH_T *sdh); +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD); +uint32_t SDH_SelectCardType(SDH_T *sdh); +void SDH_Get_SD_info(SDH_T *sdh); + +SDH_INFO_T SD0; + +void SDH_CheckRB(SDH_T *sdh) +{ + while(1) + { + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + if(sdh->INTSTS & SDH_INTSTS_DAT0STS_Msk) + { + break; + } + } +} + + +uint32_t SDH_SDCommand(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg) +{ + SDH_INFO_T *pSD; + volatile uint32_t u32Status = Successful; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk); + + while(sdh->CTL & SDH_CTL_COEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + u32Status = SDH_NO_SD_CARD; + } + } + return u32Status; +} + + +uint32_t SDH_SDCmdAndRsp(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t u32TickCount) +{ + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk); + + if(u32TickCount > 0UL) + { + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(u32TickCount-- == 0UL) + { + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* reset SD engine */ + return 2UL; + } + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + else + { + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + } + + if(_SDH_uR7_CMD) + { + if((sdh->RESP1 & 0xffUL) != 0x55UL) + { + if((sdh->RESP0 & 0xfUL) != 0x01UL) + { + _SDH_uR7_CMD = 0UL; + return SDH_CMD8_ERROR; + } + } + } + + if(!g_u8R3Flag) + { + if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk) /* check CRC7 */ + { + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } + } + else /* ignore CRC error for R3 case */ + { + g_u8R3Flag = 0UL; + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return Successful; + } +} + + +uint32_t SDH_Swap32(uint32_t u32Val) +{ + uint32_t u32Buf; + + u32Buf = u32Val; + u32Val <<= 24; + u32Val |= (u32Buf << 8) & 0xff0000UL; + u32Val |= (u32Buf >> 8) & 0xff00UL; + u32Val |= (u32Buf >> 24) & 0xffUL; + return u32Val; +} + +/* Get 16 bytes CID or CSD */ +uint32_t SDH_SDCmdAndRsp2(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg, uint32_t pu32R2ptr[]) +{ + uint32_t i; + uint32_t au32TmpBuf[5]; + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | (u32Cmd << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_R2EN_Msk); + + while(sdh->CTL & SDH_CTL_R2EN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(sdh->INTSTS & SDH_INTSTS_CRC7_Msk) + { + for(i = 0UL; i < 5UL; i++) + { + au32TmpBuf[i] = SDH_Swap32(sdh->FB[i]); + } + for(i = 0UL; i < 4UL; i++) + { + pu32R2ptr[i] = ((au32TmpBuf[i] & 0x00ffffffUL) << 8) | ((au32TmpBuf[i + 1UL] & 0xff000000UL) >> 24); + } + return Successful; + } + else + { + return SDH_CRC7_ERROR; + } +} + + +uint32_t SDH_SDCmdAndRspDataIn(SDH_T *sdh, uint32_t u32Cmd, uint32_t u32Arg) +{ + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + sdh->CMDARG = u32Arg; + sdh->CTL = (sdh->CTL & (~SDH_CTL_CMDCODE_Msk)) | ((uint32_t)u32Cmd << 8) | + (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + + while(sdh->CTL & SDH_CTL_RIEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + while(sdh->CTL & SDH_CTL_DIEN_Msk) + { + if(pSD->IsCardInsert == (uint32_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + + return Successful; +} + +/* there are 8 bits for divider0, maximum is 256 */ +#define SDH_CLK_DIV0_MAX 256UL + +void SDH_Set_clock(SDH_T *sdh, uint32_t u32SDClockKhz) +{ + if(!(__PC() & NS_OFFSET)) + { + uint32_t u32Rate, u32Div1; + static uint32_t u32SDClkSrc = 0UL; + + if (sdh == SDH0) + { + /* M2351 is only support SDH0 */ + u32SDClkSrc = (CLK->CLKSEL0 & CLK_CLKSEL0_SDH0SEL_Msk); + if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HXT) + { + _SDH_ReferenceClock = (CLK_GetHXTFreq() / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HIRC) + { + _SDH_ReferenceClock = (__HIRC / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_PLL) + { + _SDH_ReferenceClock = (CLK_GetPLLClockFreq() / 1000UL); + } + else if(u32SDClkSrc == CLK_CLKSEL0_SDH0SEL_HCLK) + { + _SDH_ReferenceClock = (CLK_GetHCLKFreq() / 1000UL); + } + } + + if(u32SDClockKhz >= 50000UL) + { + u32SDClockKhz = 50000UL; + } + u32Rate = _SDH_ReferenceClock / u32SDClockKhz; + + /* choose slower clock if system clock cannot divisible by wanted clock */ + if(_SDH_ReferenceClock % u32SDClockKhz != 0UL) + { + u32Rate++; + } + + if(u32Rate >= SDH_CLK_DIV0_MAX) + { + u32Rate = SDH_CLK_DIV0_MAX; + } + + /* --- calculate the second divider CLKDIV0[SDHOST_N] */ + if(u32Rate == 0UL) + { + u32Div1 = 0UL; + } + else + { + u32Div1 = ((u32Rate - 1UL) & 0xFFUL); + } + + /* --- setup register */ + if (sdh == SDH0) + { + /* M2351 is only support SDH0 */ + CLK->CLKDIV0 &= ~CLK_CLKDIV0_SDH0DIV_Msk; + CLK->CLKDIV0 |= (u32Div1 << CLK_CLKDIV0_SDH0DIV_Pos); + } + } +} + +uint32_t SDH_CardDetection(SDH_T *sdh) +{ + uint32_t i, u32Status = (uint32_t)TRUE; + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + if(sdh->INTEN & SDH_INTEN_CDSRC_Msk) /* Card detect pin from GPIO */ + { + if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card remove */ + { + pSD->IsCardInsert = (uint8_t)FALSE; + u32Status = (uint32_t)FALSE; + } + else + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + } + else if(!(sdh->INTEN & SDH_INTEN_CDSRC_Msk)) + { + sdh->CTL |= SDH_CTL_CLKKEEP_Msk; + for(i = 0UL; i < 5000UL; i++) {} + + if(sdh->INTSTS & SDH_INTSTS_CDSTS_Msk) /* Card insert */ + { + pSD->IsCardInsert = (uint8_t)TRUE; + } + else + { + pSD->IsCardInsert = (uint8_t)FALSE; + u32Status = (uint32_t)FALSE; + } + + sdh->CTL &= ~SDH_CTL_CLKKEEP_Msk; + } + + return u32Status; +} + + +/* Initial */ +uint32_t SDH_Init(SDH_T *sdh) +{ + uint32_t volatile i, u32Status; + uint32_t u32Resp; + uint32_t au32CIDBuffer[4]; + uint32_t volatile u32CmdTimeOut; + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + /* set the clock to 300KHz */ + SDH_Set_clock(sdh, 300UL); + + /* power ON 74 clock */ + sdh->CTL |= SDH_CTL_CLK74OEN_Msk; + + while(sdh->CTL & SDH_CTL_CLK74OEN_Msk) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */ + for(i = 0x1000UL; i > 0UL; i--) {} + + /* initial SDHC */ + _SDH_uR7_CMD = 1UL; + u32CmdTimeOut = 0xFFFFFUL; + + i = SDH_SDCmdAndRsp(sdh, 8UL, 0x00000155UL, u32CmdTimeOut); + if(i == Successful) + { + /* SD 2.0 */ + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 2.7v-3.6v */ + u32Resp = sdh->RESP0; + + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x40ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + } + if(u32Resp & 0x00400000UL) + { + pSD->CardType = SDH_TYPE_SD_HIGH; + } + else + { + pSD->CardType = SDH_TYPE_SD_LOW; + } + } + else + { + /* SD 1.1 */ + SDH_SDCommand(sdh, 0UL, 0UL); /* reset all cards */ + for(i = 0x100UL; i > 0UL; i--) {} + + i = SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + if(i == 2UL) /* MMC memory */ + { + SDH_SDCommand(sdh, 0UL, 0UL); /* reset */ + for(i = 0x100UL; i > 0UL; i--) {} + + g_u8R3Flag = 1UL; + + if(SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut) != 2UL) /* eMMC memory */ + { + u32Resp = sdh->RESP0; + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + g_u8R3Flag = 1UL; + + SDH_SDCmdAndRsp(sdh, 1UL, 0x40ff8000UL, u32CmdTimeOut); /* high voltage */ + u32Resp = sdh->RESP0; + } + + if(u32Resp & 0x00400000UL) + { + pSD->CardType = SDH_TYPE_EMMC; + } + else + { + pSD->CardType = SDH_TYPE_MMC; + } + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_ERR_DEVICE; + } + } + else if(i == 0UL) /* SD Memory */ + { + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + while(!(u32Resp & 0x00800000UL)) /* check if card is ready */ + { + SDH_SDCmdAndRsp(sdh, 55UL, 0x00UL, u32CmdTimeOut); + g_u8R3Flag = 1UL; + SDH_SDCmdAndRsp(sdh, 41UL, 0x00ff8000UL, u32CmdTimeOut); /* 3.0v-3.4v */ + u32Resp = sdh->RESP0; + } + pSD->CardType = SDH_TYPE_SD_LOW; + } + else + { + pSD->CardType = SDH_TYPE_UNKNOWN; + return SDH_INIT_ERROR; + } + } + + /* CMD2, CMD3 */ + if(pSD->CardType != SDH_TYPE_UNKNOWN) + { + SDH_SDCmdAndRsp2(sdh, 2UL, 0x00UL, au32CIDBuffer); + if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x10000UL, 0UL)) != Successful) /* set RCA */ + { + return u32Status; + } + pSD->RCA = 0x10000UL; + } + else + { + if((u32Status = SDH_SDCmdAndRsp(sdh, 3UL, 0x00UL, 0UL)) != Successful) /* get RCA */ + { + return u32Status; + } + else + { + pSD->RCA = (sdh->RESP0 << 8) & 0xffff0000UL; + } + } + } + + return Successful; +} + + +uint32_t SDH_SwitchToHighSpeed(SDH_T *sdh, SDH_INFO_T *pSD) +{ + uint32_t volatile u32Status = 0UL; + uint16_t u16CurrentComsumption, u16BusyStatus0; + + (void)pSD; + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 63UL; /* 512 bit */ + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x00ffff01UL)) != Successful) + { + return Fail; + } + + u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8); + u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if(!u16CurrentComsumption) + { + return Fail; + } + + u16BusyStatus0 = (uint16_t)(_SDH_ucSDHCBuffer[28] << 8); + u16BusyStatus0 |= (uint16_t)_SDH_ucSDHCBuffer[29]; + + if(!u16BusyStatus0) /* function ready */ + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 63UL; /* 512 bit */ + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 6UL, 0x80ffff01UL)) != Successful) + { + return Fail; + } + + /* function change timing: 8 clocks */ + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + u16CurrentComsumption = (uint16_t)(_SDH_ucSDHCBuffer[0] << 8); + u16CurrentComsumption |= (uint16_t)_SDH_ucSDHCBuffer[1]; + if(!u16CurrentComsumption) + { + return Fail; + } + + return Successful; + } + else + { + return Fail; + } +} + + +uint32_t SDH_SelectCardType(SDH_T *sdh) +{ + uint32_t volatile u32Status = 0UL; + uint32_t u32Param; + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + SDH_CheckRB(sdh); + + /* if SD card set 4bit */ + if(pSD->CardType == SDH_TYPE_SD_HIGH) + { + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 0x07UL; /* 64 bit */ + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + sdh->DMACTL |= 0x2; + while(sdh->DMACTL & 0x2) {} + + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful) + { + return u32Status; + } + + if((_SDH_ucSDHCBuffer[0] & 0xfUL) == 0xfUL) + { + u32Status = SDH_SwitchToHighSpeed(sdh, pSD); + if(u32Status == Successful) + { + /* divider */ + SDH_Set_clock(sdh, SDHC_FREQ); + } + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */ + { + return u32Status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if(pSD->CardType == SDH_TYPE_SD_LOW) + { + sdh->DMASA = (uint32_t) _SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 0x07UL; /* 64 bit */ + + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + if((u32Status = SDH_SDCmdAndRspDataIn(sdh, 51UL, 0x00UL)) != Successful) + { + return u32Status; + } + + /* set data bus width. ACMD6 for SD card, SDCR_DBW for host. */ + if((u32Status = SDH_SDCmdAndRsp(sdh, 55UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, 0x02UL, 0UL)) != Successful) /* set bus width */ + { + return u32Status; + } + + sdh->CTL |= SDH_CTL_DBW_Msk; + } + else if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + + if(pSD->CardType == SDH_TYPE_MMC) + { + sdh->CTL &= ~SDH_CTL_DBW_Msk; + } + + /* --- sent CMD6 to MMC card to set bus width to 4 bits mode */ + /* set CMD6 argument Access field to 3, Index to 183, Value to 1 (4-bit mode) */ + u32Param = (3UL << 24) | (183UL << 16) | (1UL << 8); + if((u32Status = SDH_SDCmdAndRsp(sdh, 6UL, u32Param, 0UL)) != Successful) + { + return u32Status; + } + SDH_CheckRB(sdh); + + sdh->CTL |= SDH_CTL_DBW_Msk; /* set bus width to 4-bit mode for SD host controller */ + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 16UL, SDH_BLOCK_SIZE, 0UL)) != Successful) /* set block length */ + { + return u32Status; + } + sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */ + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + sdh->INTEN |= SDH_INTEN_BLKDIEN_Msk; + + return Successful; +} + +void SDH_Get_SD_info(SDH_T *sdh) +{ + uint32_t u32RLen, u32CSize, u32Mult, u32Size; + uint32_t au32Buffer[4]; + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + SDH_SDCmdAndRsp2(sdh, 9UL, pSD->RCA, au32Buffer); + + if((pSD->CardType == SDH_TYPE_MMC) || (pSD->CardType == SDH_TYPE_EMMC)) + { + /* for MMC/eMMC card */ + if((au32Buffer[0] & 0xc0000000UL) == 0xc0000000UL) + { + /* CSD_STRUCTURE [127:126] is 3 */ + /* CSD version depend on EXT_CSD register in eMMC v4.4 for card size > 2GB */ + SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL); + + sdh->DMASA = (uint32_t)_SDH_ucSDHCBuffer; /* set DMA transfer starting address */ + sdh->BLEN = 511UL; /* read 512 bytes for EXT_CSD */ + + if(SDH_SDCmdAndRspDataIn(sdh, 8UL, 0x00UL) != Successful) + { + return; + } + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + pSD->totalSectorN = (uint32_t)_SDH_ucSDHCBuffer[215] << 24; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[214] << 16; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[213] << 8; + pSD->totalSectorN |= (uint32_t)_SDH_ucSDHCBuffer[212]; + pSD->diskSize = pSD->totalSectorN / 2UL; + } + else + { + /* CSD version v1.0/1.1/1.2 in eMMC v4.4 spec for card size <= 2GB */ + u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16; + u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30); + u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15; + u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen); + + pSD->diskSize = u32Size / 1024UL; + pSD->totalSectorN = u32Size / 512UL; + } + } + else + { + if(au32Buffer[0] & 0xc0000000UL) + { + u32CSize = ((au32Buffer[1] & 0x0000003fUL) << 16) | ((au32Buffer[2] & 0xffff0000UL) >> 16); + u32Size = (u32CSize + 1UL) * 512UL; /* Kbytes */ + + pSD->diskSize = u32Size; + pSD->totalSectorN = u32Size << 1; + } + else + { + u32RLen = (au32Buffer[1] & 0x000f0000UL) >> 16; + u32CSize = ((au32Buffer[1] & 0x000003ffUL) << 2) | ((au32Buffer[2] & 0xc0000000UL) >> 30); + u32Mult = (au32Buffer[2] & 0x00038000UL) >> 15; + u32Size = (u32CSize + 1UL) * (1UL << (u32Mult + 2UL)) * (1UL << u32RLen); + + pSD->diskSize = u32Size / 1024UL; + pSD->totalSectorN = u32Size / 512UL; + } + } + pSD->sectorSize = (int)512UL; +} + +/** @endcond HIDDEN_SYMBOLS */ + + +/** + * @brief This function use to reset SD function and select card detection source and pin. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] u32CardDetSrc Select card detection pin from GPIO or DAT3 pin. ( \ref CardDetect_From_GPIO / \ref CardDetect_From_DAT3) + * + * @return None + */ +void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc) +{ + /* enable DMAC */ + sdh->DMACTL = SDH_DMACTL_DMARST_Msk; + while(sdh->DMACTL & SDH_DMACTL_DMARST_Msk) {} + + sdh->DMACTL = SDH_DMACTL_DMAEN_Msk; + + /* Reset FMI */ + sdh->GCTL = SDH_GCTL_GCTLRST_Msk | SDH_GCTL_SDEN_Msk; /* Start reset FMI controller. */ + while(sdh->GCTL & SDH_GCTL_GCTLRST_Msk) {} + + memset(&SD0, 0, sizeof(SDH_INFO_T)); + + /* enable SD */ + sdh->GCTL = SDH_GCTL_SDEN_Msk; + + if(u32CardDetSrc & CardDetect_From_DAT3) + { + sdh->INTEN &= ~SDH_INTEN_CDSRC_Msk; + } + else + { + sdh->INTEN |= SDH_INTEN_CDSRC_Msk; + } + sdh->INTEN |= SDH_INTEN_CDIEN_Msk; + + sdh->CTL |= SDH_CTL_CTLRST_Msk; /* SD software reset */ + while(sdh->CTL & SDH_CTL_CTLRST_Msk) {} + +} + +/** + * @brief This function use to initial SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * + * @return None + * + * @details This function is used to initial SD card. + * SD initial state needs 400KHz clock output, driver will use HIRC for SD initial clock source. + * And then switch back to the user's setting. + */ +uint32_t SDH_Probe(SDH_T *sdh) +{ + uint32_t u32Val; + + /* Disable FMI/SD host interrupt */ + sdh->GINTEN = 0UL; + + sdh->CTL &= ~SDH_CTL_SDNWR_Msk; + sdh->CTL |= 0x09UL << SDH_CTL_SDNWR_Pos; /* set SDNWR = 9 */ + sdh->CTL &= ~SDH_CTL_BLKCNT_Msk; + sdh->CTL |= 0x01UL << SDH_CTL_BLKCNT_Pos; /* set BLKCNT = 1 */ + sdh->CTL &= ~SDH_CTL_DBW_Msk; /* SD 1-bit data bus */ + + if(!(SDH_CardDetection(sdh))) + { + return SDH_NO_SD_CARD; + } + + if((u32Val = SDH_Init(sdh)) != 0UL) + { + return u32Val; + } + + /* divider */ + if(SD0.CardType == SDH_TYPE_MMC) + { + SDH_Set_clock(sdh, MMC_FREQ); + } + else + { + SDH_Set_clock(sdh, SD_FREQ); + } + SDH_Get_SD_info(sdh); + + if((u32Val = SDH_SelectCardType(sdh)) != 0UL) + { + return u32Val; + } + + SDH_ok = 1; + return 0UL; +} + +/** + * @brief This function use to read data from SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[out] pu8BufAddr The buffer to receive the data from SD card. + * @param[in] u32StartSec The start read sector address. + * @param[in] u32SecCount The the read sector number of data + * + * @return None + */ +uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile u32IsSendCmd = (uint32_t)FALSE; + uint32_t volatile u32Reg; + uint32_t volatile u32Loop, u32Status; + uint32_t u32BlkSize = SDH_BLOCK_SIZE; + + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + /* --- check input parameters */ + if(u32SecCount == 0UL) + { + return SDH_SELECT_ERROR; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + SDH_CheckRB(sdh); + + sdh->BLEN = u32BlkSize - 1UL; /* the actual byte count is equal to (SDBLEN+1) */ + + if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * u32BlkSize; + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + + u32Loop = u32SecCount / 255UL; + while(u32Loop > 0UL) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & ~SDH_CTL_CMDCODE_Msk; + u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 255 */ + if(u32IsSendCmd == (uint32_t)FALSE) + { + sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(g_u8SDDataReadyFlag) + { + break; + } + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + u32Loop--; + } + + u32Loop = u32SecCount % 255UL; + if(u32Loop != 0UL) + { + uint32_t u32RegTmp; + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & (~SDH_CTL_CMDCODE_Msk); + u32Reg = u32Reg & (~SDH_CTL_BLKCNT_Msk); + u32RegTmp = (u32Loop << 16); + u32Reg |= u32RegTmp; /* setup SDCR_BLKCNT */ + + if(u32IsSendCmd == (uint32_t)FALSE) + { + sdh->CTL = u32Reg | (18UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DIEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DIEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC7_Msk)) /* check CRC7 */ + { + return SDH_CRC7_ERROR; + } + + if(!(sdh->INTSTS & SDH_INTSTS_CRC16_Msk)) /* check CRC16 */ + { + return SDH_CRC16_ERROR; + } + } + + if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + return Successful; +} + +/** + * @brief This function use to write data to SD card. + * + * @param[in] sdh The pointer of the specified SDH module. + * @param[in] pu8BufAddr The buffer to send the data to SD card. + * @param[in] u32StartSec The start write sector address. + * @param[in] u32SecCount The the write sector number of data. + * + * @return \ref SDH_SELECT_ERROR : u32SecCount is zero. \n + * \ref SDH_NO_SD_CARD : SD card be removed. \n + * \ref SDH_CRC_ERROR : CRC error happen. \n + * \ref SDH_CRC7_ERROR : CRC7 error happen. \n + * \ref Successful : Write data to SD card success. + */ +uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount) +{ + uint32_t volatile u32IsSendCmd = (uint32_t)FALSE; + uint32_t volatile u32Reg; + uint32_t volatile u32Loop, u32Status; + + SDH_INFO_T *pSD; + + /* M2351 is only support SDH0 */ + pSD = &SD0; + + /* --- check input parameters */ + if(u32SecCount == 0UL) + { + return SDH_SELECT_ERROR; + } + + if((u32Status = SDH_SDCmdAndRsp(sdh, 7UL, pSD->RCA, 0UL)) != Successful) + { + return u32Status; + } + + SDH_CheckRB(sdh); + + /* According to SD Spec v2.0, the write CMD block size MUST be 512, and the start address MUST be 512*n. */ + sdh->BLEN = SDH_BLOCK_SIZE - 1UL; /* set the block size */ + + if((pSD->CardType == SDH_TYPE_SD_HIGH) || (pSD->CardType == SDH_TYPE_EMMC)) + { + sdh->CMDARG = u32StartSec; + } + else + { + sdh->CMDARG = u32StartSec * SDH_BLOCK_SIZE; /* set start address for SD CMD */ + } + + sdh->DMASA = (uint32_t)pu8BufAddr; + u32Loop = u32SecCount / 255UL; /* the maximum block count is 0xFF=255 for register SDCR[BLK_CNT] */ + while(u32Loop > 0UL) + { + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32Reg = sdh->CTL & 0xff00c080UL; + u32Reg = u32Reg | 0xff0000UL; /* set BLK_CNT to 0xFF=255 */ + if(!u32IsSendCmd) + { + sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */ + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + u32Loop--; + } + + u32Loop = u32SecCount % 255UL; + if(u32Loop != 0UL) + { + uint32_t u32RegTmp; + g_u8SDDataReadyFlag = (uint8_t)FALSE; + u32RegTmp = (u32Loop << 16); + u32Reg = (sdh->CTL & 0xff00c080UL) | u32RegTmp; + if(!u32IsSendCmd) + { + sdh->CTL = u32Reg | (25UL << 8) | (SDH_CTL_COEN_Msk | SDH_CTL_RIEN_Msk | SDH_CTL_DOEN_Msk); + u32IsSendCmd = (uint32_t)TRUE; + } + else + { + sdh->CTL = u32Reg | SDH_CTL_DOEN_Msk; + } + + while(!g_u8SDDataReadyFlag) + { + if(pSD->IsCardInsert == (uint8_t)FALSE) + { + return SDH_NO_SD_CARD; + } + } + + if((sdh->INTSTS & SDH_INTSTS_CRCIF_Msk) != 0UL) /* check CRC */ + { + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + return SDH_CRC_ERROR; + } + } + sdh->INTSTS = SDH_INTSTS_CRCIF_Msk; + + if(SDH_SDCmdAndRsp(sdh, 12UL, 0UL, 0UL)) /* stop command */ + { + return SDH_CRC7_ERROR; + } + SDH_CheckRB(sdh); + + SDH_SDCommand(sdh, 7UL, 0UL); + sdh->CTL |= SDH_CTL_CLK8OEN_Msk; + while(sdh->CTL & SDH_CTL_CLK8OEN_Msk) {} + + return Successful; +} + + +/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SDH_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/spi.c b/arch/riscv32/fe310/src/StdDriver/src/spi.c new file mode 100644 index 00000000..4a8435ee --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/spi.c @@ -0,0 +1,1600 @@ +/**************************************************************************//** + * @file spi.c + * @version V3.00 + * @brief M2351 series SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SPI_Driver SPI Driver + @{ +*/ + + +/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions + @{ +*/ + +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s); + +/** + * @brief This function make SPI module be ready to transfer. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32MasterSlave Decides the SPI module is operating in master mode or in slave mode. (SPI_SLAVE, SPI_MASTER) + * @param[in] u32SPIMode Decides the transfer timing. (SPI_MODE_0, SPI_MODE_1, SPI_MODE_2, SPI_MODE_3) + * @param[in] u32DataWidth Decides the data width of a SPI transaction. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI peripheral clock. + * @details By default, the SPI transfer sequence is MSB first, the slave selection signal is active low and the automatic + * slave selection function is disabled. + * In Slave mode, the u32BusClock shall be NULL and the SPI clock divider setting will be 0. + * The actual clock rate may be different from the target SPI clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the + * actual SPI clock rate will be 6MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * SPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t SPI_Open(SPI_T *spi, + uint32_t u32MasterSlave, + uint32_t u32SPIMode, + uint32_t u32DataWidth, + uint32_t u32BusClock) +{ + uint32_t u32ClkSrc = 0UL, u32Div, u32HCLKFreq, u32PCLK0Freq, u32PCLK1Freq, u32RetValue = 0UL; + + /* Disable I2S mode */ + spi->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; + + if(u32DataWidth == 32UL) + { + u32DataWidth = 0UL; + } + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + /* Get APB1 clock frequency */ + u32PCLK1Freq = CLK_GetPCLK1Freq(); + + if(u32MasterSlave == SPI_MASTER) + { + /* Default setting: slave selection signal is active low; disable automatic slave selection function. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + } + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + } + else /* For slave mode, force the SPI peripheral clock rate to equal APB clock rate. */ + { + /* Default setting: slave selection signal is low level active. */ + spi->SSCTL = SPI_SS_ACTIVE_LOW; + + /* Default setting: MSB first, disable unit transfer interrupt, SP_CYCLE = 0. */ + spi->CTL = u32MasterSlave | (u32DataWidth << SPI_CTL_DWIDTH_Pos) | (u32SPIMode) | SPI_CTL_SPIEN_Msk; + + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + } + else + { + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32RetValue = u32PCLK1Freq; /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32RetValue = u32PCLK0Freq; /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + } + } + + return u32RetValue; +} + +/** + * @brief Disable SPI controller. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details Clear SPIEN bit of SPI_CTL register to disable SPI transfer control. + */ +void SPI_Close(SPI_T *spi) +{ + spi->CTL &= ~SPI_CTL_SPIEN_Msk; +} + +/** + * @brief Clear RX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI RX FIFO buffer. The RXEMPTY (SPI_STATUS[8]) will be set to 1. + */ +void SPI_ClearRxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk; +} + +/** + * @brief Clear TX FIFO buffer. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will clear SPI TX FIFO buffer. The TXEMPTY (SPI_STATUS[16]) will be set to 1. + * @note The TX shift register will not be cleared. + */ +void SPI_ClearTxFIFO(SPI_T *spi) +{ + spi->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk; +} + +/** + * @brief Disable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @return None + * @details This function will disable the automatic slave selection function and set slave selection signal to inactive state. + */ +void SPI_DisableAutoSS(SPI_T *spi) +{ + spi->SSCTL &= ~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave selection function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32SSPinMask Specifies slave selection pins. (SPI_SS) + * @param[in] u32ActiveLevel Specifies the active level of slave selection signal. (SPI_SS_ACTIVE_HIGH, SPI_SS_ACTIVE_LOW) + * @return None + * @details This function will enable the automatic slave selection function. Only available in Master mode. + * The slave selection pin and the active level will be set in this function. + */ +void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + spi->SSCTL = (spi->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))) | (u32SSPinMask | u32ActiveLevel | SPI_SSCTL_AUTOSS_Msk); +} + +/** + * @brief Set the SPI bus clock. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32BusClock The expected frequency of SPI bus clock in Hz. + * @return Actual frequency of SPI bus clock. + * @details This function is only available in Master mode. The actual clock rate may be different from the target SPI bus clock rate. + * For example, if the SPI source clock rate is 12 MHz and the target SPI bus clock rate is 7 MHz, the actual SPI bus clock + * rate will be 6 MHz. + * @note If u32BusClock = 0, DIVIDER setting will be set to the maximum value. + * @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0. + * @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of + * SPI bus clock cannot be faster than the system clock rate. User should set up carefully. + * @note If u32BusClock >= SPI peripheral clock source, DIVIDER will be set to 0. + */ +uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock) +{ + uint32_t u32ClkSrc, u32HCLKFreq; + uint32_t u32Div, u32RetValue; + + /* Get system clock frequency */ + u32HCLKFreq = CLK_GetHCLKFreq(); + + if(u32BusClock >= u32HCLKFreq) + { + if(!(__PC() & NS_OFFSET)) + { + /* Select PCLK as the clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + } + else + { + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + } + } + } + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + if(u32BusClock >= u32HCLKFreq) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock >= u32ClkSrc) + { + /* Set DIVIDER = 0 */ + spi->CLKDIV = 0UL; + /* Return master peripheral clock rate */ + u32RetValue = u32ClkSrc; + } + else if(u32BusClock == 0UL) + { + /* Set DIVIDER to the maximum value 0x1FF. f_spi = f_spi_clk_src / (DIVIDER + 1) */ + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + if(u32Div > 0x1FFUL) + { + u32Div = 0x1FFUL; + spi->CLKDIV |= SPI_CLKDIV_DIVIDER_Msk; + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (0x1FFUL + 1UL)); + } + else + { + spi->CLKDIV = (spi->CLKDIV & (~SPI_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI_CLKDIV_DIVIDER_Pos); + /* Return master peripheral clock rate */ + u32RetValue = (u32ClkSrc / (u32Div + 1UL)); + } + } + + return u32RetValue; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + spi->FIFOCTL = (spi->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/** + * @brief Get the actual frequency of SPI bus clock. Only available in Master mode. + * @param[in] spi The pointer of the specified SPI module. + * @return Actual SPI bus clock frequency in Hz. + * @details This function will calculate the actual SPI bus clock rate according to the SPIxSEL and DIVIDER settings. Only available in Master mode. + */ +uint32_t SPI_GetBusClock(SPI_T *spi) +{ + uint32_t u32Div; + uint32_t u32ClkSrc; + + /* Get DIVIDER setting */ + u32Div = (spi->CLKDIV & SPI_CLKDIV_DIVIDER_Msk) >> SPI_CLKDIV_DIVIDER_Pos; + + /* Check clock source of SPI */ + if((spi == SPI0) || (spi == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI1) || (spi == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else if((spi == SPI2) || (spi == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32ClkSrc = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32ClkSrc = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32ClkSrc = __HIRC; /* Clock source is HIRC */ + } + } + + /* Return SPI bus clock rate */ + return (u32ClkSrc / (u32Div + 1UL)); +} + +/** + * @brief Enable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Enable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Enable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL |= SPI_CTL_UNITIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSACTIEN_Msk; + } + + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SSINAIEN_Msk; + } + + /* Enable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVURIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL |= SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Enable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Disable SPI related interrupts specified by u32Mask parameter. + */ +void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask) +{ + /* Disable unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) == SPI_UNIT_INT_MASK) + { + spi->CTL &= ~SPI_CTL_UNITIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) == SPI_SSACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSACTIEN_Msk; + } + + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) == SPI_SSINACT_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SSINAIEN_Msk; + } + + /* Disable slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) == SPI_SLVUR_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVURIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) == SPI_SLVBE_INT_MASK) + { + spi->SSCTL &= ~SPI_SSCTL_SLVBEIEN_Msk; + } + + /* Disable slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) == SPI_TXUF_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) == SPI_FIFO_TXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) == SPI_FIFO_RXTH_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) == SPI_FIFO_RXOV_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) == SPI_FIFO_RXTO_INT_MASK) + { + spi->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_TXTH_INT_MASK + * - \ref SPI_FIFO_RXTH_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return Interrupt flags of selected sources. + * @details Get SPI related interrupt flags specified by u32Mask parameter. + */ +uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32IntStatus; + uint32_t u32IntFlag = 0UL; + + u32IntStatus = spi->STATUS; + + /* Check unit transfer interrupt flag */ + if((u32Mask & SPI_UNIT_INT_MASK) && (u32IntStatus & SPI_STATUS_UNITIF_Msk)) + { + u32IntFlag |= SPI_UNIT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & SPI_SSACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSACTIF_Msk)) + { + u32IntFlag |= SPI_SSACT_INT_MASK; + } + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & SPI_SSINACT_INT_MASK) && (u32IntStatus & SPI_STATUS_SSINAIF_Msk)) + { + u32IntFlag |= SPI_SSINACT_INT_MASK; + } + + /* Check slave TX under run interrupt flag */ + if((u32Mask & SPI_SLVUR_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVURIF_Msk)) + { + u32IntFlag |= SPI_SLVUR_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & SPI_SLVBE_INT_MASK) && (u32IntStatus & SPI_STATUS_SLVBEIF_Msk)) + { + u32IntFlag |= SPI_SLVBE_INT_MASK; + } + + /* Check slave TX underflow interrupt flag */ + if((u32Mask & SPI_TXUF_INT_MASK) && (u32IntStatus & SPI_STATUS_TXUFIF_Msk)) + { + u32IntFlag |= SPI_TXUF_INT_MASK; + } + + /* Check TX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_TXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_TXTHIF_Msk)) + { + u32IntFlag |= SPI_FIFO_TXTH_INT_MASK; + } + + /* Check RX threshold interrupt flag */ + if((u32Mask & SPI_FIFO_RXTH_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTHIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXTH_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & SPI_FIFO_RXOV_INT_MASK) && (u32IntStatus & SPI_STATUS_RXOVIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXOV_INT_MASK; + } + + /* Check RX time-out interrupt flag */ + if((u32Mask & SPI_FIFO_RXTO_INT_MASK) && (u32IntStatus & SPI_STATUS_RXTOIF_Msk)) + { + u32IntFlag |= SPI_FIFO_RXTO_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref SPI_UNIT_INT_MASK + * - \ref SPI_SSACT_INT_MASK + * - \ref SPI_SSINACT_INT_MASK + * - \ref SPI_SLVUR_INT_MASK + * - \ref SPI_SLVBE_INT_MASK + * - \ref SPI_TXUF_INT_MASK + * - \ref SPI_FIFO_RXOV_INT_MASK + * - \ref SPI_FIFO_RXTO_INT_MASK + * + * @return None + * @details Clear SPI related interrupt flags specified by u32Mask parameter. + */ +void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask) +{ + if(u32Mask & SPI_UNIT_INT_MASK) + { + spi->STATUS = SPI_STATUS_UNITIF_Msk; /* Clear unit transfer interrupt flag */ + } + + if(u32Mask & SPI_SSACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSACTIF_Msk; /* Clear slave selection signal active interrupt flag */ + } + + if(u32Mask & SPI_SSINACT_INT_MASK) + { + spi->STATUS = SPI_STATUS_SSINAIF_Msk; /* Clear slave selection signal inactive interrupt flag */ + } + + if(u32Mask & SPI_SLVUR_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVURIF_Msk; /* Clear slave TX under run interrupt flag */ + } + + if(u32Mask & SPI_SLVBE_INT_MASK) + { + spi->STATUS = SPI_STATUS_SLVBEIF_Msk; /* Clear slave bit count error interrupt flag */ + } + + if(u32Mask & SPI_TXUF_INT_MASK) + { + spi->STATUS = SPI_STATUS_TXUFIF_Msk; /* Clear slave TX underflow interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXOV_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXOVIF_Msk; /* Clear RX overrun interrupt flag */ + } + + if(u32Mask & SPI_FIFO_RXTO_INT_MASK) + { + spi->STATUS = SPI_STATUS_RXTOIF_Msk; /* Clear RX time-out interrupt flag */ + } +} + +/** + * @brief Get SPI status. + * @param[in] spi The pointer of the specified SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref SPI_BUSY_MASK + * - \ref SPI_RX_EMPTY_MASK + * - \ref SPI_RX_FULL_MASK + * - \ref SPI_TX_EMPTY_MASK + * - \ref SPI_TX_FULL_MASK + * - \ref SPI_TXRX_RESET_MASK + * - \ref SPI_SPIEN_STS_MASK + * - \ref SPI_SSLINE_STS_MASK + * + * @return Flags of selected sources. + * @details Get SPI related status specified by u32Mask parameter. + */ +uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask) +{ + uint32_t u32TmpStatus; + uint32_t u32Flag = 0UL; + + u32TmpStatus = spi->STATUS; + + /* Check busy status */ + if((u32Mask & SPI_BUSY_MASK) && (u32TmpStatus & SPI_STATUS_BUSY_Msk)) + { + u32Flag |= SPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & SPI_RX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_RXEMPTY_Msk)) + { + u32Flag |= SPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & SPI_RX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_RXFULL_Msk)) + { + u32Flag |= SPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & SPI_TX_EMPTY_MASK) && (u32TmpStatus & SPI_STATUS_TXEMPTY_Msk)) + { + u32Flag |= SPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & SPI_TX_FULL_MASK) && (u32TmpStatus & SPI_STATUS_TXFULL_Msk)) + { + u32Flag |= SPI_TX_FULL_MASK; + } + + /* Check TX/RX reset flag */ + if((u32Mask & SPI_TXRX_RESET_MASK) && (u32TmpStatus & SPI_STATUS_TXRXRST_Msk)) + { + u32Flag |= SPI_TXRX_RESET_MASK; + } + + /* Check SPIEN flag */ + if((u32Mask & SPI_SPIEN_STS_MASK) && (u32TmpStatus & SPI_STATUS_SPIENSTS_Msk)) + { + u32Flag |= SPI_SPIEN_STS_MASK; + } + + /* Check SPIx_SS line status */ + if((u32Mask & SPI_SSLINE_STS_MASK) && (u32TmpStatus & SPI_STATUS_SSLINE_Msk)) + { + u32Flag |= SPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + + +/** + * @brief This function is used to get I2S source clock frequency. + * @param[in] i2s The pointer of the specified I2S module. + * @return I2S source clock frequency (Hz). + * @details Return the source clock frequency according to the setting of SPI0SEL (CLK_CLKSEL2[5:4]) or SPI1SEL (CLK_CLKSEL2[7:6]) or SPI2SEL (CLK_CLKSEL2[11:10]) or SPI3SEL (CLK_CLKSEL2[13:12]). + */ +static uint32_t SPII2S_GetSourceClockFreq(SPI_T *i2s) +{ + uint32_t u32Freq; + + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32Freq = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + else + { + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32Freq = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32Freq = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32Freq = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32Freq = __HIRC; /* Clock source is HIRC */ + } + } + + return u32Freq; +} + +/** + * @brief This function configures some parameters of I2S interface for general purpose use. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32MasterSlave I2S operation mode. Valid values are listed below. + * - \ref SPII2S_MODE_MASTER + * - \ref SPII2S_MODE_SLAVE + * @param[in] u32SampleRate Sample rate + * @param[in] u32WordWidth Data length. Valid values are listed below. + * - \ref SPII2S_DATABIT_8 + * - \ref SPII2S_DATABIT_16 + * - \ref SPII2S_DATABIT_24 + * - \ref SPII2S_DATABIT_32 + * @param[in] u32Channels Audio format. Valid values are listed below. + * - \ref SPII2S_MONO + * - \ref SPII2S_STEREO + * @param[in] u32DataFormat Data format. Valid values are listed below. + * - \ref SPII2S_FORMAT_I2S + * - \ref SPII2S_FORMAT_MSB + * - \ref SPII2S_FORMAT_PCMA + * - \ref SPII2S_FORMAT_PCMB + * @return Real sample rate of master mode or peripheral clock rate of slave mode. + * @details This function will reset SPI/I2S controller and configure I2S controller according to the input parameters. + * Set TX FIFO threshold to 2 and RX FIFO threshold to 1. Both the TX and RX functions will be enabled. + * The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference. + * @note In slave mode for Secure, the SPI peripheral clock rate will equal to APB clock rate. + * @note In slave mode for Non-Secure, the SPI peripheral clock rate will equal to the clock rate set in secure mode. + */ +uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat) +{ + uint32_t u32Divider; + uint32_t u32BitRate, u32SrcClk, u32RetValue; + uint32_t u32PCLK0Freq, u32PCLK1Freq; + + if(!(__PC() & NS_OFFSET)) + { + /* Reset SPI/I2S */ + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI0RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI0RST_Msk; + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI1RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI1RST_Msk; + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + SYS->IPRST1 |= SYS_IPRST1_SPI2RST_Msk; + SYS->IPRST1 &= ~SYS_IPRST1_SPI2RST_Msk; + } + else + { + SYS->IPRST2 |= SYS_IPRST2_SPI3RST_Msk; + SYS->IPRST2 &= ~SYS_IPRST2_SPI3RST_Msk; + } + } + + /* Configure I2S controller */ + i2s->I2SCTL = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat; + /* Set TX FIFO threshold to 2 and RX FIFO threshold to 1 */ + i2s->FIFOCTL = SPII2S_FIFO_TX_LEVEL_WORD_2 | SPII2S_FIFO_RX_LEVEL_WORD_2; + + if(u32MasterSlave == SPII2S_MODE_MASTER) + { + /* Get the source clock rate */ + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + + /* Calculate the bit clock rate */ + u32BitRate = u32SampleRate * ((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL; + u32Divider = (((((u32SrcClk * 10UL) / u32BitRate) >> 1UL) + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */ + /* Set BCLKDIV setting */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_BCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_BCLKDIV_Pos); + + /* Calculate bit clock rate */ + u32BitRate = u32SrcClk / ((u32Divider + 1UL) * 2UL); + /* Calculate real sample rate */ + u32SampleRate = u32BitRate / (((u32WordWidth >> SPI_I2SCTL_WDWIDTH_Pos) + 1UL) * 16UL); + + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + + /* Return the real sample rate */ + u32RetValue = u32SampleRate; + } + else + { + /* Set BCLKDIV = 0 */ + i2s->I2SCLK &= ~SPI_I2SCLK_BCLKDIV_Msk; + /* Get APB0 clock frequency */ + u32PCLK0Freq = CLK_GetPCLK0Freq(); + /* Get APB1 clock frequency */ + u32PCLK1Freq = CLK_GetPCLK1Freq(); + + if((i2s == SPI0) || (i2s == SPI0_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI0SEL_Msk)) | CLK_CLKSEL2_SPI0SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI0_MODULE) << CLK_CLKSEL2_SPI0SEL_Pos) == CLK_CLKSEL2_SPI0SEL_PCLK1) + { + u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else if((i2s == SPI1) || (i2s == SPI1_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI1SEL_Msk)) | CLK_CLKSEL2_SPI1SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI1_MODULE) << CLK_CLKSEL2_SPI1SEL_Pos) == CLK_CLKSEL2_SPI1SEL_PCLK0) + { + u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else if((i2s == SPI2) || (i2s == SPI2_NS)) + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI2SEL_Msk)) | CLK_CLKSEL2_SPI2SEL_PCLK1; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK1Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI2_MODULE) << CLK_CLKSEL2_SPI2SEL_Pos) == CLK_CLKSEL2_SPI2SEL_PCLK1) + { + u32RetValue = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + else + { + if(!(__PC() & NS_OFFSET)) + { + /* Set the peripheral clock rate to equal APB clock rate */ + CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI3SEL_Msk)) | CLK_CLKSEL2_SPI3SEL_PCLK0; + /* Return slave peripheral clock rate */ + u32RetValue = u32PCLK0Freq; + } + else + { + /* Check clock source of I2S */ + if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_HXT) + { + u32RetValue = __HXT; /* Clock source is HXT */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PLL) + { + u32RetValue = CLK_GetPLLClockFreq(); /* Clock source is PLL */ + } + else if((CLK_GetModuleClockSource(SPI3_MODULE) << CLK_CLKSEL2_SPI3SEL_Pos) == CLK_CLKSEL2_SPI3SEL_PCLK0) + { + u32RetValue = CLK_GetPCLK0Freq(); /* Clock source is PCLK0 */ + } + else + { + u32RetValue = __HIRC; /* Clock source is HIRC */ + } + } + /* Enable TX function, RX function and I2S mode. */ + i2s->I2SCTL |= (SPI_I2SCTL_RXEN_Msk | SPI_I2SCTL_TXEN_Msk | SPI_I2SCTL_I2SEN_Msk); + } + } + + return u32RetValue; +} + +/** + * @brief Disable I2S function. + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Disable I2S function. + */ +void SPII2S_Close(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_I2SEN_Msk; +} + +/** + * @brief Enable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function enables the interrupt according to the u32Mask parameter. + */ +void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Enable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Enable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Enable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Enable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL |= SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Enable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_RZCIEN_Msk; + } + + /* Enable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL |= SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Disable interrupt function. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt source. Valid values are listed below. + * - \ref SPII2S_FIFO_TXTH_INT_MASK + * - \ref SPII2S_FIFO_RXTH_INT_MASK + * - \ref SPII2S_FIFO_RXOV_INT_MASK + * - \ref SPII2S_FIFO_RXTO_INT_MASK + * - \ref SPII2S_TXUF_INT_MASK + * - \ref SPII2S_RIGHT_ZC_INT_MASK + * - \ref SPII2S_LEFT_ZC_INT_MASK + * @return None + * @details This function disables the interrupt according to the u32Mask parameter. + */ +void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask) +{ + /* Disable TX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_TXTH_INT_MASK) == SPII2S_FIFO_TXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXTHIEN_Msk; + } + + /* Disable RX threshold interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTH_INT_MASK) == SPII2S_FIFO_RXTH_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTHIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXOV_INT_MASK) == SPII2S_FIFO_RXOV_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXOVIEN_Msk; + } + + /* Disable RX time-out interrupt flag */ + if((u32Mask & SPII2S_FIFO_RXTO_INT_MASK) == SPII2S_FIFO_RXTO_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_RXTOIEN_Msk; + } + + /* Disable TX underflow interrupt flag */ + if((u32Mask & SPII2S_TXUF_INT_MASK) == SPII2S_TXUF_INT_MASK) + { + i2s->FIFOCTL &= ~SPI_FIFOCTL_TXUFIEN_Msk; + } + + /* Disable right channel zero cross interrupt flag */ + if((u32Mask & SPII2S_RIGHT_ZC_INT_MASK) == SPII2S_RIGHT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_RZCIEN_Msk; + } + + /* Disable left channel zero cross interrupt flag */ + if((u32Mask & SPII2S_LEFT_ZC_INT_MASK) == SPII2S_LEFT_ZC_INT_MASK) + { + i2s->I2SCTL &= ~SPI_I2SCTL_LZCIEN_Msk; + } +} + +/** + * @brief Enable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32BusClock The target MCLK clock rate. + * @return Actual MCLK clock rate + * @details Set the master clock rate according to u32BusClock parameter and enable master clock output. + * The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference. + */ +uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock) +{ + uint32_t u32Divider; + uint32_t u32SrcClk, u32RetValue; + + u32SrcClk = SPII2S_GetSourceClockFreq(i2s); + if(u32BusClock == u32SrcClk) + { + u32Divider = 0UL; + } + else + { + u32Divider = (u32SrcClk / u32BusClock) >> 1UL; + /* MCLKDIV is a 7-bit width configuration. The maximum value is 0x7F. */ + if(u32Divider > 0x7FUL) + { + u32Divider = 0x7FUL; + } + } + + /* Write u32Divider to MCLKDIV (SPI_I2SCLK[6:0]) */ + i2s->I2SCLK = (i2s->I2SCLK & ~SPI_I2SCLK_MCLKDIV_Msk) | (u32Divider << SPI_I2SCLK_MCLKDIV_Pos); + + /* Enable MCLK output */ + i2s->I2SCTL |= SPI_I2SCTL_MCLKEN_Msk; + + if(u32Divider == 0UL) + { + u32RetValue = u32SrcClk; /* If MCLKDIV=0, master clock rate is equal to the source clock rate. */ + } + else + { + u32RetValue = ((u32SrcClk >> 1UL) / u32Divider); /* If MCLKDIV>0, master clock rate = source clock rate / (MCLKDIV * 2) */ + } + + return u32RetValue; +} + +/** + * @brief Disable master clock (MCLK). + * @param[in] i2s The pointer of the specified I2S module. + * @return None + * @details Clear MCLKEN bit of SPI_I2SCTL register to disable master clock output. + */ +void SPII2S_DisableMCLK(SPI_T *i2s) +{ + i2s->I2SCTL &= ~SPI_I2SCTL_MCLKEN_Msk; +} + +/** + * @brief Configure FIFO threshold setting. + * @param[in] i2s The pointer of the specified I2S module. + * @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7. + * @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7. + * @return None + * @details Set TX FIFO threshold and RX FIFO threshold configurations. + */ +void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold) +{ + i2s->FIFOCTL = (i2s->FIFOCTL & ~(SPI_FIFOCTL_TXTH_Msk | SPI_FIFOCTL_RXTH_Msk)) | + (u32TxThreshold << SPI_FIFOCTL_TXTH_Pos) | + (u32RxThreshold << SPI_FIFOCTL_RXTH_Pos); +} + +/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/sys.c b/arch/riscv32/fe310/src/StdDriver/src/sys.c new file mode 100644 index 00000000..45ff0cb8 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/sys.c @@ -0,0 +1,389 @@ +/**************************************************************************//** + * @file sys.c + * @version V3.00 + * @brief M2351 series System Manager (SYS) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup SYS_Driver SYS Driver + @{ +*/ + + +/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions + @{ +*/ + +/** + * @brief Clear reset source + * @param[in] u32Src is system reset source. Including : + * - \ref SYS_RSTSTS_CPULKRF_Msk + * - \ref SYS_RSTSTS_CPURF_Msk + * - \ref SYS_RSTSTS_SYSRF_Msk + * - \ref SYS_RSTSTS_BODRF_Msk + * - \ref SYS_RSTSTS_LVRF_Msk + * - \ref SYS_RSTSTS_WDTRF_Msk + * - \ref SYS_RSTSTS_PINRF_Msk + * - \ref SYS_RSTSTS_PORF_Msk + * @return None + * @details This function clear the selected system reset source. + */ +void SYS_ClearResetSrc(uint32_t u32Src) +{ + SYS->RSTSTS = u32Src; +} + +/** + * @brief Get Brown-out detector output status + * @param None + * @retval 0 System voltage is higher than BODVL setting or BODEN is 0. + * @retval 1 System voltage is lower than BODVL setting. + * @details This function get Brown-out detector output status. + */ +uint32_t SYS_GetBODStatus(void) +{ + return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos); +} + +/** + * @brief Get reset status register value + * @param None + * @return Reset source + * @details This function get the system reset status register value. + */ +uint32_t SYS_GetResetSrc(void) +{ + return (SYS->RSTSTS); +} + +/** + * @brief Check if register is locked nor not + * @param None + * @retval 0 Write-protection function is disabled. + * 1 Write-protection function is enabled. + * @details This function check register write-protection bit setting. + */ +uint32_t SYS_IsRegLocked(void) +{ + return SYS->REGLCTL & 1UL ? 0UL : 1UL; +} + +/** + * @brief Get product ID + * @param None + * @return Product ID + * @details This function get product ID. + */ +uint32_t SYS_ReadPDID(void) +{ + return SYS->PDID; +} + +/** + * @brief Reset chip with chip reset + * @param None + * @return None + * @details This function reset chip with chip reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetChip(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk; +} + +/** + * @brief Reset chip with CPU reset + * @param None + * @return None + * @details This function reset CPU with CPU reset. + * The register write-protection function should be disabled before using this function. + */ +void SYS_ResetCPU(void) +{ + SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk; +} + +/** + * @brief Reset selected module + * @param[in] u32ModuleIndex is module index. Including : + * - \ref PDMA0_RST + * - \ref PDMA1_RST + * - \ref EBI_RST + * - \ref USBH_RST + * - \ref SDH0_RST + * - \ref CRC_RST + * - \ref CRPT_RST + * - \ref GPIO_RST + * - \ref TMR0_RST + * - \ref TMR1_RST + * - \ref TMR2_RST + * - \ref TMR3_RST + * - \ref ACMP01_RST + * - \ref I2C0_RST + * - \ref I2C1_RST + * - \ref I2C2_RST + * - \ref QSPI0_RST + * - \ref SPI0_RST + * - \ref SPI1_RST + * - \ref SPI2_RST + * - \ref SPI3_RST + * - \ref UART0_RST + * - \ref UART1_RST + * - \ref UART2_RST + * - \ref UART3_RST + * - \ref UART4_RST + * - \ref UART5_RST + * - \ref CAN0_RST + * - \ref OTG_RST + * - \ref USBD_RST + * - \ref EADC_RST + * - \ref I2S0_RST + * - \ref TRNG_RST + * - \ref SC0_RST + * - \ref SC1_RST + * - \ref SC2_RST + * - \ref USCI0_RST + * - \ref USCI1_RST + * - \ref DAC_RST + * - \ref EPWM0_RST + * - \ref EPWM1_RST + * - \ref BPWM0_RST + * - \ref BPWM1_RST + * - \ref QEI0_RST + * - \ref QEI1_RST + * - \ref ECAP0_RST + * - \ref ECAP1_RST + * @return None + * @details This function reset selected module. + */ +void SYS_ResetModule(uint32_t u32ModuleIndex) +{ + uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL; + + /* Generate reset signal to the corresponding module */ + u32TmpVal = (1UL << (u32ModuleIndex & 0x00ffffffUL)); + u32TmpAddr = (uint32_t)&SYS->IPRST0 + ((u32ModuleIndex >> 24UL)); + *(uint32_t *)u32TmpAddr |= u32TmpVal; + + /* Release corresponding module from reset state */ + u32TmpVal = ~(1UL << (u32ModuleIndex & 0x00ffffffUL)); + *(uint32_t *)u32TmpAddr &= u32TmpVal; +} + +/** + * @brief Enable and configure Brown-out detector function + * @param[in] i32Mode is reset or interrupt mode. Including : + * - \ref SYS_BODCTL_BOD_RST_EN + * - \ref SYS_BODCTL_BOD_INTERRUPT_EN + * @param[in] u32BODLevel is Brown-out voltage level. Including : + * - \ref SYS_BODCTL_BODVL_1_6V + * - \ref SYS_BODCTL_BODVL_1_8V + * - \ref SYS_BODCTL_BODVL_2_0V + * - \ref SYS_BODCTL_BODVL_2_2V + * - \ref SYS_BODCTL_BODVL_2_4V + * - \ref SYS_BODCTL_BODVL_2_6V + * - \ref SYS_BODCTL_BODVL_2_8V + * - \ref SYS_BODCTL_BODVL_3_0V + * @return None + * @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel) +{ + /* Enable Brown-out Detector function */ + SYS->BODCTL |= SYS_BODCTL_BODEN_Msk; + + /* Enable Brown-out interrupt or reset function */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | (uint32_t)i32Mode; + + /* Select Brown-out Detector threshold voltage */ + SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel; +} + +/** + * @brief Disable Brown-out detector function + * @param None + * @return None + * @details This function disable Brown-out detector function. + * The register write-protection function should be disabled before using this function. + */ +void SYS_DisableBOD(void) +{ + SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk; +} + + +/** + * @brief Set Power Level + * @param[in] u32PowerLevel is power level setting. Including : + * - \ref SYS_PLCTL_PLSEL_PL0 + * - \ref SYS_PLCTL_PLSEL_PL1 + * @return None + * @details This function select power level. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPowerLevel(uint32_t u32PowerLevel) +{ + /* Set power voltage level */ + SYS->PLCTL = (SYS->PLCTL & (~SYS_PLCTL_PLSEL_Msk)) | (u32PowerLevel); +} + + +/** + * @brief Set Main Voltage Regulator Type + * @param[in] u32PowerRegulator is main voltage regulator type. Including : + * - \ref SYS_PLCTL_MVRS_LDO + * - \ref SYS_PLCTL_MVRS_DCDC + * @retval 0 main voltage regulator type setting is not finished + * @retval 1 main voltage regulator type setting is finished + * @details This function set main voltage regulator type. + * The main voltage regulator type setting to DCDC cannot finished if the inductor is not detected. + * The register write-protection function should be disabled before using this function. + */ +uint32_t SYS_SetPowerRegulator(uint32_t u32PowerRegulator) +{ + int32_t i32TimeOutCnt = 400; + uint32_t u32Ret = 1U; + uint32_t u32PowerRegStatus; + + /* Get main voltage regulator type status */ + u32PowerRegStatus = SYS->PLSTS & SYS_PLSTS_CURMVR_Msk; + + /* Set main voltage regulator type */ + if((u32PowerRegulator == SYS_PLCTL_MVRS_DCDC) && (u32PowerRegStatus == SYS_PLSTS_CURMVR_LDO)) + { + + /* Set main voltage regulator type to DCDC if status is LDO */ + SYS->PLCTL |= SYS_PLCTL_MVRS_Msk; + + /* Wait induction detection and main voltage regulator type change ready */ + while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_DCDC) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; /* Main voltage regulator type change time-out */ + break; + } + } + + } + else if(u32PowerRegulator == SYS_PLCTL_MVRS_LDO) + { + + /* Set main voltage regulator type to LDO if status is DCDC */ + SYS->PLCTL &= (~SYS_PLCTL_MVRS_Msk); + + /* Wait main voltage regulator type change ready */ + while((SYS->PLSTS & SYS_PLSTS_CURMVR_Msk) != SYS_PLSTS_CURMVR_LDO) + { + if(i32TimeOutCnt-- <= 0) + { + u32Ret = 0U; /* Main voltage regulator type change time-out */ + break; + } + } + + } + + /* Clear main voltage regulator type change error flag */ + if(SYS->PLSTS & SYS_PLSTS_MVRCERR_Msk) + { + SYS->PLSTS = SYS_PLSTS_MVRCERR_Msk; + u32Ret = 0U; + } + + return u32Ret; +} + +/** + * @brief Set System SRAM Power Mode + * @param[in] u32SRAMSel is SRAM region selection. Including : + * - \ref SYS_SRAMPCTL_SRAM0PM0_Msk + * - \ref SYS_SRAMPCTL_SRAM0PM1_Msk + * - \ref SYS_SRAMPCTL_SRAM0PM2_Msk + * - \ref SYS_SRAMPCTL_SRAM0PM3_Msk + * - \ref SYS_SRAMPCTL_SRAM1PM0_Msk + * - \ref SYS_SRAMPCTL_SRAM1PM1_Msk + * - \ref SYS_SRAMPCTL_SRAM1PM2_Msk + * - \ref SYS_SRAMPCTL_SRAM1PM3_Msk + * @param[in] u32PowerMode is SRAM power mode. Including : + * - \ref SYS_SRAMPCTL_SRAM_NORMAL + * - \ref SYS_SRAMPCTL_SRAM_RETENTION + * - \ref SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN + * @return None + * @details This function set system SRAM power mode. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetSSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode) +{ + uint32_t u32SRAMSelPos = 8UL; + + /* Get system SRAM power mode setting position */ + while(u32SRAMSelPos < 24UL) + { + if(u32SRAMSel & (1 << u32SRAMSelPos)) + { + break; + } + else + { + u32SRAMSelPos++; + } + } + + /* Set system SRAM power mode setting */ + SYS->SRAMPCTL = (SYS->SRAMPCTL & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos); +} + +/** + * @brief Set Peripheral SRAM Power Mode + * @param[in] u32SRAMSel is SRAM region selection. Including : + * - \ref SYS_SRAMPPCT_CAN_Msk + * - \ref SYS_SRAMPPCT_USBD_Msk + * - \ref SYS_SRAMPPCT_PDMA0_Msk + * - \ref SYS_SRAMPPCT_PDMA1_Msk + * - \ref SYS_SRAMPPCT_FMC_Msk + * @param[in] u32PowerMode is SRAM power mode. Including : + * - \ref SYS_SRAMPPCT_SRAM_NORMAL + * - \ref SYS_SRAMPPCT_SRAM_RETENTION + * - \ref SYS_SRAMPPCT_SRAM_POWER_SHUT_DOWN + * @return None + * @details This function set peripheral SRAM power mode. + * The register write-protection function should be disabled before using this function. + */ +void SYS_SetPSRAMPowerMode(uint32_t u32SRAMSel, uint32_t u32PowerMode) +{ + uint32_t u32SRAMSelPos = 0UL; + + /* Get peripheral SRAM power mode setting position */ + while(u32SRAMSelPos < 10UL) + { + if(u32SRAMSel & (1 << u32SRAMSelPos)) + { + break; + } + else + { + u32SRAMSelPos++; + } + } + + /* Set peripheral SRAM power mode setting */ + SYS->SRAMPPCT = (SYS->SRAMPPCT & (~u32SRAMSel)) | (u32PowerMode << u32SRAMSelPos); +} + + +/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group SYS_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/timer.c b/arch/riscv32/fe310/src/StdDriver/src/timer.c new file mode 100644 index 00000000..04f3176f --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/timer.c @@ -0,0 +1,392 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * @brief Timer Controller(Timer) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_Driver TIMER Driver + @{ +*/ + +/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions + @{ +*/ + +/** + * @brief Open Timer with Operate Mode and Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mode Operation mode. Possible options are + * - \ref TIMER_ONESHOT_MODE + * - \ref TIMER_PERIODIC_MODE + * - \ref TIMER_TOGGLE_MODE + * - \ref TIMER_CONTINUOUS_MODE + * @param[in] u32Freq Target working frequency + * + * @return Real timer working frequency + * + * @details This API is used to configure timer to operate in specified mode and frequency. + * If timer cannot work in target frequency, a closest frequency will be chose and returned. + * @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling + * \ref TIMER_Start macro or program registers directly. + */ +uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Cmpr = 0UL, u32Prescale = 0UL; + + /* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */ + if(u32Freq > (u32Clk / 2UL)) + { + u32Cmpr = 2UL; + } + else + { + u32Cmpr = u32Clk / u32Freq; + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CTL = u32Mode | u32Prescale; + timer->CMP = u32Cmpr; + + return(u32Clk / (u32Cmpr * (u32Prescale + 1UL))); +} + +/** + * @brief Stop Timer Counting + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API stops timer counting and disable all timer interrupt function. + */ +void TIMER_Close(TIMER_T *timer) +{ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; +} + +/** + * @brief Create a specify Delay Time + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second). + * + * @return None + * + * @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode. + * @note This API overwrites the register setting of the timer used to count the delay time. + * @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay. + */ +void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec) +{ + uint32_t u32Clk = TIMER_GetModuleClock(timer); + uint32_t u32Prescale = 0UL, u32Delay = (SystemCoreClock / u32Clk) + 1UL; + uint32_t u32Cmpr, u32NsecPerTick; + + /* Clear current timer configuration */ + timer->CTL = 0UL; + timer->EXTCTL = 0UL; + + if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */ + { + if(u32Usec < 1000UL) + { + u32Usec = 1000UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + else + { + if(u32Usec < 100UL) + { + u32Usec = 100UL; + } + if(u32Usec > 1000000UL) + { + u32Usec = 1000000UL; + } + } + + if(u32Clk <= 1000000UL) + { + u32Prescale = 0UL; + u32NsecPerTick = 1000000000UL / u32Clk; + u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick; + } + else + { + u32Cmpr = u32Usec * (u32Clk / 1000000UL); + u32Prescale = (u32Cmpr >> 24); /* for 24 bits CMPDAT */ + if (u32Prescale > 0UL) + u32Cmpr = u32Cmpr / (u32Prescale + 1UL); + } + + timer->CMP = u32Cmpr; + timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale; + + /* + When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it. + And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag. + */ + for(; u32Delay > 0UL; u32Delay--) + { + __NOP(); + } + + while(timer->CTL & TIMER_CTL_ACTSTS_Msk) {} +} + +/** + * @brief Enable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CapMode Timer capture mode. Could be + * - \ref TIMER_CAPTURE_FREE_COUNTING_MODE + * - \ref TIMER_CAPTURE_COUNTER_RESET_MODE + * @param[in] u32Edge Timer capture trigger edge. Possible values are + * - \ref TIMER_CAPTURE_EVENT_FALLING + * - \ref TIMER_CAPTURE_EVENT_RISING + * - \ref TIMER_CAPTURE_EVENT_FALLING_RISING + * - \ref TIMER_CAPTURE_EVENT_RISING_FALLING + * - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD + * - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD + * + * @return None + * + * @details This API is used to enable timer capture function with specify capture trigger edge \n + * to get current counter value or reset counter value to 0. + * @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly. + */ +void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) | + u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Disable Timer Capture Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer capture function. + */ +void TIMER_DisableCapture(TIMER_T *timer) +{ + timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk; +} + +/** + * @brief Enable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Edge Detection edge of counter pin. Could be ether + * - \ref TIMER_COUNTER_EVENT_FALLING, or + * - \ref TIMER_COUNTER_EVENT_RISING + * + * @return None + * + * @details This function is used to enable the timer counter function with specify detection edge. + * @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly. + * @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode. + */ +void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge) +{ + timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge; + timer->CTL |= TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Disable Timer Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This API is used to disable the timer event counter function. + */ +void TIMER_DisableEventCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk; +} + +/** + * @brief Get Timer Clock Frequency + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return Timer clock frequency + * + * @details This API is used to get the timer clock frequency. + * @note This API cannot return correct clock rate if timer source is from external clock input. + */ +uint32_t TIMER_GetModuleClock(TIMER_T *timer) +{ + uint32_t u32Src, u32Clk = __HIRC; + const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC}; + + if(timer == TIMER0) + { + u32Src = CLK_GetModuleClockSource(TMR0_MODULE); + } + else if(timer == TIMER1) + { + u32Src = CLK_GetModuleClockSource(TMR1_MODULE); + } + else if((timer == TIMER2) || (timer == TIMER2_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR2_MODULE); + } + else if((timer == TIMER3) || (timer == TIMER3_NS)) + { + u32Src = CLK_GetModuleClockSource(TMR3_MODULE); + } + else + { + return 0UL; + } + + if(u32Src == 2UL) + { + if((timer == TIMER0) || (timer == TIMER1)) + { + u32Clk = CLK_GetPCLK0Freq(); + } + else + { + u32Clk = CLK_GetPCLK1Freq(); + } + } + else + { + u32Clk = au32Clk[u32Src]; + } + + return u32Clk; +} + +/** + * @brief Enable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DropCount This parameter has no effect in this BSP + * @param[in] u32Timeout This parameter has no effect in this BSP + * @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE + * + * @return None + * + * @details This function is used to calculate input event frequency. After enable + * this function, a pair of timers, TIMER0 and TIMER1, or TIMER2 and TIMER3 + * will be configured for this function. The mode used to calculate input + * event frequency is mentioned as "Inter Timer Trigger Mode" in Technical + * Reference Manual. + */ +void TIMER_EnableFreqCounter(TIMER_T *timer, + uint32_t u32DropCount, + uint32_t u32Timeout, + uint32_t u32EnableInt) +{ + TIMER_T *t; /* store the timer base to configure compare value */ + + (void)u32DropCount; + (void)u32Timeout; + + if(timer == TIMER0) + { + t = TIMER1; + } + else if(timer == TIMER2) + { + t = TIMER3; + } + else if(timer == TIMER2_NS) + { + t = TIMER3_NS; + } + else + { + t = 0UL; + } + + if(t != 0UL) + { + t->CMP = 0xFFFFFFUL; + t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0UL; + timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk; + } +} + +/** + * @brief Disable Timer Frequency Counter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @brief This function is used to disable the Timer frequency counter function. + */ +void TIMER_DisableFreqCounter(TIMER_T *timer) +{ + timer->CTL &= ~TIMER_CTL_INTRGEN_Msk; +} + +/** + * @brief Select Interrupt Source to Trigger others Module + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Src Selects the interrupt source to trigger other modules. Could be: + * - \ref TIMER_TRGSRC_TIMEOUT_EVENT + * - \ref TIMER_TRGSRC_CAPTURE_EVENT + * + * @return None + * + * @brief This function is used to select the interrupt source used to trigger other modules. + */ +void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src) +{ + timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src; +} + +/** + * @brief Set Modules Trigger by Timer Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Mask The mask of modules (EPWM, EADC, DAC and PDMA) trigger by timer. Is the combination of + * - \ref TIMER_TRG_TO_EPWM, + * - \ref TIMER_TRG_TO_EADC, + * - \ref TIMER_TRG_TO_DAC and + * - \ref TIMER_TRG_TO_PDMA + * + * @return None + * + * @details This function is used to set EPWM, EADC, DAC and PDMA module triggered by timer interrupt event. + */ +void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask) +{ + timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGEPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask; +} + +/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/timer_pwm.c b/arch/riscv32/fe310/src/StdDriver/src/timer_pwm.c new file mode 100644 index 00000000..1cc2fe3e --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/timer_pwm.c @@ -0,0 +1,452 @@ +/**************************************************************************//** + * @file timer.c + * @version V3.00 + * @brief Timer PWM Controller(Timer PWM) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2017-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver + @{ +*/ + +/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions + @{ +*/ + +/** + * @brief Set PWM Counter Clock Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CntClkSrc PWM counter clock source, could be one of following source + * - \ref TPWM_CNTR_CLKSRC_TMR_CLK + * - \ref TPWM_CNTR_CLKSRC_TIMER0_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER1_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER2_INT + * - \ref TPWM_CNTR_CLKSRC_TIMER3_INT + * + * @return None + * + * @details This function is used to set PWM counter clock source. + */ +void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc) +{ + (timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc; +} + +/** + * @brief Configure PWM Output Frequency and Duty Cycle + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Frequency Target generator frequency. + * @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%... + * + * @return Nearest frequency clock in nano second + * + * @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode. + * @note This API is only available if Timer PWM counter clock source is from TMRx_CLK. + */ +uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle) +{ + uint32_t u32PWMClockFreq, u32TargetFreq; + uint32_t u32Prescaler = 0x1000UL, u32Period = 1UL, u32CMP; + + if((timer == TIMER0) || (timer == TIMER1)) + { + u32PWMClockFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PWMClockFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate u16PERIOD and u16PSC */ + for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++) + { + u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency; + + /* If target u32Period is larger than 0x10000, need to use a larger prescaler */ + if(u32Period <= 0x10000UL) + { + break; + } + } + /* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */ + u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period; + + /* Set PWM to up count type */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos); + + /* Set PWM to auto-reload mode */ + timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos); + + /* Convert to real register value */ + TPWM_SET_PERIOD(timer, (u32Period - 1UL)); + if(u32DutyCycle) + { + u32CMP = (u32DutyCycle * u32Period) / 100UL; + } + else + { + u32CMP = 0UL; + } + + TPWM_SET_CMPDAT(timer, u32CMP); + + TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL)); + + return (u32TargetFreq); +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Enable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion. + * + * @return None + * + * @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount) +{ + timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount; +} + +/** + * @brief Disable Dead-Time Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable Dead-time of selected channel. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableDeadTime(TIMER_T *timer) +{ + timer->PWMDTCTL = 0x0UL; +} + +/** + * @brief Enable PWM Counter + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM generator and start counter counting. + */ +void TPWM_EnableCounter(TIMER_T *timer) +{ + timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Disable PWM Generator + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit. + */ +void TPWM_DisableCounter(TIMER_T *timer) +{ + timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk; +} + +/** + * @brief Enable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32Condition The condition to trigger ADC. It could be one of following conditions: + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_POINT + * - \ref TPWM_TRIGGER_ADC_AT_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_ZERO_OR_PERIOD_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_UP_COUNT_POINT + * - \ref TPWM_TRIGGER_ADC_AT_COMPARE_DOWN_COUNT_POINT + * + * @return None + * + * @details This function is used to enable specified counter compare event to trigger ADC. + */ +void TPWM_EnableTriggerADC(TIMER_T *timer, uint32_t u32Condition) +{ + timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | u32Condition; +} + +/** + * @brief Disable Trigger ADC + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable counter compare event to trigger ADC. + */ +void TPWM_DisableTriggerADC(TIMER_T *timer) +{ + timer->PWMEADCTS = 0x0UL; +} + +/** + * @brief Enable Fault Brake Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting + * - \ref TPWM_OUTPUT_TOGGLE + * - \ref TPWM_OUTPUT_NOTHING + * - \ref TPWM_OUTPUT_LOW + * - \ref TPWM_OUTPUT_HIGH + * @param[in] u32BrakeSource Fault brake source, combination of following source + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1 + * - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR + * - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM + * + * @return None + * + * @details This function is used to enable fault brake function. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource) +{ + timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL); + timer->PWMBRKCTL = (timer->PWMBRKCTL & ~(TIMER_PWMBRKCTL_BRKAEVEN_Msk | TIMER_PWMBRKCTL_BRKAODD_Msk)) | + (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos); +} + +/** + * @brief Enable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to enable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 |= u32IntSource; +} + +/** + * @brief Disable Fault Brake Interrupt + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to disable fault brake interrupt. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTEN1 &= ~u32IntSource; +} + +/** + * @brief Indicate Fault Brake Interrupt Flag + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return Fault brake interrupt flag of specified source + * @retval 0 Fault brake interrupt did not occurred + * @retval 1 Fault brake interrupt occurred + * + * @details This function is used to indicate fault brake interrupt flag occurred or not of selected source. + */ +uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL); +} + +/** + * @brief Clear Fault Brake Interrupt Flags + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32IntSource Interrupt source, could be one of following source + * - \ref TPWM_BRAKE_EDGE + * - \ref TPWM_BRAKE_LEVEL + * + * @return None + * + * @details This function is used to clear fault brake interrupt flags of selected source. + * @note The register write-protection function should be disabled before using this function. + */ +void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource) +{ + timer->PWMINTSTS1 = (0x3UL << u32IntSource); +} + +/** + * @brief Enable Load Mode + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode + * - \ref TPWM_LOAD_MODE_PERIOD + * - \ref TPWM_LOAD_MODE_IMMEDIATE + * - \ref TPWM_LOAD_MODE_CENTER + * + * @return None + * + * @details This function is used to enable load mode of selected channel. + * @note The default loading mode is period loading mode. + */ +void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode) +{ + timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode; +} + +/** + * @brief Enable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinSrc The external brake pin source, could be one of following source + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * @param[in] u32DebounceCnt This value controls the real debounce sample time. + * The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt). + * @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_1 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_2 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_4 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_8 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_16 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_32 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_64 + * - \ref TPWM_BKP_DBCLK_PCLK_DIV_128 + * + * @return None + * + * @details This function is used to enable external brake pin detector noise filter function. + */ +void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel) +{ + timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) | + (u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) | + (u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) | + (u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Disable Brake Pin Noise Filter Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable external brake pin detector noise filter function. + */ +void TPWM_DisableBrakePinDebounce(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk; +} + +/** + * @brief Enable Brake Pin Inverse Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to enable PWM brake pin inverse function. + */ +void TPWM_EnableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Disable Brake Pin Inverse Function + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * + * @return None + * + * @details This function is used to disable PWM brake pin inverse function. + */ +void TPWM_DisableBrakePinInverse(TIMER_T *timer) +{ + timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk; +} + +/** + * @brief Set Brake Pin Source + * + * @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3. + * @param[in] u32BrakePinNum Brake pin selection. One of the following: + * - \ref TPWM_TM_BRAKE0 + * - \ref TPWM_TM_BRAKE1 + * - \ref TPWM_TM_BRAKE2 + * - \ref TPWM_TM_BRAKE3 + * + * @return None + * + * @details This function is used to set PWM brake pin source. + */ +void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum) +{ + timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos)); +} + + +/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group TIMER_PWM_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2017-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/uart.c b/arch/riscv32/fe310/src/StdDriver/src/uart.c new file mode 100644 index 00000000..bed504af --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/uart.c @@ -0,0 +1,696 @@ +/**************************************************************************//** + * @file uart.c + * @version V3.00 + * @brief M2351 series UART Interface Controller (UART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup UART_Driver UART Driver + @{ +*/ + + +/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions + @{ +*/ + +/** + * @brief Clear UART specified interrupt flag + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTSTS_LININT_Msk : LIN Bus interrupt + * - \ref UART_INTSTS_WKINT_Msk : Wake-up interrupt + * - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt + * - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt + * - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt + * + * @return None + * + * @details The function is used to clear UART specified interrupt flag. + */ +void UART_ClearIntFlag(UART_T* uart, uint32_t u32InterruptFlag) +{ + + if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear MODEM Status Interrupt */ + { + uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */ + { + uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */ + { + uart->WKSTS = UART_WKSTS_CTSWKF_Msk | UART_WKSTS_DATWKF_Msk | + UART_WKSTS_RFRTWKF_Msk | UART_WKSTS_RS485WKF_Msk | + UART_WKSTS_TOUTWKF_Msk; + } + + if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */ + { + uart->INTSTS = UART_INTSTS_LINIF_Msk; + uart->LINSTS = UART_LINSTS_BITEF_Msk | UART_LINSTS_BRKDETF_Msk | + UART_LINSTS_SLVSYNCF_Msk | UART_LINSTS_SLVIDPEF_Msk | + UART_LINSTS_SLVHEF_Msk | UART_LINSTS_SLVHDETF_Msk ; + } + +} + + +/** + * @brief Disable UART interrupt + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART interrupt. + */ +void UART_Close(UART_T* uart) +{ + uart->INTEN = 0ul; +} + + +/** + * @brief Disable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to disable UART auto flow control. + */ +void UART_DisableFlowCtrl(UART_T* uart) +{ + uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk); +} + + +/** + * @brief Disable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module. + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ. + */ +void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + /* Disable UART specified interrupt */ + UART_DISABLE_INT(uart, u32InterruptFlag); + + /* Disable NVIC UART IRQ */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART0_IRQn); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART1_IRQn); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART2_IRQn); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART3_IRQn); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART4_IRQn); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + NVIC_DisableIRQ(UART5_IRQn); + break; + default: + break; + } +} + + +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +/** + * @brief Enable UART auto flow control function + * + * @param[in] uart The pointer of the specified UART module. + * + * @return None + * + * @details The function is used to Enable UART auto flow control. + */ +void UART_EnableFlowCtrl(UART_T* uart) +{ + /* Set RTS pin output is low level active */ + uart->MODEM |= UART_MODEM_RTSACTLV_Msk; + + /* Set CTS pin input is low level active */ + uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk; + + /* Set RTS and CTS auto flow control enable */ + uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk; +} + + +/** + * @brief Enable UART specified interrupt + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32InterruptFlag The specified interrupt of UART module: + * - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt + * - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt + * - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt + * - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt + * - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt + * - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt + * - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt + * - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt + * - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt + * - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt + * + * @return None + * + * @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ. + */ +void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag) +{ + + /* Enable UART specified interrupt */ + UART_ENABLE_INT(uart, u32InterruptFlag); + + /* Enable NVIC UART IRQ */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART0_IRQn); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART1_IRQn); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART2_IRQn); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART3_IRQn); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART4_IRQn); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + NVIC_EnableIRQ(UART5_IRQn); + break; + default: + break; + } + +} + + +/** + * @brief Open and set UART function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The baudrate of UART module. + * + * @return None + * + * @details This function use to enable UART function and set baud-rate. + */ +void UART_Open(UART_T* uart, uint32_t u32baudrate) +{ + uint32_t u32UartClkSrcSel, u32UartClkDivNum; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + break; + default: + return ; + } + + /* Select UART function */ + uart->FUNCSEL = UART_FUNCSEL_UART; + + /* Set UART line configuration */ + uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1; + + /* Set UART Rx and RTS trigger level */ + uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk); + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } +} + + +/** + * @brief Read UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive FIFO. + * @param[in] u32ReadBytes The the read bytes number of data. + * + * @return u32Count Receive byte count + * + * @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf. + */ +uint32_t UART_Read(UART_T* uart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + pu8RxBuf[u32Count] = (uint8_t)uart->DAT; /* Get Data from UART RX */ + } + } + + return u32Count; +} + + +/** + * @brief Set UART line configuration + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32baudrate The register value of baudrate of UART module. + * If u32baudrate = 0, UART baudrate will not change. + * @param[in] u32data_width The data length of UART module. + * - \ref UART_WORD_LEN_5 + * - \ref UART_WORD_LEN_6 + * - \ref UART_WORD_LEN_7 + * - \ref UART_WORD_LEN_8 + * @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module. + * - \ref UART_PARITY_NONE + * - \ref UART_PARITY_ODD + * - \ref UART_PARITY_EVEN + * - \ref UART_PARITY_MARK + * - \ref UART_PARITY_SPACE + * @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module. + * - \ref UART_STOP_BIT_1 + * - \ref UART_STOP_BIT_1_5 + * - \ref UART_STOP_BIT_2 + * + * @return None + * + * @details This function use to config UART line setting. + */ +void UART_SetLineConfig(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32UartClkSrcSel, u32UartClkDivNum; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv = 0ul; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + break; + default: + return ; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART baud rate */ + if(u32baudrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE2_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate); + + if(u32BaudDiv > 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32baudrate)); + } + else + { + uart->BAUD = (UART_BAUD_MODE2 | u32BaudDiv); + } + } + + /* Set UART line configuration */ + uart->LINE = u32data_width | u32parity | u32stop_bits; +} + + +/** + * @brief Set Rx timeout count + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32TOC Rx timeout counter. + * + * @return None + * + * @details This function use to set Rx timeout count. + */ +void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC) +{ + /* Set time-out interrupt comparator */ + uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC); + + /* Set time-out counter enable */ + uart->INTEN |= UART_INTEN_TOCNTEN_Msk; +} + + +/** + * @brief Select and configure IrDA function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Buadrate The baudrate of UART module. + * @param[in] u32Direction The direction of UART module in IrDA mode: + * - \ref UART_IRDA_TXEN + * - \ref UART_IRDA_RXEN + * + * @return None + * + * @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate. + */ +void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction) +{ + uint32_t u32UartClkSrcSel, u32UartClkDivNum; + uint32_t au32ClkTbl[4] = {__HXT, 0ul, __LXT, __HIRC}; + uint32_t u32BaudDiv; + + /* Select IrDA function mode */ + uart->FUNCSEL = UART_FUNCSEL_IrDA; + + /* Get UART clock source selection and UART clock divider number */ + switch((uint32_t)uart) + { + case UART0_BASE: + case UART0_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE); + break; + case UART1_BASE: + case UART1_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE); + break; + case UART2_BASE: + case UART2_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE); + break; + case UART3_BASE: + case UART3_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE); + break; + case UART4_BASE: + case UART4_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE); + break; + case UART5_BASE: + case UART5_BASE+NS_OFFSET: + u32UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE); + u32UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE); + break; + default: + return ; + } + + /* Get PLL clock frequency if UART clock source selection is PLL */ + if(u32UartClkSrcSel == 1ul) + { + au32ClkTbl[u32UartClkSrcSel] = CLK_GetPLLClockFreq(); + } + + /* Set UART IrDA baud rate in mode 0 */ + if(u32Buadrate != 0ul) + { + u32BaudDiv = UART_BAUD_MODE0_DIVIDER((au32ClkTbl[u32UartClkSrcSel]) / (u32UartClkDivNum + 1ul), u32Buadrate); + + if(u32BaudDiv < 0xFFFFul) + { + uart->BAUD = (UART_BAUD_MODE0 | u32BaudDiv); + } + } + + /* Configure IrDA relative settings */ + if(u32Direction == UART_IRDA_RXEN) + { + uart->IRDA |= UART_IRDA_RXINV_Msk; /* Rx signal is inverse */ + uart->IRDA &= ~UART_IRDA_TXEN_Msk; + } + else + { + uart->IRDA &= ~UART_IRDA_TXINV_Msk; /* Tx signal is not inverse */ + uart->IRDA |= UART_IRDA_TXEN_Msk; + } + +} + + +/** + * @brief Select and configure RS485 function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The operation mode(NMM/AUD/AAD). + * - \ref UART_ALTCTL_RS485NMM_Msk + * - \ref UART_ALTCTL_RS485AUD_Msk + * - \ref UART_ALTCTL_RS485AAD_Msk + * @param[in] u32Addr The RS485 address. + * + * @return None + * + * @details The function is used to set RS485 relative setting. + */ +void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr) +{ + /* Select UART RS485 function mode */ + uart->FUNCSEL = UART_FUNCSEL_RS485; + + /* Set RS585 configuration */ + uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk); + uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos)); +} + + +/** + * @brief Select and configure LIN function + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] u32Mode The LIN direction : + * - \ref UART_ALTCTL_LINTXEN_Msk + * - \ref UART_ALTCTL_LINRXEN_Msk + * @param[in] u32BreakLength The breakfield length. + * + * @return None + * + * @details The function is used to set LIN relative setting. + */ +void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength) +{ + /* Select LIN function mode */ + uart->FUNCSEL = UART_FUNCSEL_LIN; + + /* Select LIN function setting : Tx enable, Rx enable and break field length */ + uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk); + uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos)); +} + + +/** + * @brief Write UART data + * + * @param[in] uart The pointer of the specified UART module. + * @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO. + * @param[out] u32WriteBytes The byte number of data. + * + * @return u32Count transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by UART. + */ +uint32_t UART_Write(UART_T* uart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + uint32_t u32Exit = 0ul; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while( UART_IS_TX_FULL(uart) ) /* Wait Tx not full and Time-out manner */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + u32Exit = 1ul; + break; + } + else + { + } + } + + if(u32Exit == 1ul) + { + break; + } + else + { + uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */ + } + } + + return u32Count; +} + + +/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/usbd.c b/arch/riscv32/fe310/src/StdDriver/src/usbd.c new file mode 100644 index 00000000..dfb09af9 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/usbd.c @@ -0,0 +1,791 @@ +/**************************************************************************//** + * @file usbd.c + * @version V3.00 + * @brief M2351 series USBD driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2018-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USBD_Driver USBD Driver + @{ +*/ + + +/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions + @{ +*/ + +/* Global variables for Control Pipe */ +uint8_t g_USBD_au8SetupPacket[8] = {0UL}; /*!< Setup packet buffer */ +volatile uint8_t g_USBD_u8RemoteWakeupEn = 0UL; /*!< Remote wake up function enable flag */ + +/** + * @cond HIDDEN_SYMBOLS + */ +static uint8_t *g_USBD_pu8CtrlInPointer = 0; +static uint8_t *g_USBD_pu8CtrlOutPointer = 0; +static volatile uint32_t g_USBD_u32CtrlInSize = 0UL; +static volatile uint32_t g_USBD_u32CtrlOutSize = 0UL; +static volatile uint32_t g_USBD_u32CtrlOutSizeLimit = 0UL; +static volatile uint32_t g_USBD_u32UsbAddr = 0UL; +static volatile uint32_t g_USBD_u32UsbConfig = 0UL; +static volatile uint32_t g_USBD_u32CtrlMaxPktSize = 8UL; +static volatile uint32_t g_USBD_u32UsbAltInterface = 0UL; +static volatile uint32_t g_USBD_u32CtrlOutToggle = 0; +static volatile uint8_t g_USBD_u8CtrlInZeroFlag = 0UL; +/** + * @endcond + */ + +const S_USBD_INFO_T *g_USBD_sInfo; /*!< A pointer for USB information structure */ + +VENDOR_REQ g_USBD_pfnVendorRequest = NULL; /*!< USB Vendor Request Functional Pointer */ +CLASS_REQ g_USBD_pfnClassRequest = NULL; /*!< USB Class Request Functional Pointer */ +SET_INTERFACE_REQ g_USBD_pfnSetInterface = NULL; /*!< USB Set Interface Functional Pointer */ +SET_CONFIG_CB g_USBD_pfnSetConfigCallback = NULL; /*!< USB Set configuration callback function pointer */ +uint32_t g_USBD_u32EpStallLock = 0UL; /*!< Bit map flag to lock specified EP when SET_FEATURE */ + +/** + * @brief This function makes USBD module to be ready to use + * + * @param[in] param The structure of USBD information. + * @param[in] pfnClassReq USB Class request callback function. + * @param[in] pfnSetInterface USB Set Interface request callback function. + * + * @return None + * + * @details This function will enable USB controller, USB PHY transceiver and pull-up resistor of USB_D+ pin. USB PHY will drive SE0 to bus. + */ +void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface) +{ + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + g_USBD_sInfo = param; + g_USBD_pfnClassRequest = pfnClassReq; + g_USBD_pfnSetInterface = pfnSetInterface; + + /* get EP0 maximum packet size */ + g_USBD_u32CtrlMaxPktSize = g_USBD_sInfo->gu8DevDesc[7]; + + /* Initial USB engine */ +#ifdef SUPPORT_LPM + pUSBD->ATTR = 0x7D0UL | USBD_LPMACK; +#else + pUSBD->ATTR = 0x7D0UL; +#endif + /* Force SE0 */ + USBD_SET_SE0(); +} + +/** + * @brief This function makes USB host to recognize the device + * + * @param None + * + * @return None + * + * @details Enable WAKEUP, FLDET, USB and BUS interrupts. Disable software-disconnect function after 100ms delay with SysTick timer. + */ +void USBD_Start(void) +{ + /* Disable software-disconnect function */ + USBD_CLR_SE0(); + + /* Clear USB-related interrupts before enable interrupt */ + USBD_CLR_INT_FLAG(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); + + /* Enable USB-related interrupts. */ + USBD_ENABLE_INT(USBD_INT_BUS | USBD_INT_USB | USBD_INT_FLDET | USBD_INT_WAKEUP); +} + +/** + * @brief Get the received SETUP packet + * + * @param[in] buf A buffer pointer used to store 8-byte SETUP packet. + * + * @return None + * + * @details Store SETUP packet to a user-specified buffer. + * + */ +void USBD_GetSetupPacket(uint8_t *buf) +{ + USBD_MemCopy(buf, g_USBD_au8SetupPacket, 8UL); +} + +/** + * @brief Process SETUP packet + * + * @param None + * + * @return None + * + * @details Parse SETUP packet and perform the corresponding action. + * + */ +void USBD_ProcessSetupPacket(void) +{ + g_USBD_u32CtrlOutToggle = 0; + /* Get SETUP packet from USB buffer */ + USBD_MemCopy(g_USBD_au8SetupPacket, (uint8_t *)USBD_BUF_BASE, 8UL); + + /* Check the request type */ + switch(g_USBD_au8SetupPacket[0] & 0x60UL) + { + case REQ_STANDARD: /* Standard */ + { + USBD_StandardRequest(); + break; + } + case REQ_CLASS: /* Class */ + { + if(g_USBD_pfnClassRequest != NULL) + { + g_USBD_pfnClassRequest(); + } + break; + } + case REQ_VENDOR: /* Vendor */ + { + if(g_USBD_pfnVendorRequest != NULL) + { + g_USBD_pfnVendorRequest(); + } + break; + } + default: /* reserved */ + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } +} + +/** + * @brief Process GetDescriptor request + * + * @param None + * + * @return None + * + * @details Parse GetDescriptor request and perform the corresponding action. + * + */ +static void USBD_GetDescriptor(void) +{ + uint32_t u32Len; + + g_USBD_u8CtrlInZeroFlag = (uint8_t)0UL; + u32Len = 0UL; + u32Len = g_USBD_au8SetupPacket[7]; + u32Len <<= 8UL; + u32Len += g_USBD_au8SetupPacket[6]; + + switch(g_USBD_au8SetupPacket[3]) + { + /* Get Device Descriptor */ + case DESC_DEVICE: + { + u32Len = USBD_Minimum(u32Len, (uint32_t)LEN_DEVICE); + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8DevDesc, u32Len); + break; + } + /* Get Configuration Descriptor */ + case DESC_CONFIG: + { + uint32_t u32TotalLen; + + u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[3]; + u32TotalLen = g_USBD_sInfo->gu8ConfigDesc[2] + (u32TotalLen << 8UL); + + if(u32Len > u32TotalLen) + { + u32Len = u32TotalLen; + if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL) + { + g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8ConfigDesc, u32Len); + break; + } + /* Get BOS Descriptor */ + case DESC_BOS: + { + if(g_USBD_sInfo->gu8BosDesc == 0) + { + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + } + else + { + u32Len = USBD_Minimum(u32Len, LEN_BOS + LEN_BOSCAP); + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8BosDesc, u32Len); + } + break; + } + /* Get HID Descriptor */ + case DESC_HID: + { + /* CV3.0 HID Class Descriptor Test, + Need to indicate index of the HID Descriptor within gu8ConfigDescriptor, specifically HID Composite device. */ + uint32_t u32ConfigDescOffset; /* u32ConfigDescOffset is configuration descriptor offset (HID descriptor start index) */ + u32Len = USBD_Minimum(u32Len, LEN_HID); + u32ConfigDescOffset = g_USBD_sInfo->gu32ConfigHidDescIdx[g_USBD_au8SetupPacket[4]]; + USBD_PrepareCtrlIn((uint8_t *)&g_USBD_sInfo->gu8ConfigDesc[u32ConfigDescOffset], u32Len); + break; + } + /* Get Report Descriptor */ + case DESC_HID_RPT: + { + if(u32Len > g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]]) + { + u32Len = g_USBD_sInfo->gu32HidReportSize[g_USBD_au8SetupPacket[4]]; + if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL) + { + g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8HidReportDesc[g_USBD_au8SetupPacket[4]], u32Len); + break; + } + /* Get String Descriptor */ + case DESC_STRING: + { + /* Get String Descriptor */ + if(g_USBD_au8SetupPacket[2] < 4UL) + { + if(u32Len > g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]) + { + u32Len = g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]][0]; + if((u32Len % g_USBD_u32CtrlMaxPktSize) == 0UL) + { + g_USBD_u8CtrlInZeroFlag = (uint8_t)1UL; + } + } + USBD_PrepareCtrlIn((uint8_t *)g_USBD_sInfo->gu8StringDesc[g_USBD_au8SetupPacket[2]], u32Len); + break; + } + else + { + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + default: + /* Not support. Reply STALL. */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } +} + +/** + * @brief Process standard request + * + * @param None + * + * @return None + * + * @details Parse standard request and perform the corresponding action. + * + */ +void USBD_StandardRequest(void) +{ + uint32_t u32Addr; + USBD_T *pUSBD; + OTG_T *pOTG; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + pOTG = OTG_NS; + } + else + { + pUSBD = USBD; + pOTG = OTG; + } + + /* clear global variables for new request */ + g_USBD_pu8CtrlInPointer = 0; + g_USBD_u32CtrlInSize = 0UL; + + if((g_USBD_au8SetupPacket[0] & 0x80UL) == 0x80UL) /* request data transfer direction */ + { + /* Device to host */ + switch(g_USBD_au8SetupPacket[1]) + { + case GET_CONFIGURATION: + { + /* Return current configuration setting */ + /* Data stage */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)g_USBD_u32UsbConfig; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + case GET_DESCRIPTOR: + { + USBD_GetDescriptor(); + USBD_PrepareCtrlOut(0, 0UL); /* For status stage */ + break; + } + case GET_INTERFACE: + { + /* Return current interface setting */ + /* Data stage */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)g_USBD_u32UsbAltInterface; + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 1UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + case GET_STATUS: + { + /* Device */ + if(g_USBD_au8SetupPacket[0] == 0x80UL) + { + uint8_t u8Tmp; + + u8Tmp = (uint8_t)0UL; + if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x40UL) == 0x40UL) + { + u8Tmp |= (uint8_t)1UL; /* Self-Powered/Bus-Powered. */ + } + if((g_USBD_sInfo->gu8ConfigDesc[7] & 0x20UL) == 0x20UL) + { + u8Tmp |= (uint8_t)(g_USBD_u8RemoteWakeupEn << 1UL); /* Remote wake up */ + } + + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = u8Tmp; + + } + /* Interface */ + else if(g_USBD_au8SetupPacket[0] == 0x81UL) + { + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)0UL; + } + /* Endpoint */ + else if(g_USBD_au8SetupPacket[0] == 0x82UL) + { + uint8_t ep = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + M8(u32Addr) = (uint8_t)(USBD_GetStall(ep) ? 1UL : 0UL); + } + + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0) + 1UL; + M8(u32Addr) = (uint8_t)0UL; + /* Data stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 2UL); + /* Status stage */ + USBD_PrepareCtrlOut(0, 0UL); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } + else + { + /* Host to device */ + switch(g_USBD_au8SetupPacket[1]) + { + case CLEAR_FEATURE: + { + if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + uint32_t epNum, i; + + /* EP number stall is not allow to be clear in MSC class "Error Recovery Test". + a flag: g_USBD_u32EpStallLock is added to support it */ + epNum = (uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL); + for(i = 0UL; i < USBD_MAX_EP; i++) + { + if(((pUSBD->EP[i].CFG & 0xFUL) == epNum) && ((g_USBD_u32EpStallLock & (1UL << i)) == 0UL)) + { + pUSBD->EP[i].CFGP &= ~USBD_CFGP_SSTALL_Msk; + pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + } + } + else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_USBD_u8RemoteWakeupEn = (uint8_t)0UL; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_ADDRESS: + { + g_USBD_u32UsbAddr = g_USBD_au8SetupPacket[2]; + + /* DATA IN for end of setup */ + /* Status Stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_CONFIGURATION: + { + g_USBD_u32UsbConfig = g_USBD_au8SetupPacket[2]; + + if(g_USBD_pfnSetConfigCallback) + { + g_USBD_pfnSetConfigCallback(); + } + + /* DATA IN for end of setup */ + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_FEATURE: + { + if((g_USBD_au8SetupPacket[0] & 0xFUL) == 0UL) /* 0: device */ + { + if((g_USBD_au8SetupPacket[2] == 3UL) && (g_USBD_au8SetupPacket[3] == 0UL)) /* 3: HNP enable */ + { + pOTG->CTL |= (OTG_CTL_HNPREQEN_Msk | OTG_CTL_BUSREQ_Msk); + } + } + if(g_USBD_au8SetupPacket[2] == FEATURE_ENDPOINT_HALT) + { + USBD_SetStall((uint8_t)(g_USBD_au8SetupPacket[4] & 0xFUL)); + } + else if(g_USBD_au8SetupPacket[2] == FEATURE_DEVICE_REMOTE_WAKEUP) + { + g_USBD_u8RemoteWakeupEn = (uint8_t)1UL; + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + case SET_INTERFACE: + { + g_USBD_u32UsbAltInterface = g_USBD_au8SetupPacket[2]; + if(g_USBD_pfnSetInterface != NULL) + { + g_USBD_pfnSetInterface(g_USBD_u32UsbAltInterface); + } + + /* Status stage */ + USBD_SET_DATA1(EP0); + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + break; + } + default: + { + /* Setup error, stall the device */ + USBD_SET_EP_STALL(EP0); + USBD_SET_EP_STALL(EP1); + break; + } + } + } +} + +/** + * @brief Prepare the first Control IN pipe + * + * @param[in] pu8Buf The pointer of data sent to USB host. + * @param[in] u32Size The IN transfer size. + * + * @return None + * + * @details Prepare data for Control IN transfer. + * + */ +void USBD_PrepareCtrlIn(uint8_t pu8Buf[], uint32_t u32Size) +{ + uint32_t u32Addr; + + if(u32Size > g_USBD_u32CtrlMaxPktSize) + { + /* Data size > MXPLD */ + g_USBD_pu8CtrlInPointer = pu8Buf + g_USBD_u32CtrlMaxPktSize; + g_USBD_u32CtrlInSize = u32Size - g_USBD_u32CtrlMaxPktSize; + USBD_SET_DATA1(EP0); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, g_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlMaxPktSize); + } + else + { + /* Data size <= MXPLD */ + g_USBD_pu8CtrlInPointer = 0; + g_USBD_u32CtrlInSize = 0UL; + USBD_SET_DATA1(EP0); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, pu8Buf, u32Size); + USBD_SET_PAYLOAD_LEN(EP0, u32Size); + } +} + +/** + * @brief Repeat Control IN pipe + * + * @param None + * + * @return None + * + * @details This function processes the remained data of Control IN transfer. + * + */ +void USBD_CtrlIn(void) +{ + uint32_t u32Addr; + + if(g_USBD_u32CtrlInSize) + { + /* Process remained data */ + if(g_USBD_u32CtrlInSize > g_USBD_u32CtrlMaxPktSize) + { + /* Data size > MXPLD */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)g_USBD_pu8CtrlInPointer, g_USBD_u32CtrlMaxPktSize); + USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlMaxPktSize); + g_USBD_pu8CtrlInPointer += g_USBD_u32CtrlMaxPktSize; + g_USBD_u32CtrlInSize -= g_USBD_u32CtrlMaxPktSize; + } + else + { + /* Data size <= MXPLD */ + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP0); + USBD_MemCopy((uint8_t *)u32Addr, (uint8_t *)g_USBD_pu8CtrlInPointer, g_USBD_u32CtrlInSize); + USBD_SET_PAYLOAD_LEN(EP0, g_USBD_u32CtrlInSize); + g_USBD_pu8CtrlInPointer = 0; + g_USBD_u32CtrlInSize = 0UL; + } + } + else /* No more data for IN token */ + { + /* In ACK for Set address */ + if((g_USBD_au8SetupPacket[0] == REQ_STANDARD) && (g_USBD_au8SetupPacket[1] == SET_ADDRESS)) + { + u32Addr = USBD_GET_ADDR(); + if((u32Addr != g_USBD_u32UsbAddr) && (u32Addr == 0UL)) + { + USBD_SET_ADDR(g_USBD_u32UsbAddr); + } + } + + /* For the case of data size is integral times maximum packet size */ + if(g_USBD_u8CtrlInZeroFlag) + { + USBD_SET_PAYLOAD_LEN(EP0, 0UL); + g_USBD_u8CtrlInZeroFlag = (uint8_t)0UL; + } + } +} + +/** + * @brief Prepare the first Control OUT pipe + * + * @param[in] pu8Buf The pointer of data received from USB host. + * @param[in] u32Size The OUT transfer size. + * + * @return None + * + * @details This function is used to prepare the first Control OUT transfer. + * + */ +void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size) +{ + g_USBD_pu8CtrlOutPointer = pu8Buf; + g_USBD_u32CtrlOutSize = 0UL; + g_USBD_u32CtrlOutSizeLimit = u32Size; + USBD_SET_PAYLOAD_LEN(EP1, g_USBD_u32CtrlMaxPktSize); +} + +/** + * @brief Repeat Control OUT pipe + * + * @param None + * + * @return None + * + * @details This function processes the successive Control OUT transfer. + * + */ +void USBD_CtrlOut(void) +{ + uint32_t u32Size; + uint32_t u32Addr; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + if(g_USBD_u32CtrlOutToggle != (pUSBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk)) + { + g_USBD_u32CtrlOutToggle = pUSBD->EPSTS0 & USBD_EPSTS0_EPSTS1_Msk; + if(g_USBD_u32CtrlOutSize < g_USBD_u32CtrlOutSizeLimit) + { + u32Size = USBD_GET_PAYLOAD_LEN(EP1); + u32Addr = USBD_BUF_BASE + USBD_GET_EP_BUF_ADDR(EP1); + USBD_MemCopy((uint8_t *)g_USBD_pu8CtrlOutPointer, (uint8_t *)u32Addr, u32Size); + g_USBD_pu8CtrlOutPointer += u32Size; + g_USBD_u32CtrlOutSize += u32Size; + + if(g_USBD_u32CtrlOutSize < g_USBD_u32CtrlOutSizeLimit) + { + USBD_SET_PAYLOAD_LEN(EP1, g_USBD_u32CtrlMaxPktSize); + } + } + } + else + { + USBD_SET_PAYLOAD_LEN(EP1, g_USBD_u32CtrlMaxPktSize); + } +} + +/** + * @brief Reset software flags + * + * @param None + * + * @return None + * + * @details This function resets all variables for protocol and resets USB device address to 0. + * + */ +void USBD_SwReset(void) +{ + uint32_t i; + USBD_T *pUSBD; + + if((__PC() & NS_OFFSET) == NS_OFFSET) + { + pUSBD = USBD_NS; + } + else + { + pUSBD = USBD; + } + + /* Reset all variables for protocol */ + g_USBD_pu8CtrlInPointer = 0; + g_USBD_u32CtrlInSize = 0UL; + g_USBD_pu8CtrlOutPointer = 0; + g_USBD_u32CtrlOutSize = 0UL; + g_USBD_u32CtrlOutSizeLimit = 0UL; + g_USBD_u32EpStallLock = 0UL; + memset(g_USBD_au8SetupPacket, 0, 8UL); + + /* Reset PID DATA0 */ + for(i = 0UL; i < USBD_MAX_EP; i++) + { + pUSBD->EP[i].CFG &= ~USBD_CFG_DSQSYNC_Msk; + } + + /* Reset USB device address */ + USBD_SET_ADDR(0UL); +} + +/** + * @brief USBD Set Vendor Request + * + * @param[in] pfnVendorReq Vendor Request Callback Function + * + * @return None + * + * @details This function is used to set USBD vendor request callback function + */ +void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq) +{ + g_USBD_pfnVendorRequest = pfnVendorReq; +} + +/** + * @brief The callback function which called when get SET CONFIGURATION request + * + * @param[in] pfnSetConfigCallback Callback function pointer for SET CONFIGURATION request + * + * @return None + * + * @details This function is used to set the callback function which will be called at SET CONFIGURATION request. + */ +void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback) +{ + g_USBD_pfnSetConfigCallback = pfnSetConfigCallback; +} + + +/** + * @brief EP stall lock function to avoid stall clear by USB SET FEATURE request. + * + * @param[in] u32EpBitmap Use bitmap to select which endpoints will be locked + * + * @return None + * + * @details This function is used to lock relative endpoint to avoid stall clear by SET FEATURE request. + * If ep stall locked, user needs to reset USB device or re-configure device to clear it. + */ +void USBD_LockEpStall(uint32_t u32EpBitmap) +{ + g_USBD_u32EpStallLock = u32EpBitmap; +} + +/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USBD_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +#ifdef __cplusplus +} +#endif + +/*** (C) COPYRIGHT 2018-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/usci_i2c.c b/arch/riscv32/fe310/src/StdDriver/src/usci_i2c.c new file mode 100644 index 00000000..cf17ad41 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/usci_i2c.c @@ -0,0 +1,1661 @@ +/****************************************************************************//** + * @file usci_i2c.c + * @version V3.00 + * $Revision: 1 $ + * $Date: 16/07/07 7:50p $ + * @brief M2351 series USCI I2C(UI2C) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_I2C_Driver USCI_I2C Driver + @{ +*/ + + +/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions + @{ +*/ + +/** + * @brief This function makes USCI_I2C module be ready and set the wanted bus clock + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Enable USCI_I2C module and configure USCI_I2C module(bus clock, data format). + */ +uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */ + + /* Enable USCI_I2C protocol */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; + ui2c->CTL = 4u << UI2C_CTL_FUNMODE_Pos; + + /* Data format configuration */ + /* 8 bit data length */ + ui2c->LINECTL &= ~UI2C_LINECTL_DWIDTH_Msk; + ui2c->LINECTL |= 8u << UI2C_LINECTL_DWIDTH_Pos; + + /* MSB data format */ + ui2c->LINECTL &= ~UI2C_LINECTL_LSB_Msk; + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + ui2c->PROTCTL |= UI2C_PROTCTL_PROTEN_Msk; + + return (u32Pclk / ((u32ClkDiv + 1u) << 1u)); +} + +/** + * @brief This function closes the USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Close USCI_I2C protocol function. + */ +void UI2C_Close(UI2C_T *ui2c) +{ + /* Disable USCI_I2C function */ + ui2c->CTL &= ~UI2C_CTL_FUNMODE_Msk; +} + +/** + * @brief This function clears the time-out flag + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details Clear time-out flag when time-out flag is set. + */ +void UI2C_ClearTimeoutFlag(UI2C_T *ui2c) +{ + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; +} + +/** + * @brief This function sets the control bit of the USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Start Set START bit to USCI_I2C module. + * @param[in] u8Stop Set STOP bit to USCI_I2C module. + * @param[in] u8Ptrg Set PTRG bit to USCI_I2C module. + * @param[in] u8Ack Set ACK bit to USCI_I2C module. + * + * @return None + * + * @details The function set USCI_I2C control bit of USCI_I2C bus protocol. + */ +void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack) +{ + uint32_t u32Reg = 0u; + uint32_t u32Val = ui2c->PROTCTL & ~(UI2C_PROTCTL_STA_Msk | UI2C_PROTCTL_STO_Msk | UI2C_PROTCTL_AA_Msk); + + if(u8Start) + { + u32Reg |= UI2C_PROTCTL_STA_Msk; + } + if(u8Stop) + { + u32Reg |= UI2C_PROTCTL_STO_Msk; + } + if(u8Ptrg) + { + u32Reg |= UI2C_PROTCTL_PTRG_Msk; + } + if(u8Ack) + { + u32Reg |= UI2C_PROTCTL_AA_Msk; + } + ui2c->PROTCTL = u32Val | u32Reg; +} + +/** + * @brief This function disables the interrupt of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to an interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details The function is used to disable USCI_I2C bus interrupt events. + */ +void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Disable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_TOIEN_Msk; + } + /* Disable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STARIEN_Msk; + } + /* Disable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_STORIEN_Msk; + } + /* Disable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_NACKIEN_Msk; + } + /* Disable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ARBLOIEN_Msk; + } + + /* Disable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ERRIEN_Msk; + } + /* Disable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN &= ~UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function enables the interrupt of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * @return None + * + * @details The function is used to enable USCI_I2C bus interrupt events. + */ +void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Enable time-out interrupt flag */ + if((u32Mask & UI2C_TO_INT_MASK) == UI2C_TO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_TOIEN_Msk; + } + /* Enable start condition received interrupt flag */ + if((u32Mask & UI2C_STAR_INT_MASK) == UI2C_STAR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STARIEN_Msk; + } + /* Enable stop condition received interrupt flag */ + if((u32Mask & UI2C_STOR_INT_MASK) == UI2C_STOR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_STORIEN_Msk; + } + /* Enable non-acknowledge interrupt flag */ + if((u32Mask & UI2C_NACK_INT_MASK) == UI2C_NACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_NACKIEN_Msk; + } + /* Enable arbitration lost interrupt flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) == UI2C_ARBLO_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ARBLOIEN_Msk; + } + /* Enable error interrupt flag */ + if((u32Mask & UI2C_ERR_INT_MASK) == UI2C_ERR_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ERRIEN_Msk; + } + /* Enable acknowledge interrupt flag */ + if((u32Mask & UI2C_ACK_INT_MASK) == UI2C_ACK_INT_MASK) + { + ui2c->PROTIEN |= UI2C_PROTIEN_ACKIEN_Msk; + } +} + +/** + * @brief This function returns the real bus clock of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details The function returns the actual USCI_I2C module bus clock. + */ +uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c) +{ + uint32_t u32Divider; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + u32Divider = (ui2c->BRGEN & UI2C_BRGEN_CLKDIV_Msk) >> UI2C_BRGEN_CLKDIV_Pos; + + return (u32Pclk / ((u32Divider + 1u) << 1u)); +} + +/** + * @brief This function sets bus clock frequency of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32BusClock The target bus speed of USCI_I2C module. + * + * @return Actual USCI_I2C bus clock frequency. + * + * @details Use this function set USCI_I2C bus clock frequency and return actual bus clock. + */ +uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((ui2c == UI2C1) || (ui2c == UI2C1_NS)) + { + u32Pclk = CLK_GetPCLK1Freq(); + } + else + { + u32Pclk = CLK_GetPCLK0Freq(); + } + u32ClkDiv = (uint32_t)((((((u32Pclk / 2u) * 10u) / (u32BusClock)) + 5u) / 10u) - 1u); /* Compute proper divider for USCI_I2C clock */ + + /* Set USCI_I2C bus clock */ + ui2c->BRGEN &= ~UI2C_BRGEN_CLKDIV_Msk; + ui2c->BRGEN |= (u32ClkDiv << UI2C_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1u) << 1u)); +} + +/** + * @brief This function gets the interrupt flag of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details Use this function to get USCI_I2C interrupt flag when module occurs interrupt event. + */ +uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0U; + uint32_t u32TmpValue; + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_TOIF_Msk; + /* Check Time-out Interrupt Flag */ + if((u32Mask & UI2C_TO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_TO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STARIF_Msk; + /* Check Start Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STAR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STAR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_STORIF_Msk; + /* Check Stop Condition Received Interrupt Flag */ + if((u32Mask & UI2C_STOR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_STOR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_NACKIF_Msk; + /* Check Non-Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_NACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_NACK_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ARBLOIF_Msk; + /* Check Arbitration Lost Interrupt Flag */ + if((u32Mask & UI2C_ARBLO_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ARBLO_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ERRIF_Msk; + /* Check Error Interrupt Flag */ + if((u32Mask & UI2C_ERR_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ERR_INT_MASK; + } + + u32TmpValue = ui2c->PROTSTS & UI2C_PROTSTS_ACKIF_Msk; + /* Check Acknowledge Interrupt Flag */ + if((u32Mask & UI2C_ACK_INT_MASK) && (u32TmpValue)) + { + u32IntFlag |= UI2C_ACK_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief This function clears the interrupt flag of USCI_I2C module. + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It is combination of: + * - \ref UI2C_TO_INT_MASK + * - \ref UI2C_STAR_INT_MASK + * - \ref UI2C_STOR_INT_MASK + * - \ref UI2C_NACK_INT_MASK + * - \ref UI2C_ARBLO_INT_MASK + * - \ref UI2C_ERR_INT_MASK + * - \ref UI2C_ACK_INT_MASK + * + * @return None + * + * @details Use this function to clear USCI_I2C interrupt flag when module occurs interrupt event and set flag. + */ +void UI2C_ClearIntFlag(UI2C_T *ui2c, uint32_t u32Mask) +{ + /* Clear Time-out Interrupt Flag */ + if(u32Mask & UI2C_TO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_TOIF_Msk; + } + /* Clear Start Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STAR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STARIF_Msk; + } + /* Clear Stop Condition Received Interrupt Flag */ + if(u32Mask & UI2C_STOR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_STORIF_Msk; + } + /* Clear Non-Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_NACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_NACKIF_Msk; + } + /* Clear Arbitration Lost Interrupt Flag */ + if(u32Mask & UI2C_ARBLO_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ARBLOIF_Msk; + } + /* Clear Error Interrupt Flag */ + if(u32Mask & UI2C_ERR_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ERRIF_Msk; + } + /* Clear Acknowledge Interrupt Flag */ + if(u32Mask & UI2C_ACK_INT_MASK) + { + ui2c->PROTSTS = UI2C_PROTSTS_ACKIF_Msk; + } +} + +/** + * @brief This function returns the data stored in data register of USCI_I2C module. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return USCI_I2C data. + * + * @details To read a byte data from USCI_I2C module receive data register. + */ +uint32_t UI2C_GetData(UI2C_T *ui2c) +{ + return (ui2c->RXDAT); +} + +/** + * @brief This function writes a byte data to data register of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8Data The data which will be written to data register of USCI_I2C module. + * + * @return None + * + * @details To write a byte data to transmit data register to transmit data. + */ +void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data) +{ + ui2c->TXDAT = u8Data; +} + +/** + * @brief Configure slave address and enable GC mode + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channel number [0/1] + * @param[in] u16SlaveAddr The slave address. + * @param[in] u8GCMode GC mode enable or not. Valid values are: + * - \ref UI2C_GCMODE_ENABLE + * - \ref UI2C_GCMODE_DISABLE + * + * @return None + * + * @details To configure USCI_I2C module slave address and GC mode. + */ +void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode) +{ + if(u8SlaveNo) + { + ui2c->DEVADDR1 = u16SlaveAddr; + } + else + { + ui2c->DEVADDR0 = u16SlaveAddr; + } + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_GCFUNC_Msk) | u8GCMode; +} + +/** + * @brief Configure the mask bit of slave address. + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveNo Slave channle number [0/1] + * @param[in] u16SlaveAddrMask The slave address mask. + * + * @return None + * + * @details To configure USCI_I2C module slave address mask bit. + * @note The corresponding address bit is "Don't Care". + */ +void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask) +{ + if(u8SlaveNo) + { + ui2c->ADDRMSK1 = u16SlaveAddrMask; + } + else + { + ui2c->ADDRMSK0 = u16SlaveAddrMask; + } +} + +/** + * @brief This function enables time-out function and configures timeout counter + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u32TimeoutCnt Timeout counter. Valid values are between 0~0x3FF. + * + * @return None + * + * @details To enable USCI_I2C bus time-out function and set time-out counter. + */ +void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt) +{ + ui2c->PROTCTL = (ui2c->PROTCTL & ~UI2C_PROTCTL_TOCNT_Msk) | (u32TimeoutCnt << UI2C_PROTCTL_TOCNT_Pos); + ui2c->BRGEN = (ui2c->BRGEN & ~UI2C_BRGEN_TMCNTSRC_Msk) | UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function disables time-out function + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C bus time-out function. + */ +void UI2C_DisableTimeout(UI2C_T *ui2c) +{ + ui2c->PROTCTL &= ~UI2C_PROTCTL_TOCNT_Msk; + ui2c->BRGEN &= ~UI2C_BRGEN_TMCNTEN_Msk; +} + +/** + * @brief This function enables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8WakeupMode The wake-up mode selection. Valid values are: + * - \ref UI2C_DATA_TOGGLE_WK + * - \ref UI2C_ADDR_MATCH_WK + * + * @return None + * + * @details To enable USCI_I2C module wake-up function. + */ +void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode) +{ + ui2c->WKCTL = (ui2c->WKCTL & ~UI2C_WKCTL_WKADDREN_Msk) | (u8WakeupMode | UI2C_WKCTL_WKEN_Msk); +} + +/** + * @brief This function disables the wakeup function of USCI_I2C module + * + * @param[in] ui2c The pointer of the specified USCI_I2C module. + * + * @return None + * + * @details To disable USCI_I2C module wake-up function. + */ +void UI2C_DisableWakeup(UI2C_T *ui2c) +{ + ui2c->WKCTL &= ~UI2C_WKCTL_WKEN_Msk; +} + +/** + * @brief Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master write a byte data to Slave. + * + */ + +uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + +/** + * @brief Write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master write multi bytes data to Slave. + * + */ + +uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify a byte register address and write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] data A byte data to write it to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify a address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); /* return (Success)/(Fail) status */ +} + + +/** + * @brief Specify a byte register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 byte) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else + { + if(u32txLen < u32wLen) + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Specify two bytes register address and Write a byte to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 byte) of data write to + * @param[in] data Write a byte data to Slave + * + * @retval 0 Write data success + * @retval 1 Write data fail, or bus occurs error events + * + * @details The function is used for USCI_I2C Master specify two bytes address that data write to in Slave. + * + */ + +uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(u32txLen == 0U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 1U) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u32txLen++; + } + else if(u32txLen == 2U) + { + UI2C_SET_DATA(ui2c, data); /* Write data to UI2C_TXDAT */ + u32txLen++; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return (u8Err | u8Xfering); +} + + +/** + * @brief Specify two bytes register address and write multi bytes to Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data write to + * @param[in] *data Pointer to array to write data to Slave + * @param[in] u32wLen How many bytes need to write to Slave + * + * @return A length of how many bytes have been transmitted. + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data write to in Slave. + * + */ + +uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *data, uint32_t u32wLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32txLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte data address to UI2C_TXDAT */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte data address to UI2C_TXDAT */ + u8Addr = 0; + } + else + { + if(u32txLen < u32wLen) + { + UI2C_SET_DATA(ui2c, data[u32txLen++]); /* Write data to UI2C_TXDAT */ + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + } + } + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_CTL register */ + } + + return u32txLen; /* Return bytes length that have been transmitted */ +} + +/** + * @brief Read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master to read a byte data from Slave. + * + */ +uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + eEvent = MASTER_READ_DATA; + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Err = 1U; + } + else + { + rdata = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; + + return rdata; /* Return read data */ +} + + +/** + * @brief Read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master to read multi data bytes from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < (u32rLen - 1U)) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (unsigned char) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + + +/** + * @brief Specify a byte register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address(1 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify a byte address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify a byte register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u8DataAddr Specify a address (1 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify a byte address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, u8DataAddr); /* Write data address of register */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + else if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + /* SLA+R ACK */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/** + * @brief Specify two bytes register address and read a byte from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address(2 byte) of data read from + * + * @return Read a byte data from Slave + * + * @details The function is used for USCI_I2C Master specify two bytes address that a data byte read from Slave. + * + * + */ +uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) +{ + uint8_t u8Xfering = 1U, u8Err = 0U, rdata = 0U, u8Addr = 1U, u8Ctrl = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else + { + /* SLA+R ACK */ + u8Ctrl = UI2C_CTL_PTRG; + eEvent = MASTER_READ_DATA; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + { + rdata = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + } + else + { + u8Err = 1U; + } + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + u8Err = 1U; + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + if(u8Err) + rdata = 0U; /* If occurs error, return 0 */ + + return rdata; /* Return read data */ +} + +/** + * @brief Specify two bytes register address and read multi bytes from Slave + * + * @param[in] *ui2c The pointer of the specified USCI_I2C module. + * @param[in] u8SlaveAddr Access Slave address(7-bit) + * @param[in] u16DataAddr Specify a address (2 bytes) of data read from + * @param[out] *rdata Point to array to store data from Slave + * @param[in] u32rLen How many bytes need to read from Slave + * + * @return A length of how many bytes have been received + * + * @details The function is used for USCI_I2C Master specify two bytes address that multi data bytes read from Slave. + * + * + */ +uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen) +{ + uint8_t u8Xfering = 1U, u8Addr = 1U, u8Ctrl = 0U; + uint32_t u32rxLen = 0U; + enum UI2C_MASTER_EVENT eEvent = MASTER_SEND_START; + + UI2C_START(ui2c); /* Send START */ + + while(u8Xfering) + { + while(!(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U)); /* Wait UI2C new status occur */ + + switch(UI2C_GET_PROT_STATUS(ui2c) & 0x3F00U) + { + case UI2C_PROTSTS_STARIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STARIF_Msk); /* Clear START INT Flag */ + + if(eEvent == MASTER_SEND_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x00U)); /* Write SLA+W to Register UI2C_TXDAT */ + eEvent = MASTER_SEND_ADDRESS; + } + else if(eEvent == MASTER_SEND_REPEAT_START) + { + UI2C_SET_DATA(ui2c, ((uint8_t)(u8SlaveAddr << 1U) | 0x01U)); /* Write SLA+R to Register TXDAT */ + eEvent = MASTER_SEND_H_RD_ADDRESS; + } + + u8Ctrl = UI2C_CTL_PTRG; + break; + + case UI2C_PROTSTS_ACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_ACKIF_Msk); /* Clear ACK INT Flag */ + + if(eEvent == MASTER_SEND_ADDRESS) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFF00U) >> 8U); /* Write Hi byte address of register */ + eEvent = MASTER_SEND_DATA; + } + else if(eEvent == MASTER_SEND_DATA) + { + if(u8Addr) + { + UI2C_SET_DATA(ui2c, (uint8_t)(u16DataAddr & 0xFFU)); /* Write Lo byte address of register */ + u8Addr = 0; + } + else + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STA); /* Send repeat START signal */ + eEvent = MASTER_SEND_REPEAT_START; + } + } + else if(eEvent == MASTER_SEND_H_RD_ADDRESS) + { + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + eEvent = MASTER_READ_DATA; + } + else + { + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + if(u32rxLen < u32rLen - 1U) + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_AA); + else + u8Ctrl = UI2C_CTL_PTRG; + } + + break; + + case UI2C_PROTSTS_NACKIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_NACKIF_Msk); /* Clear NACK INT Flag */ + + if(eEvent == MASTER_READ_DATA) + rdata[u32rxLen++] = (uint8_t) UI2C_GET_DATA(ui2c); /* Receive Data */ + + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + + break; + + case UI2C_PROTSTS_STORIF_Msk: + UI2C_CLR_PROT_INT_FLAG(ui2c, UI2C_PROTSTS_STORIF_Msk); /* Clear STOP INT Flag */ + u8Ctrl = UI2C_CTL_PTRG; /* Clear SI */ + u8Xfering = 0U; + break; + + case UI2C_PROTSTS_ARBLOIF_Msk: /* Arbitration Lost */ + default: /* Unknow status */ + u8Ctrl = (UI2C_CTL_PTRG | UI2C_CTL_STO); /* Clear SI and send STOP */ + break; + } + + UI2C_SET_CONTROL_REG(ui2c, u8Ctrl); /* Write controlbit to UI2C_PROTCTL register */ + } + + return u32rxLen; /* Return bytes length that have been received */ +} + +/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_I2C_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/usci_spi.c b/arch/riscv32/fe310/src/StdDriver/src/usci_spi.c new file mode 100644 index 00000000..dd558fed --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/usci_spi.c @@ -0,0 +1,636 @@ +/****************************************************************************//** + * @file usci_spi.c + * @version V3.00 + * @brief M2351 series USCI_SPI driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_SPI_Driver USCI_SPI Driver + @{ +*/ + + +/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions + @{ +*/ + +/** + * @brief This function make USCI_SPI module be ready to transfer. + * By default, the USCI_SPI transfer sequence is MSB first, the slave selection + * signal is active low and the automatic slave select function is disabled. In + * Slave mode, the u32BusClock must be NULL and the USCI_SPI clock + * divider setting will be 0. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are: + * - \ref USPI_SLAVE + * - \ref USPI_MASTER + * @param[in] u32SPIMode Decide the transfer timing. Valid values are: + * - \ref USPI_MODE_0 + * - \ref USPI_MODE_1 + * - \ref USPI_MODE_2 + * - \ref USPI_MODE_3 + * @param[in] u32DataWidth The data width of a USCI_SPI transaction. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv = 0UL; + uint32_t u32Pclk; + uint32_t u32RetValue = 0UL; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + if(u32BusClock != 0UL) + { + u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */ + } + + /* Enable USCI_SPI protocol */ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; + uspi->CTL = 1UL << USPI_CTL_FUNMODE_Pos; + + /* Data format configuration */ + if(u32DataWidth == 16UL) + { + u32DataWidth = 0UL; + } + uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk; + uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos); + + /* MSB data format */ + uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk; + + /* Set slave selection signal active low */ + if(u32MasterSlave == USPI_MASTER) + { + uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk; + } + else + { + uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk; + } + + /* Set operating mode and transfer timing */ + uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk); + uspi->PROTCTL |= (u32MasterSlave | u32SPIMode); + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk; + + if(u32BusClock != 0UL) + { + u32RetValue = (u32Pclk / ((u32ClkDiv + 1UL) << 1UL)); + } + else + { + u32RetValue = 0UL; + } + + return u32RetValue; +} + +/** + * @brief Disable USCI_SPI function mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_Close(USPI_T *uspi) +{ + uspi->CTL &= ~USPI_CTL_FUNMODE_Msk; +} + +/** + * @brief Clear Rx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearRxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk; +} + +/** + * @brief Clear Tx buffer. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_ClearTxBuf(USPI_T *uspi) +{ + uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk; +} + +/** + * @brief Disable the automatic slave select function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableAutoSS(USPI_T *uspi) +{ + uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk); +} + +/** + * @brief Enable the automatic slave select function. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32SSPinMask This parameter is not used. + * @param[in] u32ActiveLevel The active level of slave select signal. Valid values are: + * - \ref USPI_SS_ACTIVE_HIGH + * - \ref USPI_SS_ACTIVE_LOW + * @return None + */ +void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel) +{ + (void)u32SSPinMask; + uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel; + uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk; +} + +/** + * @brief Set the USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32BusClock The expected frequency of USCI_SPI bus clock. + * @return Actual frequency of USCI_SPI peripheral clock. + */ +uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock) +{ + uint32_t u32ClkDiv; + uint32_t u32Pclk; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32Pclk = CLK_GetPCLK0Freq(); + } + else + { + u32Pclk = CLK_GetPCLK1Freq(); + } + + u32ClkDiv = (uint32_t)((((((u32Pclk / 2UL) * 10UL) / (u32BusClock)) + 5UL) / 10UL) - 1UL); /* Compute proper divider for USCI_SPI clock */ + + /* Set USCI_SPI bus clock */ + uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk; + uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos); + + return (u32Pclk / ((u32ClkDiv + 1UL) << 1UL)); +} + +/** + * @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return Actual USCI_SPI bus clock frequency. + */ +uint32_t USPI_GetBusClock(USPI_T *uspi) +{ + uint32_t u32ClkDiv, u32BusClk; + + u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos; + + if((uspi == USPI0) || (uspi == USPI0_NS)) + { + u32BusClk = (CLK_GetPCLK0Freq() / ((u32ClkDiv + 1UL) << 1UL)); + } + else + { + u32BusClk = (CLK_GetPCLK1Freq() / ((u32ClkDiv + 1UL) << 1UL)); + } + + return u32BusClk; +} + +/** + * @brief Enable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be enabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Enable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk; + } + + /* Enable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk; + } + + /* Enable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk; + } + + /* Enable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk; + } + + /* Enable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk; + } +} + +/** + * @brief Disable related interrupts specified by u32Mask parameter. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt bit. + * This parameter decides which interrupts will be disabled. Valid values are: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask) +{ + /* Disable slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk; + } + + /* Disable slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk; + } + + /* Disable slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk; + } + + /* Disable slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK) + { + uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk; + } + + /* Disable TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK) + { + uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK) + { + uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk; + } +} + +/** + * @brief Get interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return Interrupt flags of selected sources. + */ +uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32ProtStatus, u32BufStatus; + uint32_t u32IntFlag = 0UL; + + u32ProtStatus = uspi->PROTSTS; + u32BufStatus = uspi->BUFSTS; + + /* Check slave selection signal inactive interrupt flag */ + if((u32Mask & USPI_SSINACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSINAIF_Msk)) + { + u32IntFlag |= USPI_SSINACT_INT_MASK; + } + + /* Check slave selection signal active interrupt flag */ + if((u32Mask & USPI_SSACT_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SSACTIF_Msk)) + { + u32IntFlag |= USPI_SSACT_INT_MASK; + } + + /* Check slave time-out interrupt flag */ + if((u32Mask & USPI_SLVTO_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVTOIF_Msk)) + { + u32IntFlag |= USPI_SLVTO_INT_MASK; + } + + /* Check slave bit count error interrupt flag */ + if((u32Mask & USPI_SLVBE_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_SLVBEIF_Msk)) + { + u32IntFlag |= USPI_SLVBE_INT_MASK; + } + + /* Check TX under run interrupt flag */ + if((u32Mask & USPI_TXUDR_INT_MASK) && (u32BufStatus & USPI_BUFSTS_TXUDRIF_Msk)) + { + u32IntFlag |= USPI_TXUDR_INT_MASK; + } + + /* Check RX overrun interrupt flag */ + if((u32Mask & USPI_RXOV_INT_MASK) && (u32BufStatus & USPI_BUFSTS_RXOVIF_Msk)) + { + u32IntFlag |= USPI_RXOV_INT_MASK; + } + + /* Check TX start interrupt flag */ + if((u32Mask & USPI_TXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXSTIF_Msk)) + { + u32IntFlag |= USPI_TXST_INT_MASK; + } + + /* Check TX end interrupt flag */ + if((u32Mask & USPI_TXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_TXENDIF_Msk)) + { + u32IntFlag |= USPI_TXEND_INT_MASK; + } + + /* Check RX start interrupt flag */ + if((u32Mask & USPI_RXST_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXSTIF_Msk)) + { + u32IntFlag |= USPI_RXST_INT_MASK; + } + + /* Check RX end interrupt flag */ + if((u32Mask & USPI_RXEND_INT_MASK) && (u32ProtStatus & USPI_PROTSTS_RXENDIF_Msk)) + { + u32IntFlag |= USPI_RXEND_INT_MASK; + } + + return u32IntFlag; +} + +/** + * @brief Clear interrupt flag. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref USPI_SSINACT_INT_MASK + * - \ref USPI_SSACT_INT_MASK + * - \ref USPI_SLVTO_INT_MASK + * - \ref USPI_SLVBE_INT_MASK + * - \ref USPI_TXUDR_INT_MASK + * - \ref USPI_RXOV_INT_MASK + * - \ref USPI_TXST_INT_MASK + * - \ref USPI_TXEND_INT_MASK + * - \ref USPI_RXST_INT_MASK + * - \ref USPI_RXEND_INT_MASK + * @return None + */ +void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask) +{ + /* Clear slave selection signal inactive interrupt flag */ + if(u32Mask & USPI_SSINACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk; + } + + /* Clear slave selection signal active interrupt flag */ + if(u32Mask & USPI_SSACT_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk; + } + + /* Clear slave time-out interrupt flag */ + if(u32Mask & USPI_SLVTO_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk; + } + + /* Clear slave bit count error interrupt flag */ + if(u32Mask & USPI_SLVBE_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk; + } + + /* Clear TX under run interrupt flag */ + if(u32Mask & USPI_TXUDR_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk; + } + + /* Clear RX overrun interrupt flag */ + if(u32Mask & USPI_RXOV_INT_MASK) + { + uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk; + } + + /* Clear TX start interrupt flag */ + if(u32Mask & USPI_TXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk; + } + + /* Clear TX end interrupt flag */ + if(u32Mask & USPI_TXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk; + } + + /* Clear RX start interrupt flag */ + if(u32Mask & USPI_RXST_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk; + } + + /* Clear RX end interrupt flag */ + if(u32Mask & USPI_RXEND_INT_MASK) + { + uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk; + } +} + +/** + * @brief Get USCI_SPI status. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @param[in] u32Mask The combination of all related sources. + * Each bit corresponds to a source. + * This parameter decides which flags will be read. It is combination of: + * - \ref USPI_BUSY_MASK + * - \ref USPI_RX_EMPTY_MASK + * - \ref USPI_RX_FULL_MASK + * - \ref USPI_TX_EMPTY_MASK + * - \ref USPI_TX_FULL_MASK + * - \ref USPI_SSLINE_STS_MASK + * @return Flags of selected sources. + */ +uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask) +{ + uint32_t u32ProtStatus, u32BufStatus; + uint32_t u32Flag = 0UL; + + u32ProtStatus = uspi->PROTSTS; + u32BufStatus = uspi->BUFSTS; + + /* Check busy status */ + if((u32Mask & USPI_BUSY_MASK) && (u32ProtStatus & USPI_PROTSTS_BUSY_Msk)) + { + u32Flag |= USPI_BUSY_MASK; + } + + /* Check RX empty flag */ + if((u32Mask & USPI_RX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_RXEMPTY_Msk)) + { + u32Flag |= USPI_RX_EMPTY_MASK; + } + + /* Check RX full flag */ + if((u32Mask & USPI_RX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_RXFULL_Msk)) + { + u32Flag |= USPI_RX_FULL_MASK; + } + + /* Check TX empty flag */ + if((u32Mask & USPI_TX_EMPTY_MASK) && (u32BufStatus & USPI_BUFSTS_TXEMPTY_Msk)) + { + u32Flag |= USPI_TX_EMPTY_MASK; + } + + /* Check TX full flag */ + if((u32Mask & USPI_TX_FULL_MASK) && (u32BufStatus & USPI_BUFSTS_TXFULL_Msk)) + { + u32Flag |= USPI_TX_FULL_MASK; + } + + /* Check USCI_SPI_SS line status */ + if((u32Mask & USPI_SSLINE_STS_MASK) && (u32ProtStatus & USPI_PROTSTS_SSLINE_Msk)) + { + u32Flag |= USPI_SSLINE_STS_MASK; + } + + return u32Flag; +} + +/** + * @brief Enable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_EnableWakeup(USPI_T *uspi) +{ + uspi->WKCTL |= USPI_WKCTL_WKEN_Msk; +} + +/** + * @brief Disable USCI_SPI Wake-up Function. + * @param[in] uspi The pointer of the specified USCI_SPI module. + * @return None + */ +void USPI_DisableWakeup(USPI_T *uspi) +{ + uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk; +} + +/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_SPI_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ diff --git a/arch/riscv32/fe310/src/StdDriver/src/usci_uart.c b/arch/riscv32/fe310/src/StdDriver/src/usci_uart.c new file mode 100644 index 00000000..afac669c --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/usci_uart.c @@ -0,0 +1,733 @@ +/**************************************************************************//** + * @file usci_uart.c + * @version V3.00 + * @brief M2351 series USCI UART (UUART) driver source file + * + * @note + * SPDX-License-Identifier: Apache-2.0 + * Copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ + +#include +#include "NuMicro.h" + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup USCI_UART_Driver USCI_UART Driver + @{ +*/ + +/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions + @{ +*/ + +/** + * @brief Clear USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be cleared. It could be the combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + + if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk; + } + + if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */ + { + uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk); + } + + if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */ + { + uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk; + } + + if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk; + } + + if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk; + } + + if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk; + } + + if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */ + { + uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk; + } + +} + + +/** + * @brief Get USCI_UART specified interrupt flag + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt sources. + * Each bit corresponds to a interrupt source. + * This parameter decides which interrupt flags will be read. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return Interrupt flags of selected sources. + * + * @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter. + */ + +uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask) +{ + uint32_t u32IntFlag = 0ul; + uint32_t u32Tmp1, u32Tmp2; + + /* Check Auto-baud Rate Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_ABR_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_ABR_INT_MASK; + } + + /* Check Receive Line Status Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RLS_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RLS_INT_MASK; + } + + /* Check Receive Buffer Over-run Error Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_BUF_RXOV_INT_MASK); + u32Tmp2 = (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_BUF_RXOV_INT_MASK; + } + + /* Check Transmit Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXST_INT_MASK; + } + + /* Check Transmit End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_TXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_TXEND_INT_MASK; + } + + /* Check Receive Start Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXST_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXST_INT_MASK; + } + + /* Check Receive End Interrupt Flag */ + u32Tmp1 = (u32Mask & UUART_RXEND_INT_MASK); + u32Tmp2 = (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk); + if(u32Tmp1 && u32Tmp2) + { + u32IntFlag |= UUART_RXEND_INT_MASK; + } + + return u32IntFlag; +} + + +/** + * @brief Disable USCI_UART function mode + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART function mode. + */ +void UUART_Close(UUART_T* uuart) +{ + uuart->CTL = 0UL; +} + + +/** + * @brief Disable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be disabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter. + */ +void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask) +{ + + /* Disable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk; + } + + /* Disable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk; + } + + /* Disable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Disable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk; + } + + /* Disable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk; + } + + /* Disable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk; + } + + /* Disable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Enable interrupt function. + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32Mask The combination of all related interrupt enable bits. + * Each bit corresponds to a interrupt enable bit. + * This parameter decides which interrupts will be enabled. It is combination of: + * - \ref UUART_ABR_INT_MASK + * - \ref UUART_RLS_INT_MASK + * - \ref UUART_BUF_RXOV_INT_MASK + * - \ref UUART_TXST_INT_MASK + * - \ref UUART_TXEND_INT_MASK + * - \ref UUART_RXST_INT_MASK + * - \ref UUART_RXEND_INT_MASK + * + * @return None + * + * @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter.. + */ +void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask) +{ + /* Enable Auto-baud rate interrupt flag */ + if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk; + } + + /* Enable receive line status interrupt flag */ + if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK) + { + uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk; + } + + /* Enable RX overrun interrupt flag */ + if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK) + { + uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk; + } + + /* Enable TX start interrupt flag */ + if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk; + } + + /* Enable TX end interrupt flag */ + if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk; + } + + /* Enable RX start interrupt flag */ + if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk; + } + + /* Enable RX end interrupt flag */ + if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK) + { + uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk; + } +} + + +/** + * @brief Open and set USCI_UART function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The baud rate of USCI_UART module. + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to enable USCI_UART function and set baud-rate. + */ +uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if((uuart == UUART0) || (uuart == UUART0_NS)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + u32Tmp = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + } + + /* Enable USCI_UART protocol */ + uuart->CTL &= ~UUART_CTL_FUNMODE_Msk; + uuart->CTL = 2ul << UUART_CTL_FUNMODE_Pos; + + /* Set USCI_UART line configuration */ + uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk; + uuart->DATIN0 = (2ul << UUART_DATIN0_EDGEDET_Pos); /* Set falling edge detection */ + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos); + + uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Read USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8RxBuf The buffer to receive the data of receive buffer. + * @param[in] u32ReadBytes The read bytes number of data. + * + * @return Receive byte count + * + * @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf. + */ +uint32_t UUART_Read(UUART_T* uuart, uint8_t pu8RxBuf[], uint32_t u32ReadBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count < u32ReadBytes; u32Count++) + { + u32delayno = 0ul; + + while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + pu8RxBuf[u32Count] = (uint8_t)uuart->RXDAT; /* Get Data from USCI RX */ + } + + return u32Count; + +} + + +/** + * @brief Set USCI_UART line configuration + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32baudrate The register value of baud rate of USCI_UART module. + * If u32baudrate = 0, USCI_UART baud rate will not change. + * @param[in] u32data_width The data length of USCI_UART module. + * - \ref UUART_WORD_LEN_6 + * - \ref UUART_WORD_LEN_7 + * - \ref UUART_WORD_LEN_8 + * - \ref UUART_WORD_LEN_9 + * @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module. + * - \ref UUART_PARITY_NONE + * - \ref UUART_PARITY_ODD + * - \ref UUART_PARITY_EVEN + * @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module. + * - \ref UUART_STOP_BIT_1 + * - \ref UUART_STOP_BIT_2 + * + * @return Real baud rate of USCI_UART module. + * + * @details This function use to config USCI_UART line setting. + */ +uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits) +{ + uint32_t u32PCLKFreq, u32PDSCnt, u32DSCnt, u32ClkDiv; + uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt; + uint32_t u32Div; + + /* Get PCLK frequency */ + if((uuart == UUART0) || (uuart == UUART0_NS)) + { + u32PCLKFreq = CLK_GetPCLK0Freq(); + } + else /* UUART1 */ + { + u32PCLKFreq = CLK_GetPCLK1Freq(); + } + + if(u32baudrate != 0ul) + { + + /* Calculate baud rate divider */ + u32Div = u32PCLKFreq / u32baudrate; + u32Tmp = (u32PCLKFreq / u32Div) - u32baudrate; + u32Tmp2 = u32baudrate - (u32PCLKFreq / (u32Div + 1ul)); + + if(u32Tmp >= u32Tmp2) u32Div = u32Div + 1ul; + + if(u32Div >= 65536ul) + { + + /* Set the smallest baud rate that USCI_UART can generate */ + u32PDSCnt = 0x4ul; + u32MinDSCnt = 0x10ul; + u32MinClkDiv = 0x400ul; + + } + else + { + + u32Tmp = 0x400ul * 0x10ul; + for(u32PDSCnt = 1ul; u32PDSCnt <= 0x04ul; u32PDSCnt++) + { + if(u32Div <= (u32Tmp * u32PDSCnt)) break; + } + + if(u32PDSCnt > 0x4ul) u32PDSCnt = 0x4ul; + + u32Div = u32Div / u32PDSCnt; + + /* Find best solution */ + u32Min = (uint32_t) - 1; + u32MinDSCnt = 0ul; + u32MinClkDiv = 0ul; + + for(u32DSCnt = 6ul; u32DSCnt <= 0x10ul; u32DSCnt++) /* DSCNT could be 0x5~0xF */ + { + u32ClkDiv = u32Div / u32DSCnt; + + if(u32ClkDiv > 0x400ul) + { + u32ClkDiv = 0x400ul; + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = u32Tmp + 1ul; + } + else + { + u32Tmp = u32Div - (u32ClkDiv * u32DSCnt); + u32Tmp2 = ((u32ClkDiv + 1ul) * u32DSCnt) - u32Div; + } + + if(u32Tmp >= u32Tmp2) + { + u32ClkDiv = u32ClkDiv + 1ul; + } + else u32Tmp2 = u32Tmp; + + if(u32Tmp2 < u32Min) + { + u32Min = u32Tmp2; + u32MinDSCnt = u32DSCnt; + u32MinClkDiv = u32ClkDiv; + + /* Break when get good results */ + if(u32Min == 0ul) + { + break; + } + } + } + + } + + /* Set USCI_UART baud rate */ + uuart->BRGEN = ((u32MinClkDiv - 1ul) << UUART_BRGEN_CLKDIV_Pos) | + ((u32MinDSCnt - 1ul) << UUART_BRGEN_DSCNT_Pos) | + ((u32PDSCnt - 1ul) << UUART_BRGEN_PDSCNT_Pos); + } + else + { + u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1ul; + u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1ul; + u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1ul; + } + + /* Set USCI_UART line configuration */ + uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width; + uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk | + UUART_PROTCTL_PARITYEN_Msk)) | u32parity; + uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32stop_bits; + + return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv); +} + + +/** + * @brief Write USCI_UART data + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer. + * @param[out] u32WriteBytes The byte number of data. + * + * @return Transfer byte count + * + * @details The function is to write data into TX buffer to transmit data by USCI_UART. + */ +uint32_t UUART_Write(UUART_T* uuart, uint8_t pu8TxBuf[], uint32_t u32WriteBytes) +{ + uint32_t u32Count, u32delayno; + + for(u32Count = 0ul; u32Count != u32WriteBytes; u32Count++) + { + u32delayno = 0ul; + while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0ul) /* Wait Tx empty */ + { + u32delayno++; + if(u32delayno >= 0x40000000ul) + { + break; + } + } + + if(u32delayno >= 0x40000000ul) + { + break; + } + + uuart->TXDAT = (uint8_t)pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */ + } + + return u32Count; +} + + +/** + * @brief Enable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * @param[in] u32WakeupMode The wakeup mode of USCI_UART module. +* - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode +* - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode + * + * @return None + * + * @details The function is used to enable Wake-up function of USCI_UART. + */ +void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode) +{ + uuart->PROTCTL |= u32WakeupMode; + uuart->WKCTL |= UUART_WKCTL_WKEN_Msk; +} + + +/** + * @brief Disable USCI_UART Wake-up Function + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable Wake-up function of USCI_UART. + */ +void UUART_DisableWakeup(UUART_T* uuart) +{ + uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk); + uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk; +} + +/** + * @brief Enable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to enable USCI_UART auto flow control. + */ +void UUART_EnableFlowCtrl(UUART_T* uuart) +{ + /* Set RTS signal is low level active */ + uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk; + + /* Set CTS signal is low level active */ + uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk; + + /* Enable CTS and RTS auto flow control function */ + uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk; +} + +/** + * @brief Disable USCI_UART auto flow control + * + * @param[in] uuart The pointer of the specified USCI_UART module. + * + * @return None + * + * @details The function is used to disable USCI_UART auto flow control. + */ +void UUART_DisableFlowCtrl(UUART_T* uuart) +{ + /* Disable CTS and RTS auto flow control function */ + uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk); +} + + + + +/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group USCI_UART_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/wdt.c b/arch/riscv32/fe310/src/StdDriver/src/wdt.c new file mode 100644 index 00000000..d54300c0 --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/wdt.c @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file wdt.c + * @version V3.00 + * @brief Watchdog Timer(WDT) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WDT_Driver WDT Driver + @{ +*/ + +/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions + @{ +*/ + +/** + * @brief Initialize WDT and start counting + * + * @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are: + * - \ref WDT_TIMEOUT_2POW4 + * - \ref WDT_TIMEOUT_2POW6 + * - \ref WDT_TIMEOUT_2POW8 + * - \ref WDT_TIMEOUT_2POW10 + * - \ref WDT_TIMEOUT_2POW12 + * - \ref WDT_TIMEOUT_2POW14 + * - \ref WDT_TIMEOUT_2POW16 + * - \ref WDT_TIMEOUT_2POW18 + * @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are: + * - \ref WDT_RESET_DELAY_1026CLK + * - \ref WDT_RESET_DELAY_130CLK + * - \ref WDT_RESET_DELAY_18CLK + * - \ref WDT_RESET_DELAY_3CLK + * @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE. + * @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n + * enable or disable WDT time-out reset system or wake-up system. + * @note Please make sure that Register Write-Protection Function has been disabled before using this function. + */ +void WDT_Open(uint32_t u32TimeoutInterval, + uint32_t u32ResetDelay, + uint32_t u32EnableReset, + uint32_t u32EnableWakeup) +{ + WDT->ALTCTL = u32ResetDelay; + + WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk | + (u32EnableReset << WDT_CTL_RSTEN_Pos) | + (u32EnableWakeup << WDT_CTL_WKEN_Pos); +} + +/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/StdDriver/src/wwdt.c b/arch/riscv32/fe310/src/StdDriver/src/wwdt.c new file mode 100644 index 00000000..637c939e --- /dev/null +++ b/arch/riscv32/fe310/src/StdDriver/src/wwdt.c @@ -0,0 +1,69 @@ +/**************************************************************************//** + * @file wwdt.c + * @version V3.00 + * @brief Window Watchdog Timer(WWDT) driver source file + * + * SPDX-License-Identifier: Apache-2.0 + * @copyright (C) 2016-2020 Nuvoton Technology Corp. All rights reserved. +*****************************************************************************/ +#include "NuMicro.h" + + +/** @addtogroup Standard_Driver Standard Driver + @{ +*/ + +/** @addtogroup WWDT_Driver WWDT Driver + @{ +*/ + +/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions + @{ +*/ + +/** + * @brief Open WWDT and start counting + * + * @param[in] u32PreScale Pre-scale setting of WWDT counter. Valid values are: + * - \ref WWDT_PRESCALER_1 + * - \ref WWDT_PRESCALER_2 + * - \ref WWDT_PRESCALER_4 + * - \ref WWDT_PRESCALER_8 + * - \ref WWDT_PRESCALER_16 + * - \ref WWDT_PRESCALER_32 + * - \ref WWDT_PRESCALER_64 + * - \ref WWDT_PRESCALER_128 + * - \ref WWDT_PRESCALER_192 + * - \ref WWDT_PRESCALER_256 + * - \ref WWDT_PRESCALER_384 + * - \ref WWDT_PRESCALER_512 + * - \ref WWDT_PRESCALER_768 + * - \ref WWDT_PRESCALER_1024 + * - \ref WWDT_PRESCALER_1536 + * - \ref WWDT_PRESCALER_2048 + * @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F. + * @param[in] u32EnableInt Enable WWDT time-out interrupt function. Valid values are TRUE and FALSE. + * + * @return None + * + * @details This function makes WWDT module start counting with different counter period by pre-scale setting and compared window value. + * @note Application can call this function only once after boot up. + */ +void WWDT_Open(uint32_t u32PreScale, + uint32_t u32CmpValue, + uint32_t u32EnableInt) +{ + WWDT->CTL = u32PreScale | + (u32CmpValue << WWDT_CTL_CMPDAT_Pos) | + ((u32EnableInt == (uint32_t)TRUE) ? WWDT_CTL_INTEN_Msk : 0UL) | + WWDT_CTL_WWDTEN_Msk; +} + +/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */ + +/*@}*/ /* end of group WWDT_Driver */ + +/*@}*/ /* end of group Standard_Driver */ + +/*** (C) COPYRIGHT 2016-2020 Nuvoton Technology Corp. ***/ + diff --git a/arch/riscv32/fe310/src/freedom-metal/.clang-format b/arch/riscv32/fe310/src/freedom-metal/.clang-format new file mode 100644 index 00000000..f9d627fe --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.clang-format @@ -0,0 +1,5 @@ +BasedOnStyle: LLVM +Language: Cpp + +IndentWidth: 4 + diff --git a/arch/riscv32/fe310/src/freedom-metal/.gitattributes b/arch/riscv32/fe310/src/freedom-metal/.gitattributes new file mode 100644 index 00000000..a17d9d5a --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.gitattributes @@ -0,0 +1,11 @@ +# Ignore autotools files when computing language stats +m4/* linguist-vendored=true +ar-lib linguist-generated=true +compile linguist-generated=true +configure linguist-generated=true +depcomp linguist-generated=true +install-sh linguist-generated=true +missing linguist-generated=true +Makefile.in linguist-generated=true +aclocal.m4 linguist-generated=true + diff --git a/arch/riscv32/fe310/src/freedom-metal/.github/CODEOWNERS b/arch/riscv32/fe310/src/freedom-metal/.github/CODEOWNERS new file mode 100644 index 00000000..bee2112b --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.github/CODEOWNERS @@ -0,0 +1,3 @@ +# Automatically request review on all PRs +* @e-puerto @sifive-eblot @paul-walmsley-sifive + diff --git a/arch/riscv32/fe310/src/freedom-metal/.github/workflows/release.yml b/arch/riscv32/fe310/src/freedom-metal/.github/workflows/release.yml new file mode 100644 index 00000000..0fe2ddf3 --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.github/workflows/release.yml @@ -0,0 +1,76 @@ +on: + push: + # Require one of the following patterns to match the tag + tags: + - 'v[0-9]+.[0-9]+.[0-9]+.[0-9]+' # ex. v20.00.00.00 + - 'v[0-9]+.[0-9]+.RC.[0-9]+' # ex. v20.00.RC.00 + +name: Create Release + +env: + PROJECT_NAME: freedom-metal + # Release is a prerelease if the tag contains rc + PRERELEASE: ${{ contains(github.ref, 'RC') }} + +jobs: + release: + runs-on: ubuntu-latest + + steps: + # Perform a recursive, PAT-authenticated checkout of all freedom-metal + # submodules. This allows us to update the published docs on github.io. + - name: 'Checkout' + uses: actions/checkout@v2 + with: + submodules: 'recursive' + fetch-depth: 0 + token: ${{ secrets.PERSONAL_ACCESS_TOKEN }} + + - name: 'Create Release Notes' + uses: sifive/action-release-notes@v1 + id: create-release-notes + with: + project-name: ${{ env.PROJECT_NAME }} + release: ${{ github.ref }} + + - name: 'Create Release' + uses: actions/create-release@v1 + env: + GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} + with: + tag_name: ${{ github.ref }} + release_name: ${{ env.PROJECT_NAME }} ${{ github.ref }} + body: ${{ steps.create-release-notes.outputs.release-notes }} + draft: false + prerelease: ${{ env.PRERELEASE }} + + - name: 'Build Docker Image for Docs Build' + run: | + docker build -t docs-build -f doc/Dockerfile . + + - name: 'Clean Docs Output Folder' + run: | + cd doc/html + git fetch + git checkout master + git reset --hard origin/master + + - name: 'Build Sphinx Documentation' + run: | + tag=$(echo ${{ github.ref }} | cut -d '/' -f 3) + docker run \ + --rm \ + -v $(pwd):/freedom-metal \ + -e RELEASE_TAG="${tag}" \ + docs-build \ + make -C /freedom-metal/doc clean html + + - name: 'Publish Documentation' + run: | + tag=$(echo ${{ github.ref }} | cut -d '/' -f 3) + cd doc/html + git config user.email "no-reply@sifive.com" + git config user.name "actions-bot" + git add . + git commit -m "Documentation for ${{ env.PROJECT_NAME }} ${tag}" + git push diff --git a/arch/riscv32/fe310/src/freedom-metal/.github/workflows/tests.yml b/arch/riscv32/fe310/src/freedom-metal/.github/workflows/tests.yml new file mode 100644 index 00000000..53a58a78 --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.github/workflows/tests.yml @@ -0,0 +1,32 @@ +name: tests + +on: pull_request + +jobs: + test: + runs-on: ubuntu-latest + + steps: + - name: 'Clone freedom-metal' + uses: actions/checkout@v2 + with: + path: freedom-metal + fetch-depth: 1 + submodules: true + token: ${{ secrets.PERSONAL_ACCESS_TOKEN }} + + - name: 'Login to Docker Hub' + uses: docker/login-action@v1.9.0 + with: + username: ${{ secrets.DOCKERHUB_USERNAME }} + password: ${{ secrets.DOCKERHUB_TOKEN }} + + - name: 'Build freedom-metal container' + run: | + docker build -t freedom-metal \ + -f freedom-metal/docker/Dockerfile \ + freedom-metal + + - name: 'Run Clang code style test' + run: | + docker run --rm freedom-metal ./scripts/check-format diff --git a/arch/riscv32/fe310/src/freedom-metal/.gitignore b/arch/riscv32/fe310/src/freedom-metal/.gitignore new file mode 100644 index 00000000..18984a5a --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.gitignore @@ -0,0 +1,36 @@ +/autom4te.cache/ +/config.log +*.swp +/Makefile +/config.status +*.a +*.o +.dirstamp +.deps +/hello +/pll_set_hz +/mee/machines +/machine.dtb +*.lds +*.dtb +/mee/machine +*.map +*.mk +/return_pass +/return_fail +*.specs + +# Editor - Various Merge tools +*.bak +# Editor - Emacs +*~ +\#*\# +# Editor - VIM +[._]*.s[a-v][a-z] +[._]*.sw[a-p] +[._]s[a-rt-v][a-z] +[._]ss[a-gi-z] +[._]sw[a-p] +# ctags +tags + diff --git a/arch/riscv32/fe310/src/freedom-metal/.gitmodules b/arch/riscv32/fe310/src/freedom-metal/.gitmodules new file mode 100644 index 00000000..a9f65293 --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/.gitmodules @@ -0,0 +1,3 @@ +[submodule "doc/html"] + path = doc/html + url = ../freedom-metal-docs.git diff --git a/arch/riscv32/fe310/src/freedom-metal/Doxyfile b/arch/riscv32/fe310/src/freedom-metal/Doxyfile new file mode 100644 index 00000000..22c8f784 --- /dev/null +++ b/arch/riscv32/fe310/src/freedom-metal/Doxyfile @@ -0,0 +1,2537 @@ +# Doxyfile 1.8.15 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a double hash (##) is considered a comment and is placed in +# front of the TAG it is preceding. +# +# All text after a single hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists, items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (\" \"). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the configuration +# file that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# https://www.gnu.org/software/libiconv/ for the list of possible encodings. +# The default value is: UTF-8. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by +# double-quotes, unless you are using Doxywizard) that should identify the +# project for which the documentation is generated. This name is used in the +# title of most generated pages and in a few other places. +# The default value is: My Project. + +PROJECT_NAME = "Freedom Metal" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. This +# could be handy for archiving the generated documentation or if some version +# control system is used. + +PROJECT_NUMBER = + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer a +# quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = "Bare Metal Compatibility Library for the Freedom Platform" + +# With the PROJECT_LOGO tag one can specify a logo or an icon that is included +# in the documentation. The maximum height of the logo should not exceed 55 +# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy +# the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path +# into which the generated documentation will be written. If a relative path is +# entered, it will be relative to the location where doxygen was started. If +# left blank the current directory will be used. + +OUTPUT_DIRECTORY = "doc" + +# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub- +# directories (in 2 levels) under the output directory of each output format and +# will distribute the generated files over these directories. Enabling this +# option can be useful when feeding doxygen a huge amount of source files, where +# putting all generated files in the same directory would otherwise causes +# performance problems for the file system. +# The default value is: NO. + +CREATE_SUBDIRS = NO + +# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII +# characters to appear in the names of generated files. If set to NO, non-ASCII +# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode +# U+3044. +# The default value is: NO. + +ALLOW_UNICODE_NAMES = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all constant output in the proper language. +# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese, +# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States), +# Esperanto, Farsi (Persian), Finnish, French, German, Greek, Hungarian, +# Indonesian, Italian, Japanese, Japanese-en (Japanese with English messages), +# Korean, Korean-en (Korean with English messages), Latvian, Lithuanian, +# Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese, Romanian, Russian, +# Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish, Swedish, Turkish, +# Ukrainian and Vietnamese. +# The default value is: English. + +OUTPUT_LANGUAGE = English + +# The OUTPUT_TEXT_DIRECTION tag is used to specify the direction in which all +# documentation generated by doxygen is written. Doxygen will use this +# information to generate all generated output in the proper direction. +# Possible values are: None, LTR, RTL and Context. +# The default value is: None. + +OUTPUT_TEXT_DIRECTION = None + +# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member +# descriptions after the members that are listed in the file and class +# documentation (similar to Javadoc). Set to NO to disable this. +# The default value is: YES. + +BRIEF_MEMBER_DESC = YES + +# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief +# description of a member or function before the detailed description +# +# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the +# brief descriptions will be completely suppressed. +# The default value is: YES. + +REPEAT_BRIEF = YES + +# This tag implements a quasi-intelligent brief description abbreviator that is +# used to form the text in various listings. Each string in this list, if found +# as the leading text of the brief description, will be stripped from the text +# and the result, after processing the whole list, is used as the annotated +# text. Otherwise, the brief description is used as-is. If left blank, the +# following values are used ($name is automatically replaced with the name of +# the entity):The $name class, The $name widget, The $name file, is, provides, +# specifies, contains, represents, a, an and the. + +ABBREVIATE_BRIEF = "The $name class" \ + "The $name widget" \ + "The $name file" \ + is \ + provides \ + specifies \ + contains \ + represents \ + a \ + an \ + the + +# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then +# doxygen will generate a detailed section even if there is only a brief +# description. +# The default value is: NO. + +ALWAYS_DETAILED_SEC = NO + +# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all +# inherited members of a class in the documentation of that class as if those +# members were ordinary class members. Constructors, destructors and assignment +# operators of the base classes will not be shown. +# The default value is: NO. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path +# before files name in the file list and in the header files. If set to NO the +# shortest path that makes the file name unique will be used +# The default value is: YES. + +FULL_PATH_NAMES = YES + +# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path. +# Stripping is only done if one of the specified strings matches the left-hand +# part of the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the path to +# strip. +# +# Note that you can specify absolute paths here, but also relative paths, which +# will be relative from the directory where doxygen is started. +# This tag requires that the tag FULL_PATH_NAMES is set to YES. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the +# path mentioned in the documentation of a class, which tells the reader which +# header file to include in order to use a class. If left blank only the name of +# the header file containing the class definition is used. Otherwise one should +# specify the list of include paths that are normally passed to the compiler +# using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but +# less readable) file names. This can be useful is your file systems doesn't +# support long names like on DOS, Mac, or CD-ROM. +# The default value is: NO. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the +# first line (until the first dot) of a Javadoc-style comment as the brief +# description. If set to NO, the Javadoc-style will behave just like regular Qt- +# style comments (thus requiring an explicit @brief command for a brief +# description.) +# The default value is: NO. + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first +# line (until the first dot) of a Qt-style comment as the brief description. If +# set to NO, the Qt-style will behave just like regular Qt-style comments (thus +# requiring an explicit \brief command for a brief description.) +# The default value is: NO. + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a +# multi-line C++ special comment block (i.e. a block of //! or /// comments) as +# a brief description. This used to be the default behavior. The new default is +# to treat a multi-line C++ comment block as a detailed description. Set this +# tag to YES if you prefer the old behavior instead. +# +# Note that setting this tag to YES also means that rational rose comments are +# not recognized any more. +# The default value is: NO. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the +# documentation from any documented member that it re-implements. +# The default value is: YES. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new +# page for each member. If set to NO, the documentation of a member will be part +# of the file/class/namespace that contains it. +# The default value is: NO. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen +# uses this value to replace tabs by spaces in code fragments. +# Minimum value: 1, maximum value: 16, default value: 4. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that act as commands in +# the documentation. An alias has the form: +# name=value +# For example adding +# "sideeffect=@par Side Effects:\n" +# will allow you to put the command \sideeffect (or @sideeffect) in the +# documentation, which will result in a user-defined paragraph with heading +# "Side Effects:". You can put \n's in the value part of an alias to insert +# newlines (in the resulting output). You can put ^^ in the value part of an +# alias to insert a newline as if a physical newline was in the original file. +# When you need a literal { or } or , in the value part of an alias you have to +# escape them by means of a backslash (\), this can lead to conflicts with the +# commands \{ and \} for these it is advised to use the version @{ and @} or use +# a double escape (\\{ and \\}) + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding "class=itcl::class" +# will allow you to use the command class in the itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources +# only. Doxygen will then generate output that is more tailored for C. For +# instance, some of the names that are used will be different. The list of all +# members will be omitted, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or +# Python sources only. Doxygen will then generate output that is more tailored +# for that language. For instance, namespaces will be presented as packages, +# qualified scopes will look different, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources. Doxygen will then generate output that is tailored for Fortran. +# The default value is: NO. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for VHDL. +# The default value is: NO. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Set the OPTIMIZE_OUTPUT_SLICE tag to YES if your project consists of Slice +# sources only. Doxygen will then generate output that is more tailored for that +# language. For instance, namespaces will be presented as modules, types will be +# separated into more groups, etc. +# The default value is: NO. + +OPTIMIZE_OUTPUT_SLICE = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, and +# language is one of the parsers supported by doxygen: IDL, Java, Javascript, +# Csharp (C#), C, C++, D, PHP, md (Markdown), Objective-C, Python, Slice, +# Fortran (fixed format Fortran: FortranFixed, free formatted Fortran: +# FortranFree, unknown formatted Fortran: Fortran. In the later case the parser +# tries to guess whether the code is fixed or free formatted code, this is the +# default for Fortran type files), VHDL, tcl. For instance to make doxygen treat +# .inc files as Fortran files (default is PHP), and .f files as C (default is +# Fortran), use: inc=Fortran f=C. +# +# Note: For files without extension you can use no_extension as a placeholder. +# +# Note that for custom extensions you also need to set FILE_PATTERNS otherwise +# the files are not read by doxygen. + +EXTENSION_MAPPING = + +# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments +# according to the Markdown format, which allows for more readable +# documentation. See https://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you can +# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in +# case of backward compatibilities issues. +# The default value is: YES. + +MARKDOWN_SUPPORT = YES + +# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up +# to that level are automatically included in the table of contents, even if +# they do not have an id attribute. +# Note: This feature currently applies only to Markdown headings. +# Minimum value: 0, maximum value: 99, default value: 0. +# This tag requires that the tag MARKDOWN_SUPPORT is set to YES. + +TOC_INCLUDE_HEADINGS = 0 + +# When enabled doxygen tries to link words that correspond to documented +# classes, or namespaces to their corresponding documentation. Such a link can +# be prevented in individual cases by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. +# The default value is: YES. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should set this +# tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); +# versus func(std::string) {}). This also make the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. +# The default value is: NO. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. +# The default value is: NO. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip (see: +# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen +# will parse them like normal C++ but will assume all classes use public instead +# of private inheritance when no explicit protection keyword is present. +# The default value is: NO. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES will make +# doxygen to replace the get and set methods by a property in the documentation. +# This will only work if the methods are indeed getting or setting a simple +# type. If this is not the case, or you want to show the methods anyway, you +# should set this option to NO. +# The default value is: YES. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. +# The default value is: NO. + +DISTRIBUTE_GROUP_DOC = NO + +# If one adds a struct or class to a group and this option is enabled, then also +# any nested class or struct is added to the same group. By default this option +# is disabled and one has to add nested compounds explicitly via \ingroup. +# The default value is: NO. + +GROUP_NESTED_COMPOUNDS = NO + +# Set the SUBGROUPING tag to YES to allow class member groups of the same type +# (for instance a group of public functions) to be put as a subgroup of that +# type (e.g. under the Public Functions section). Set it to NO to prevent +# subgrouping. Alternatively, this can be done per class using the +# \nosubgrouping command. +# The default value is: YES. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions +# are shown inside the group in which they are included (e.g. using \ingroup) +# instead of on a separate page (for HTML and Man pages) or section (for LaTeX +# and RTF). +# +# Note that this feature does not work in combination with +# SEPARATE_MEMBER_PAGES. +# The default value is: NO. + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions +# with only public data fields or simple typedef fields will be shown inline in +# the documentation of the scope in which they are defined (i.e. file, +# namespace, or group documentation), provided this scope is documented. If set +# to NO, structs, classes, and unions are shown on a separate page (for HTML and +# Man pages) or section (for LaTeX and RTF). +# The default value is: NO. + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or +# enum is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically be +# useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. +# The default value is: NO. + +TYPEDEF_HIDES_STRUCT = NO + +# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This +# cache is used to resolve symbols given their name and scope. Since this can be +# an expensive process and often the same symbol appears multiple times in the +# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small +# doxygen will become slower. If the cache is too large, memory is wasted. The +# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range +# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536 +# symbols. At the end of a run doxygen will report the cache usage and suggest +# the optimal cache size from a speed point of view. +# Minimum value: 0, maximum value: 9, default value: 0. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in +# documentation are documented, even if no documentation was available. Private +# class members and static file members will be hidden unless the +# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES. +# Note: This will also disable the warnings about undocumented members that are +# normally produced when WARNINGS is set to YES. +# The default value is: NO. + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will +# be included in the documentation. +# The default value is: NO. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal +# scope will be included in the documentation. +# The default value is: NO. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be +# included in the documentation. +# The default value is: NO. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined +# locally in source files will be included in the documentation. If set to NO, +# only classes defined in header files are included. Does not have any effect +# for Java sources. +# The default value is: YES. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. If set to YES, local methods, +# which are defined in the implementation section but not in the interface are +# included in the documentation. If set to NO, only methods in the interface are +# included. +# The default value is: NO. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base name of +# the file that contains the anonymous namespace. By default anonymous namespace +# are hidden. +# The default value is: NO. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all +# undocumented members inside documented classes or files. If set to NO these +# members will be included in the various overviews, but no documentation +# section is generated. This option has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. If set +# to NO, these classes will be included in the various overviews. This option +# has no effect if EXTRACT_ALL is enabled. +# The default value is: NO. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend +# (class|struct|union) declarations. If set to NO, these declarations will be +# included in the documentation. +# The default value is: NO. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any +# documentation blocks found inside the body of a function. If set to NO, these +# blocks will be appended to the function's detailed documentation block. +# The default value is: NO. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation that is typed after a +# \internal command is included. If the tag is set to NO then the documentation +# will be excluded. Set it to YES to include the internal documentation. +# The default value is: NO. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file +# names in lower-case letters. If set to YES, upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. +# The default value is: system dependent. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with +# their full class and namespace scopes in the documentation. If set to YES, the +# scope will be hidden. +# The default value is: NO. + +HIDE_SCOPE_NAMES = NO + +# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will +# append additional text to a page's title, such as Class Reference. If set to +# YES the compound reference will be hidden. +# The default value is: NO. + +HIDE_COMPOUND_REFERENCE= NO + +# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of +# the files that are included by a file in the documentation of that file. +# The default value is: YES. + +SHOW_INCLUDE_FILES = YES + +# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each +# grouped member an include statement to the documentation, telling the reader +# which file to include in order to use the member. +# The default value is: NO. + +SHOW_GROUPED_MEMB_INC = NO + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include +# files with double quotes in the documentation rather than with sharp brackets. +# The default value is: NO. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the +# documentation for inline members. +# The default value is: YES. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the +# (detailed) documentation of file and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. +# The default value is: YES. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief +# descriptions of file, namespace and class members alphabetically by member +# name. If set to NO, the members will appear in declaration order. Note that +# this will also influence the order of the classes in the class list. +# The default value is: NO. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the +# (brief and detailed) documentation of class members so that constructors and +# destructors are listed first. If set to NO the constructors will appear in the +# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS. +# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief +# member documentation. +# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting +# detailed member documentation. +# The default value is: NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy +# of group names into alphabetical order. If set to NO the group names will +# appear in their defined order. +# The default value is: NO. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by +# fully-qualified names, including namespaces. If set to NO, the class list will +# be sorted only by class name, not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the alphabetical +# list. +# The default value is: NO. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper +# type resolution of all parameters of a function it will reject a match between +# the prototype and the implementation of a member function even if there is +# only one candidate or it is obvious which candidate to choose by doing a +# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still +# accept a match between prototype and implementation in such cases. +# The default value is: NO. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo +# list. This list is created by putting \todo commands in the documentation. +# The default value is: YES. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test +# list. This list is created by putting \test commands in the documentation. +# The default value is: YES. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug +# list. This list is created by putting \bug commands in the documentation. +# The default value is: YES. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO) +# the deprecated list. This list is created by putting \deprecated commands in +# the documentation. +# The default value is: YES. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional documentation +# sections, marked by \if ... \endif and \cond +# ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the +# initial value of a variable or macro / define can have for it to appear in the +# documentation. If the initializer consists of more lines than specified here +# it will be hidden. Use a value of 0 to hide initializers completely. The +# appearance of the value of individual variables and macros / defines can be +# controlled using \showinitializer or \hideinitializer command in the +# documentation regardless of this setting. +# Minimum value: 0, maximum value: 10000, default value: 30. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at +# the bottom of the documentation of classes and structs. If set to YES, the +# list will mention the files that were used to generate the documentation. +# The default value is: YES. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This +# will remove the Files entry from the Quick Index and from the Folder Tree View +# (if specified). +# The default value is: YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces +# page. This will remove the Namespaces entry from the Quick Index and from the +# Folder Tree View (if specified). +# The default value is: YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command command input-file, where command is the value of the +# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided +# by doxygen. Whatever the program writes to standard output is used as the file +# version. For an example see the documentation. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. You can +# optionally specify a file name after the option, if omitted DoxygenLayout.xml +# will be used as the name of the layout file. +# +# Note that if you run doxygen from a directory containing a file called +# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE +# tag is left empty. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files containing +# the reference definitions. This must be a list of .bib files. The .bib +# extension is automatically appended if omitted. This requires the bibtex tool +# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info. +# For LaTeX the style of the bibliography can be controlled using +# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the +# search path. See also \cite for info how to create references. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# Configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated to +# standard output by doxygen. If QUIET is set to YES this implies that the +# messages are off. +# The default value is: NO. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES +# this implies that the warnings are on. +# +# Tip: Turn warnings on while writing the documentation. +# The default value is: YES. + +WARNINGS = YES + +# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate +# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag +# will automatically be disabled. +# The default value is: YES. + +WARN_IF_UNDOCUMENTED = YES + +# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some parameters +# in a documented function, or documenting parameters that don't exist or using +# markup commands wrongly. +# The default value is: YES. + +WARN_IF_DOC_ERROR = YES + +# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that +# are documented, but have no documentation for their parameters or return +# value. If set to NO, doxygen will only warn about wrong or incomplete +# parameter documentation, but not about the absence of documentation. If +# EXTRACT_ALL is set to YES then this flag will automatically be disabled. +# The default value is: NO. + +WARN_NO_PARAMDOC = NO + +# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when +# a warning is encountered. +# The default value is: NO. + +WARN_AS_ERROR = NO + +# The WARN_FORMAT tag determines the format of the warning messages that doxygen +# can produce. The string should contain the $file, $line, and $text tags, which +# will be replaced by the file and line number from which the warning originated +# and the warning text. Optionally the format may contain $version, which will +# be replaced by the version of the file (if it could be obtained via +# FILE_VERSION_FILTER) +# The default value is: $file:$line: $text. + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning and error +# messages should be written. If left blank the output is written to standard +# error (stderr). + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# Configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag is used to specify the files and/or directories that contain +# documented source files. You may enter file names like myfile.cpp or +# directories like /usr/src/myproject. Separate the files or directories with +# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING +# Note: If this tag is empty the current directory is searched. + +INPUT = metal + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses +# libiconv (or the iconv built into libc) for the transcoding. See the libiconv +# documentation (see: https://www.gnu.org/software/libiconv/) for the list of +# possible encodings. +# The default value is: UTF-8. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and +# *.h) to filter out the source-files in the directories. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# read by doxygen. +# +# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp, +# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h, +# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc, +# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, +# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf, *.qsf and *.ice. + +FILE_PATTERNS = *.c \ + *.cc \ + *.cxx \ + *.cpp \ + *.c++ \ + *.java \ + *.ii \ + *.ixx \ + *.ipp \ + *.i++ \ + *.inl \ + *.idl \ + *.ddl \ + *.odl \ + *.h \ + *.hh \ + *.hxx \ + *.hpp \ + *.h++ \ + *.cs \ + *.d \ + *.php \ + *.php4 \ + *.php5 \ + *.phtml \ + *.inc \ + *.m \ + *.markdown \ + *.md \ + *.mm \ + *.dox \ + *.py \ + *.pyw \ + *.f90 \ + *.f95 \ + *.f03 \ + *.f08 \ + *.f \ + *.for \ + *.tcl \ + *.vhd \ + *.vhdl \ + *.ucf \ + *.qsf \ + *.ice + +# The RECURSIVE tag can be used to specify whether or not subdirectories should +# be searched for input files as well. +# The default value is: NO. + +RECURSIVE = NO + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = metal/compiler.h metal/io.h metal/machine.h + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. +# The default value is: NO. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test +# +# Note that the wildcards are matched against the file with absolute path, so to +# exclude all test directories use the pattern */test/* + +EXCLUDE_SYMBOLS = _* __* *vtable + +# The EXAMPLE_PATH tag can be used to specify one or more files or directories +# that contain example code fragments that are included (see the \include +# command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and +# *.h) to filter out the source-files in the directories. If left blank all +# files are included. + +EXAMPLE_PATTERNS = * + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude commands +# irrespective of the value of the RECURSIVE tag. +# The default value is: NO. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or directories +# that contain images that are to be included in the documentation (see the +# \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command: +# +# +# +# where is the value of the INPUT_FILTER tag, and is the +# name of an input file. Doxygen will then use the output that the filter +# program writes to standard output. If FILTER_PATTERNS is specified, this tag +# will be ignored. +# +# Note that the filter must not add or remove lines; it is applied before the +# code is scanned, but not when the output code is generated. If lines are added +# or removed, the anchors will not be placed correctly. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. The filters are a list of the form: pattern=filter +# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how +# filters are used. If the FILTER_PATTERNS tag is empty or if none of the +# patterns match the file name, INPUT_FILTER is applied. +# +# Note that for custom extensions or not directly supported extensions you also +# need to set EXTENSION_MAPPING for the extension otherwise the files are not +# properly processed by doxygen. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will also be used to filter the input files that are used for +# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES). +# The default value is: NO. + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and +# it is also possible to disable source filtering for a specific pattern using +# *.ext= (so without naming a filter). +# This tag requires that the tag FILTER_SOURCE_FILES is set to YES. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page +# (index.html). This can be useful if you have a project on for instance GitHub +# and want to reuse the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = + +#--------------------------------------------------------------------------- +# Configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will be +# generated. Documented entities will be cross-referenced with these sources. +# +# Note: To get rid of all source code in the generated output, make sure that +# also VERBATIM_HEADERS is set to NO. +# The default value is: NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body of functions, +# classes and enums directly into the documentation. +# The default value is: NO. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any +# special comment blocks from generated source code fragments. Normal C, C++ and +# Fortran comments will always remain visible. +# The default value is: YES. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES then for each documented +# entity all documented functions referencing it will be listed. +# The default value is: NO. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES then for each documented function +# all documented entities called/used by that function will be listed. +# The default value is: NO. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set +# to YES then the hyperlinks from functions in REFERENCES_RELATION and +# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will +# link to the documentation. +# The default value is: YES. + +REFERENCES_LINK_SOURCE = YES + +# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the +# source code will show a tooltip with additional information such as prototype, +# brief description and links to the definition and documentation. Since this +# will make the HTML file larger and loading of large files a bit slower, you +# can opt to disable this feature. +# The default value is: YES. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +SOURCE_TOOLTIPS = YES + +# If the USE_HTAGS tag is set to YES then the references to source code will +# point to the HTML generated by the htags(1) tool instead of doxygen built-in +# source browser. The htags tool is part of GNU's global source tagging system +# (see https://www.gnu.org/software/global/global.html). You will need version +# 4.8.6 or higher. +# +# To use it do the following: +# - Install the latest version of global +# - Enable SOURCE_BROWSER and USE_HTAGS in the configuration file +# - Make sure the INPUT points to the root of the source tree +# - Run doxygen as normal +# +# Doxygen will invoke htags (and that will in turn invoke gtags), so these +# tools must be available from the command line (i.e. in the search path). +# +# The result: instead of the source browser generated by doxygen, the links to +# source code will now point to the output of htags. +# The default value is: NO. +# This tag requires that the tag SOURCE_BROWSER is set to YES. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a +# verbatim copy of the header file for each class for which an include is +# specified. Set to NO to disable this. +# See also: Section \class. +# The default value is: YES. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# Configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all +# compounds will be generated. Enable this if the project contains a lot of +# classes, structs, unions or interfaces. +# The default value is: YES. + +ALPHABETICAL_INDEX = YES + +# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in +# which the alphabetical index list will be split. +# Minimum value: 1, maximum value: 20, default value: 5. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all classes will +# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag +# can be used to specify a prefix (or a list of prefixes) that should be ignored +# while generating the index headers. +# This tag requires that the tag ALPHABETICAL_INDEX is set to YES. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output +# The default value is: YES. + +GENERATE_HTML = NO + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a +# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of +# it. +# The default directory is: html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each +# generated HTML page (for example: .htm, .php, .asp). +# The default value is: .html. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a user-defined HTML header file for +# each generated HTML page. If the tag is left blank doxygen will generate a +# standard header. +# +# To get valid HTML the header file that includes any scripts and style sheets +# that doxygen needs, which is dependent on the configuration options used (e.g. +# the setting GENERATE_TREEVIEW). It is highly recommended to start with a +# default header using +# doxygen -w html new_header.html new_footer.html new_stylesheet.css +# YourConfigFile +# and then modify the file new_header.html. See also section "Doxygen usage" +# for information on how to generate the default header that doxygen normally +# uses. +# Note: The header is subject to change so you typically have to regenerate the +# default header when upgrading to a newer version of doxygen. For a description +# of the possible markers and block names see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each +# generated HTML page. If the tag is left blank doxygen will generate a standard +# footer. See HTML_HEADER for more information on how to generate a default +# footer and what special commands can be used inside the footer. See also +# section "Doxygen usage" for information on how to generate the default footer +# that doxygen normally uses. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style +# sheet that is used by each HTML page. It can be used to fine-tune the look of +# the HTML output. If left blank doxygen will generate a default style sheet. +# See also section "Doxygen usage" for information on how to generate the style +# sheet that doxygen normally uses. +# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as +# it is more robust and this tag (HTML_STYLESHEET) will in the future become +# obsolete. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined +# cascading style sheets that are included after the standard style sheets +# created by doxygen. Using this option one can overrule certain style aspects. +# This is preferred over using HTML_STYLESHEET since it does not replace the +# standard style sheet and is therefore more robust against future updates. +# Doxygen will copy the style sheet files to the output directory. +# Note: The order of the extra style sheet files is of importance (e.g. the last +# style sheet in the list overrules the setting of the previous ones in the +# list). For an example see the documentation. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that the +# files will be copied as-is; there are no commands or markers available. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen +# will adjust the colors in the style sheet and background images according to +# this color. Hue is specified as an angle on a colorwheel, see +# https://en.wikipedia.org/wiki/Hue for more information. For instance the value +# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300 +# purple, and 360 is red again. +# Minimum value: 0, maximum value: 359, default value: 220. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors +# in the HTML output. For a value of 0 the output will use grayscales only. A +# value of 255 will produce the most vivid colors. +# Minimum value: 0, maximum value: 255, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the +# luminance component of the colors in the HTML output. Values below 100 +# gradually make the output lighter, whereas values above 100 make the output +# darker. The value divided by 100 is the actual gamma applied, so 80 represents +# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not +# change the gamma. +# Minimum value: 40, maximum value: 240, default value: 80. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting this +# to YES can help to show when doxygen was last run and thus if the +# documentation is up to date. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_TIMESTAMP = NO + +# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML +# documentation will contain a main index with vertical navigation menus that +# are dynamically created via Javascript. If disabled, the navigation index will +# consists of multiple levels of tabs that are statically embedded in every HTML +# page. Disable this option to support browsers that do not have Javascript, +# like the Qt help browser. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_MENUS = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries +# shown in the various tree structured indices initially; the user can expand +# and collapse entries dynamically later on. Doxygen will expand the tree to +# such a level that at most the specified number of entries are visible (unless +# a fully collapsed tree already exceeds this amount). So setting the number of +# entries 1 will produce a full collapsed tree by default. 0 is a special value +# representing an infinite number of entries and will result in a full expanded +# tree by default. +# Minimum value: 0, maximum value: 9999, default value: 100. +# This tag requires that the tag GENERATE_HTML is set to YES. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files will be +# generated that can be used as input for Apple's Xcode 3 integrated development +# environment (see: https://developer.apple.com/xcode/), introduced with OSX +# 10.5 (Leopard). To create a documentation set, doxygen will generate a +# Makefile in the HTML output directory. Running make will produce the docset in +# that directory and running make install will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at +# startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy +# genXcode/_index.html for more information. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_DOCSET = NO + +# This tag determines the name of the docset feed. A documentation feed provides +# an umbrella under which multiple documentation sets from a single provider +# (such as a company or product suite) can be grouped. +# The default value is: Doxygen generated docs. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# This tag specifies a string that should uniquely identify the documentation +# set bundle. This should be a reverse domain-name style string, e.g. +# com.mycompany.MyDocSet. Doxygen will append .docset to the name. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify +# the documentation publisher. This should be a reverse domain-name style +# string, e.g. com.mycompany.MyDocSet.documentation. +# The default value is: org.doxygen.Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher. +# The default value is: Publisher. +# This tag requires that the tag GENERATE_DOCSET is set to YES. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three +# additional HTML index files: index.hhp, index.hhc, and index.hhk. The +# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop +# (see: https://www.microsoft.com/en-us/download/details.aspx?id=21138) on +# Windows. +# +# The HTML Help Workshop contains a compiler that can convert all HTML output +# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML +# files are now used as the Windows 98 help format, and will replace the old +# Windows help format (.hlp) on all Windows platforms in the future. Compressed +# HTML files also contain an index, a table of contents, and you can search for +# words in the documentation. The HTML workshop also contains a viewer for +# compressed HTML files. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_HTMLHELP = NO + +# The CHM_FILE tag can be used to specify the file name of the resulting .chm +# file. You can add a path in front of the file if the result should not be +# written to the html output directory. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_FILE = + +# The HHC_LOCATION tag can be used to specify the location (absolute path +# including file name) of the HTML help compiler (hhc.exe). If non-empty, +# doxygen will try to run the HTML help compiler on the generated index.hhp. +# The file has to be specified with full path. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +HHC_LOCATION = + +# The GENERATE_CHI flag controls if a separate .chi index file is generated +# (YES) or that it should be included in the master .chm file (NO). +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +GENERATE_CHI = NO + +# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc) +# and project file content. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +CHM_INDEX_ENCODING = + +# The BINARY_TOC flag controls whether a binary table of contents is generated +# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it +# enables the Previous and Next buttons. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members to +# the table of contents of the HTML help documentation and to the tree view. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTMLHELP is set to YES. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that +# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help +# (.qch) of the generated HTML documentation. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify +# the file name of the resulting .qch file. The path specified is relative to +# the HTML output folder. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help +# Project output. For more information please see Qt Help Project / Namespace +# (see: http://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace). +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt +# Help Project output. For more information please see Qt Help Project / Virtual +# Folders (see: http://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual- +# folders). +# The default value is: doc. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_VIRTUAL_FOLDER = doc + +# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom +# filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see Qt Help Project / Custom +# Filters (see: http://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom- +# filters). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's filter section matches. Qt Help Project / Filter Attributes (see: +# http://doc.qt.io/archives/qt-4.8/qthelpproject.html#filter-attributes). +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHP_SECT_FILTER_ATTRS = + +# The QHG_LOCATION tag can be used to specify the location of Qt's +# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the +# generated .qhp file. +# This tag requires that the tag GENERATE_QHP is set to YES. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be +# generated, together with the HTML files, they form an Eclipse help plugin. To +# install this plugin and make it available under the help contents menu in +# Eclipse, the contents of the directory containing the HTML and XML files needs +# to be copied into the plugins directory of eclipse. The name of the directory +# within the plugins directory should be the same as the ECLIPSE_DOC_ID value. +# After copying Eclipse needs to be restarted before the help appears. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the Eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have this +# name. Each documentation set should have its own identifier. +# The default value is: org.doxygen.Project. +# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# If you want full control over the layout of the generated HTML pages it might +# be necessary to disable the index and replace it with your own. The +# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top +# of each HTML page. A value of NO enables the index and the value YES disables +# it. Since the tabs in the index contain the same information as the navigation +# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. If the tag +# value is set to YES, a side panel will be generated containing a tree-like +# index structure (just like the one that is generated for HTML Help). For this +# to work a browser that supports JavaScript, DHTML, CSS and frames is required +# (i.e. any modern browser). Windows users are probably better off using the +# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can +# further fine-tune the look of the index. As an example, the default style +# sheet generated by doxygen has an example that shows how to put an image at +# the root of the tree instead of the PROJECT_NAME. Since the tree basically has +# the same information as the tab index, you could consider setting +# DISABLE_INDEX to YES when enabling this option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that +# doxygen will group on one line in the generated HTML documentation. +# +# Note that a value of 0 will completely suppress the enum values from appearing +# in the overview section. +# Minimum value: 0, maximum value: 20, default value: 4. +# This tag requires that the tag GENERATE_HTML is set to YES. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used +# to set the initial width (in pixels) of the frame in which the tree is shown. +# Minimum value: 0, maximum value: 1500, default value: 250. +# This tag requires that the tag GENERATE_HTML is set to YES. + +TREEVIEW_WIDTH = 250 + +# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to +# external symbols imported via tag files in a separate window. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of LaTeX formulas included as images in +# the HTML documentation. When you change the font size after a successful +# doxygen run you need to manually remove any form_*.png images from the HTML +# output directory to force them to be regenerated. +# Minimum value: 8, maximum value: 50, default value: 10. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANSPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are not +# supported properly for IE 6.0, but are supported on all modern browsers. +# +# Note that when changing this option you need to delete any form_*.png files in +# the HTML output directory before the changes have effect. +# The default value is: YES. +# This tag requires that the tag GENERATE_HTML is set to YES. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see +# https://www.mathjax.org) which uses client side Javascript for the rendering +# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX +# installed or if you want to formulas look prettier in the HTML output. When +# enabled you may also need to install MathJax separately and configure the path +# to it using the MATHJAX_RELPATH option. +# The default value is: NO. +# This tag requires that the tag GENERATE_HTML is set to YES. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# the MathJax output. See the MathJax site (see: +# http://docs.mathjax.org/en/latest/output.html) for more details. +# Possible values are: HTML-CSS (which is slower, but has the best +# compatibility), NativeMML (i.e. MathML) and SVG. +# The default value is: HTML-CSS. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the HTML +# output directory using the MATHJAX_RELPATH option. The destination directory +# should contain the MathJax.js script. For instance, if the mathjax directory +# is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax +# Content Delivery Network so you can quickly see the result without installing +# MathJax. However, it is strongly recommended to install a local copy of +# MathJax from https://www.mathjax.org before deployment. +# The default value is: https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.5/. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_RELPATH = https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.5/ + +# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax +# extension names that should be enabled during MathJax rendering. For example +# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_EXTENSIONS = + +# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces +# of code that will be used on startup of the MathJax code. See the MathJax site +# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an +# example see the documentation. +# This tag requires that the tag USE_MATHJAX is set to YES. + +MATHJAX_CODEFILE = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box for +# the HTML output. The underlying search engine uses javascript and DHTML and +# should work on any modern browser. Note that when using HTML help +# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET) +# there is already a search function so this one should typically be disabled. +# For large projects the javascript based search engine can be slow, then +# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to +# search using the keyboard; to jump to the search box use + S +# (what the is depends on the OS and browser, but it is typically +# , /