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How to model ADC/DAC #279

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jankap opened this issue Mar 27, 2024 · 1 comment

jankap commented Mar 27, 2024

Is it already possible to model ideal and non-ideal analog-digital-converters (ADC) or DACs given the parts in the standard library?

Thanks :)

Contributor

baggepinnen commented Mar 29, 2024

Not quite :/

We are currently lacking

IntegerOutput (DigitalOutput). However, we do now support variables with integer type, so such an output connector could be implemented.
Handling the trigger condition could be done with an event, but events are currently known to have a number of bugs. If the triggering is periodic, it could in principle be implemented as a clocked system, unfortunately, support for this is not complete yet so this alternative is not yet available.

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