mkWSIPatternWorker4B.v

//
// Generated by Bluespec Compiler, version 2012.09.beta1 (build 29570, 2012-09.11)
//
// On Mon Nov  5 13:20:56 EST 2012
//
//
// Ports:
// Name                         I/O  size props
// wciS0_SResp                    O     2 reg
// wciS0_SData                    O    32 reg
// wciS0_SThreadBusy              O     1
// wciS0_SFlag                    O     2
// wsiM0_MCmd                     O     3
// wsiM0_MReqLast                 O     1
// wsiM0_MBurstPrecise            O     1
// wsiM0_MBurstLength             O    12
// wsiM0_MData                    O    32 reg
// wsiM0_MByteEn                  O     4 reg
// wsiM0_MReqInfo                 O     8
// wsiM0_MReset_n                 O     1
// wciS0_Clk                      I     1 clock
// wciS0_MReset_n                 I     1 reset
// wciS0_MCmd                     I     3
// wciS0_MAddrSpace               I     1
// wciS0_MByteEn                  I     4
// wciS0_MAddr                    I    32
// wciS0_MData                    I    32
// wciS0_MFlag                    I     2 unused
// wsiM0_SThreadBusy              I     1 reg
// wsiM0_SReset_n                 I     1 reg
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkWSIPatternWorker4B(wciS0_Clk,
			    wciS0_MReset_n,

			    wciS0_MCmd,

			    wciS0_MAddrSpace,

			    wciS0_MByteEn,

			    wciS0_MAddr,

			    wciS0_MData,

			    wciS0_SResp,

			    wciS0_SData,

			    wciS0_SThreadBusy,

			    wciS0_SFlag,

			    wciS0_MFlag,

			    wsiM0_MCmd,

			    wsiM0_MReqLast,

			    wsiM0_MBurstPrecise,

			    wsiM0_MBurstLength,

			    wsiM0_MData,

			    wsiM0_MByteEn,

			    wsiM0_MReqInfo,

			    wsiM0_SThreadBusy,

			    wsiM0_MReset_n,

			    wsiM0_SReset_n);
  parameter [0 : 0] hasDebugLogic = 1'b0;
  input  wciS0_Clk;
  input  wciS0_MReset_n;

  // action method wciS0_mCmd
  input  [2 : 0] wciS0_MCmd;

  // action method wciS0_mAddrSpace
  input  wciS0_MAddrSpace;

  // action method wciS0_mByteEn
  input  [3 : 0] wciS0_MByteEn;

  // action method wciS0_mAddr
  input  [31 : 0] wciS0_MAddr;

  // action method wciS0_mData
  input  [31 : 0] wciS0_MData;

  // value method wciS0_sResp
  output [1 : 0] wciS0_SResp;

  // value method wciS0_sData
  output [31 : 0] wciS0_SData;

  // value method wciS0_sThreadBusy
  output wciS0_SThreadBusy;

  // value method wciS0_sFlag
  output [1 : 0] wciS0_SFlag;

  // action method wciS0_mFlag
  input  [1 : 0] wciS0_MFlag;

  // value method wsiM0_mCmd
  output [2 : 0] wsiM0_MCmd;

  // value method wsiM0_mReqLast
  output wsiM0_MReqLast;

  // value method wsiM0_mBurstPrecise
  output wsiM0_MBurstPrecise;

  // value method wsiM0_mBurstLength
  output [11 : 0] wsiM0_MBurstLength;

  // value method wsiM0_mData
  output [31 : 0] wsiM0_MData;

  // value method wsiM0_mByteEn
  output [3 : 0] wsiM0_MByteEn;

  // value method wsiM0_mReqInfo
  output [7 : 0] wsiM0_MReqInfo;

  // value method wsiM0_mDataInfo

  // action method wsiM0_sThreadBusy
  input  wsiM0_SThreadBusy;

  // value method wsiM0_mReset_n
  output wsiM0_MReset_n;

  // action method wsiM0_sReset_n
  input  wsiM0_SReset_n;

  // signals for module outputs
  wire [31 : 0] wciS0_SData, wsiM0_MData;
  wire [11 : 0] wsiM0_MBurstLength;
  wire [7 : 0] wsiM0_MReqInfo;
  wire [3 : 0] wsiM0_MByteEn;
  wire [2 : 0] wsiM0_MCmd;
  wire [1 : 0] wciS0_SFlag, wciS0_SResp;
  wire wciS0_SThreadBusy, wsiM0_MBurstPrecise, wsiM0_MReqLast, wsiM0_MReset_n;

  // inlined wires
  wire [95 : 0] wsiM_extStatusW$wget;
  wire [71 : 0] wci_wslv_wciReq$wget;
  wire [60 : 0] wsiM_reqFifo_x_wire$wget;
  wire [33 : 0] wci_wslv_respF_x_wire$wget;
  wire [31 : 0] dataBram_serverAdapterA_outData_enqData$wget,
		dataBram_serverAdapterA_outData_outData$wget,
		dataBram_serverAdapterB_outData_enqData$wget,
		dataBram_serverAdapterB_outData_outData$wget,
		metaBram_serverAdapterA_1_outData_enqData$wget,
		metaBram_serverAdapterA_1_outData_outData$wget,
		metaBram_serverAdapterA_2_outData_enqData$wget,
		metaBram_serverAdapterA_2_outData_outData$wget,
		metaBram_serverAdapterA_3_outData_enqData$wget,
		metaBram_serverAdapterA_3_outData_outData$wget,
		metaBram_serverAdapterA_outData_enqData$wget,
		metaBram_serverAdapterA_outData_outData$wget,
		metaBram_serverAdapterB_1_outData_enqData$wget,
		metaBram_serverAdapterB_1_outData_outData$wget,
		metaBram_serverAdapterB_2_outData_enqData$wget,
		metaBram_serverAdapterB_2_outData_outData$wget,
		metaBram_serverAdapterB_3_outData_enqData$wget,
		metaBram_serverAdapterB_3_outData_outData$wget,
		metaBram_serverAdapterB_outData_enqData$wget,
		metaBram_serverAdapterB_outData_outData$wget,
		statusReg_w$wget,
		wci_wci_Es_mAddr_w$wget,
		wci_wci_Es_mData_w$wget;
  wire [15 : 0] metaPtr_modulus_bw$wget;
  wire [3 : 0] wci_wci_Es_mByteEn_w$wget;
  wire [2 : 0] dataBram_serverAdapterA_cnt_1$wget,
	       dataBram_serverAdapterA_cnt_2$wget,
	       dataBram_serverAdapterA_cnt_3$wget,
	       dataBram_serverAdapterB_cnt_1$wget,
	       dataBram_serverAdapterB_cnt_2$wget,
	       dataBram_serverAdapterB_cnt_3$wget,
	       metaBram_serverAdapterA_1_cnt_1$wget,
	       metaBram_serverAdapterA_1_cnt_2$wget,
	       metaBram_serverAdapterA_1_cnt_3$wget,
	       metaBram_serverAdapterA_2_cnt_1$wget,
	       metaBram_serverAdapterA_2_cnt_2$wget,
	       metaBram_serverAdapterA_2_cnt_3$wget,
	       metaBram_serverAdapterA_3_cnt_1$wget,
	       metaBram_serverAdapterA_3_cnt_2$wget,
	       metaBram_serverAdapterA_3_cnt_3$wget,
	       metaBram_serverAdapterA_cnt_1$wget,
	       metaBram_serverAdapterA_cnt_2$wget,
	       metaBram_serverAdapterA_cnt_3$wget,
	       metaBram_serverAdapterB_1_cnt_1$wget,
	       metaBram_serverAdapterB_1_cnt_2$wget,
	       metaBram_serverAdapterB_1_cnt_3$wget,
	       metaBram_serverAdapterB_2_cnt_1$wget,
	       metaBram_serverAdapterB_2_cnt_2$wget,
	       metaBram_serverAdapterB_2_cnt_3$wget,
	       metaBram_serverAdapterB_3_cnt_1$wget,
	       metaBram_serverAdapterB_3_cnt_2$wget,
	       metaBram_serverAdapterB_3_cnt_3$wget,
	       metaBram_serverAdapterB_cnt_1$wget,
	       metaBram_serverAdapterB_cnt_2$wget,
	       metaBram_serverAdapterB_cnt_3$wget,
	       wci_wci_Es_mCmd_w$wget,
	       wci_wslv_wEdge$wget;
  wire [1 : 0] dataBram_serverAdapterA_s1_1$wget,
	       dataBram_serverAdapterA_writeWithResp$wget,
	       dataBram_serverAdapterB_s1_1$wget,
	       dataBram_serverAdapterB_writeWithResp$wget,
	       metaBram_serverAdapterA_1_s1_1$wget,
	       metaBram_serverAdapterA_1_writeWithResp$wget,
	       metaBram_serverAdapterA_2_s1_1$wget,
	       metaBram_serverAdapterA_2_writeWithResp$wget,
	       metaBram_serverAdapterA_3_s1_1$wget,
	       metaBram_serverAdapterA_3_writeWithResp$wget,
	       metaBram_serverAdapterA_s1_1$wget,
	       metaBram_serverAdapterA_writeWithResp$wget,
	       metaBram_serverAdapterB_1_s1_1$wget,
	       metaBram_serverAdapterB_1_writeWithResp$wget,
	       metaBram_serverAdapterB_2_s1_1$wget,
	       metaBram_serverAdapterB_2_writeWithResp$wget,
	       metaBram_serverAdapterB_3_s1_1$wget,
	       metaBram_serverAdapterB_3_writeWithResp$wget,
	       metaBram_serverAdapterB_s1_1$wget,
	       metaBram_serverAdapterB_writeWithResp$wget;
  wire dataBram_serverAdapterA_cnt_1$whas,
       dataBram_serverAdapterA_cnt_2$whas,
       dataBram_serverAdapterA_cnt_3$whas,
       dataBram_serverAdapterA_outData_deqCalled$whas,
       dataBram_serverAdapterA_outData_enqData$whas,
       dataBram_serverAdapterA_outData_outData$whas,
       dataBram_serverAdapterA_s1_1$whas,
       dataBram_serverAdapterA_writeWithResp$whas,
       dataBram_serverAdapterB_cnt_1$whas,
       dataBram_serverAdapterB_cnt_2$whas,
       dataBram_serverAdapterB_cnt_3$whas,
       dataBram_serverAdapterB_outData_deqCalled$whas,
       dataBram_serverAdapterB_outData_enqData$whas,
       dataBram_serverAdapterB_outData_outData$whas,
       dataBram_serverAdapterB_s1_1$whas,
       dataBram_serverAdapterB_writeWithResp$whas,
       metaBram_serverAdapterA_1_cnt_1$whas,
       metaBram_serverAdapterA_1_cnt_2$whas,
       metaBram_serverAdapterA_1_cnt_3$whas,
       metaBram_serverAdapterA_1_outData_deqCalled$whas,
       metaBram_serverAdapterA_1_outData_enqData$whas,
       metaBram_serverAdapterA_1_outData_outData$whas,
       metaBram_serverAdapterA_1_s1_1$whas,
       metaBram_serverAdapterA_1_writeWithResp$whas,
       metaBram_serverAdapterA_2_cnt_1$whas,
       metaBram_serverAdapterA_2_cnt_2$whas,
       metaBram_serverAdapterA_2_cnt_3$whas,
       metaBram_serverAdapterA_2_outData_deqCalled$whas,
       metaBram_serverAdapterA_2_outData_enqData$whas,
       metaBram_serverAdapterA_2_outData_outData$whas,
       metaBram_serverAdapterA_2_s1_1$whas,
       metaBram_serverAdapterA_2_writeWithResp$whas,
       metaBram_serverAdapterA_3_cnt_1$whas,
       metaBram_serverAdapterA_3_cnt_2$whas,
       metaBram_serverAdapterA_3_cnt_3$whas,
       metaBram_serverAdapterA_3_outData_deqCalled$whas,
       metaBram_serverAdapterA_3_outData_enqData$whas,
       metaBram_serverAdapterA_3_outData_outData$whas,
       metaBram_serverAdapterA_3_s1_1$whas,
       metaBram_serverAdapterA_3_writeWithResp$whas,
       metaBram_serverAdapterA_cnt_1$whas,
       metaBram_serverAdapterA_cnt_2$whas,
       metaBram_serverAdapterA_cnt_3$whas,
       metaBram_serverAdapterA_outData_deqCalled$whas,
       metaBram_serverAdapterA_outData_enqData$whas,
       metaBram_serverAdapterA_outData_outData$whas,
       metaBram_serverAdapterA_s1_1$whas,
       metaBram_serverAdapterA_writeWithResp$whas,
       metaBram_serverAdapterB_1_cnt_1$whas,
       metaBram_serverAdapterB_1_cnt_2$whas,
       metaBram_serverAdapterB_1_cnt_3$whas,
       metaBram_serverAdapterB_1_outData_deqCalled$whas,
       metaBram_serverAdapterB_1_outData_enqData$whas,
       metaBram_serverAdapterB_1_outData_outData$whas,
       metaBram_serverAdapterB_1_s1_1$whas,
       metaBram_serverAdapterB_1_writeWithResp$whas,
       metaBram_serverAdapterB_2_cnt_1$whas,
       metaBram_serverAdapterB_2_cnt_2$whas,
       metaBram_serverAdapterB_2_cnt_3$whas,
       metaBram_serverAdapterB_2_outData_deqCalled$whas,
       metaBram_serverAdapterB_2_outData_enqData$whas,
       metaBram_serverAdapterB_2_outData_outData$whas,
       metaBram_serverAdapterB_2_s1_1$whas,
       metaBram_serverAdapterB_2_writeWithResp$whas,
       metaBram_serverAdapterB_3_cnt_1$whas,
       metaBram_serverAdapterB_3_cnt_2$whas,
       metaBram_serverAdapterB_3_cnt_3$whas,
       metaBram_serverAdapterB_3_outData_deqCalled$whas,
       metaBram_serverAdapterB_3_outData_enqData$whas,
       metaBram_serverAdapterB_3_outData_outData$whas,
       metaBram_serverAdapterB_3_s1_1$whas,
       metaBram_serverAdapterB_3_writeWithResp$whas,
       metaBram_serverAdapterB_cnt_1$whas,
       metaBram_serverAdapterB_cnt_2$whas,
       metaBram_serverAdapterB_cnt_3$whas,
       metaBram_serverAdapterB_outData_deqCalled$whas,
       metaBram_serverAdapterB_outData_enqData$whas,
       metaBram_serverAdapterB_outData_outData$whas,
       metaBram_serverAdapterB_s1_1$whas,
       metaBram_serverAdapterB_writeWithResp$whas,
       metaPtr_decAction$whas,
       metaPtr_incAction$whas,
       statusReg_w$whas,
       wci_wci_Es_mAddrSpace_w$wget,
       wci_wci_Es_mAddrSpace_w$whas,
       wci_wci_Es_mAddr_w$whas,
       wci_wci_Es_mByteEn_w$whas,
       wci_wci_Es_mCmd_w$whas,
       wci_wci_Es_mData_w$whas,
       wci_wslv_ctlAckReg_1$wget,
       wci_wslv_ctlAckReg_1$whas,
       wci_wslv_reqF_r_clr$whas,
       wci_wslv_reqF_r_deq$whas,
       wci_wslv_reqF_r_enq$whas,
       wci_wslv_respF_dequeueing$whas,
       wci_wslv_respF_enqueueing$whas,
       wci_wslv_respF_x_wire$whas,
       wci_wslv_sFlagReg_1$wget,
       wci_wslv_sFlagReg_1$whas,
       wci_wslv_sThreadBusy_pw$whas,
       wci_wslv_wEdge$whas,
       wci_wslv_wciReq$whas,
       wci_wslv_wci_cfrd_pw$whas,
       wci_wslv_wci_cfwr_pw$whas,
       wci_wslv_wci_ctrl_pw$whas,
       wsiM_operateD_1$wget,
       wsiM_operateD_1$whas,
       wsiM_peerIsReady_1$wget,
       wsiM_peerIsReady_1$whas,
       wsiM_reqFifo_dequeueing$whas,
       wsiM_reqFifo_enqueueing$whas,
       wsiM_reqFifo_x_wire$whas,
       wsiM_sThreadBusy_pw$whas;

  // register bytesRemain
  reg [31 : 0] bytesRemain;
  wire [31 : 0] bytesRemain$D_IN;
  wire bytesRemain$EN;

  // register controlReg
  reg [31 : 0] controlReg;
  wire [31 : 0] controlReg$D_IN;
  wire controlReg$EN;

  // register dataBram_serverAdapterA_cnt
  reg [2 : 0] dataBram_serverAdapterA_cnt;
  wire [2 : 0] dataBram_serverAdapterA_cnt$D_IN;
  wire dataBram_serverAdapterA_cnt$EN;

  // register dataBram_serverAdapterA_s1
  reg [1 : 0] dataBram_serverAdapterA_s1;
  wire [1 : 0] dataBram_serverAdapterA_s1$D_IN;
  wire dataBram_serverAdapterA_s1$EN;

  // register dataBram_serverAdapterB_cnt
  reg [2 : 0] dataBram_serverAdapterB_cnt;
  wire [2 : 0] dataBram_serverAdapterB_cnt$D_IN;
  wire dataBram_serverAdapterB_cnt$EN;

  // register dataBram_serverAdapterB_s1
  reg [1 : 0] dataBram_serverAdapterB_s1;
  wire [1 : 0] dataBram_serverAdapterB_s1$D_IN;
  wire dataBram_serverAdapterB_s1$EN;

  // register dataCount
  reg [31 : 0] dataCount;
  reg [31 : 0] dataCount$D_IN;
  wire dataCount$EN;

  // register dataPtr
  reg [31 : 0] dataPtr;
  wire [31 : 0] dataPtr$D_IN;
  wire dataPtr$EN;

  // register doZLM
  reg doZLM;
  wire doZLM$D_IN, doZLM$EN;

  // register isFirst
  reg isFirst;
  wire isFirst$D_IN, isFirst$EN;

  // register mesgCount
  reg [31 : 0] mesgCount;
  reg [31 : 0] mesgCount$D_IN;
  wire mesgCount$EN;

  // register mesgLengthSoFar
  reg [13 : 0] mesgLengthSoFar;
  wire [13 : 0] mesgLengthSoFar$D_IN;
  wire mesgLengthSoFar$EN;

  // register mesgRemain
  reg [31 : 0] mesgRemain;
  wire [31 : 0] mesgRemain$D_IN;
  wire mesgRemain$EN;

  // register metaBram_serverAdapterA_1_cnt
  reg [2 : 0] metaBram_serverAdapterA_1_cnt;
  wire [2 : 0] metaBram_serverAdapterA_1_cnt$D_IN;
  wire metaBram_serverAdapterA_1_cnt$EN;

  // register metaBram_serverAdapterA_1_s1
  reg [1 : 0] metaBram_serverAdapterA_1_s1;
  wire [1 : 0] metaBram_serverAdapterA_1_s1$D_IN;
  wire metaBram_serverAdapterA_1_s1$EN;

  // register metaBram_serverAdapterA_2_cnt
  reg [2 : 0] metaBram_serverAdapterA_2_cnt;
  wire [2 : 0] metaBram_serverAdapterA_2_cnt$D_IN;
  wire metaBram_serverAdapterA_2_cnt$EN;

  // register metaBram_serverAdapterA_2_s1
  reg [1 : 0] metaBram_serverAdapterA_2_s1;
  wire [1 : 0] metaBram_serverAdapterA_2_s1$D_IN;
  wire metaBram_serverAdapterA_2_s1$EN;

  // register metaBram_serverAdapterA_3_cnt
  reg [2 : 0] metaBram_serverAdapterA_3_cnt;
  wire [2 : 0] metaBram_serverAdapterA_3_cnt$D_IN;
  wire metaBram_serverAdapterA_3_cnt$EN;

  // register metaBram_serverAdapterA_3_s1
  reg [1 : 0] metaBram_serverAdapterA_3_s1;
  wire [1 : 0] metaBram_serverAdapterA_3_s1$D_IN;
  wire metaBram_serverAdapterA_3_s1$EN;

  // register metaBram_serverAdapterA_cnt
  reg [2 : 0] metaBram_serverAdapterA_cnt;
  wire [2 : 0] metaBram_serverAdapterA_cnt$D_IN;
  wire metaBram_serverAdapterA_cnt$EN;

  // register metaBram_serverAdapterA_s1
  reg [1 : 0] metaBram_serverAdapterA_s1;
  wire [1 : 0] metaBram_serverAdapterA_s1$D_IN;
  wire metaBram_serverAdapterA_s1$EN;

  // register metaBram_serverAdapterB_1_cnt
  reg [2 : 0] metaBram_serverAdapterB_1_cnt;
  wire [2 : 0] metaBram_serverAdapterB_1_cnt$D_IN;
  wire metaBram_serverAdapterB_1_cnt$EN;

  // register metaBram_serverAdapterB_1_s1
  reg [1 : 0] metaBram_serverAdapterB_1_s1;
  wire [1 : 0] metaBram_serverAdapterB_1_s1$D_IN;
  wire metaBram_serverAdapterB_1_s1$EN;

  // register metaBram_serverAdapterB_2_cnt
  reg [2 : 0] metaBram_serverAdapterB_2_cnt;
  wire [2 : 0] metaBram_serverAdapterB_2_cnt$D_IN;
  wire metaBram_serverAdapterB_2_cnt$EN;

  // register metaBram_serverAdapterB_2_s1
  reg [1 : 0] metaBram_serverAdapterB_2_s1;
  wire [1 : 0] metaBram_serverAdapterB_2_s1$D_IN;
  wire metaBram_serverAdapterB_2_s1$EN;

  // register metaBram_serverAdapterB_3_cnt
  reg [2 : 0] metaBram_serverAdapterB_3_cnt;
  wire [2 : 0] metaBram_serverAdapterB_3_cnt$D_IN;
  wire metaBram_serverAdapterB_3_cnt$EN;

  // register metaBram_serverAdapterB_3_s1
  reg [1 : 0] metaBram_serverAdapterB_3_s1;
  wire [1 : 0] metaBram_serverAdapterB_3_s1$D_IN;
  wire metaBram_serverAdapterB_3_s1$EN;

  // register metaBram_serverAdapterB_cnt
  reg [2 : 0] metaBram_serverAdapterB_cnt;
  wire [2 : 0] metaBram_serverAdapterB_cnt$D_IN;
  wire metaBram_serverAdapterB_cnt$EN;

  // register metaBram_serverAdapterB_s1
  reg [1 : 0] metaBram_serverAdapterB_s1;
  wire [1 : 0] metaBram_serverAdapterB_s1$D_IN;
  wire metaBram_serverAdapterB_s1$EN;

  // register metaPtr_modulus
  reg [15 : 0] metaPtr_modulus;
  wire [15 : 0] metaPtr_modulus$D_IN;
  wire metaPtr_modulus$EN;

  // register metaPtr_value
  reg [15 : 0] metaPtr_value;
  wire [15 : 0] metaPtr_value$D_IN;
  wire metaPtr_value$EN;

  // register splitReadInFlight
  reg splitReadInFlight;
  wire splitReadInFlight$D_IN, splitReadInFlight$EN;

  // register thisLength
  reg [31 : 0] thisLength;
  wire [31 : 0] thisLength$D_IN;
  wire thisLength$EN;

  // register thisOpcode
  reg [31 : 0] thisOpcode;
  wire [31 : 0] thisOpcode$D_IN;
  wire thisOpcode$EN;

  // register thisTLS
  reg [31 : 0] thisTLS;
  wire [31 : 0] thisTLS$D_IN;
  wire thisTLS$EN;

  // register thisTMS
  reg [31 : 0] thisTMS;
  wire [31 : 0] thisTMS$D_IN;
  wire thisTMS$EN;

  // register unrollCnt
  reg [15 : 0] unrollCnt;
  wire [15 : 0] unrollCnt$D_IN;
  wire unrollCnt$EN;

  // register wci_wslv_cEdge
  reg [2 : 0] wci_wslv_cEdge;
  wire [2 : 0] wci_wslv_cEdge$D_IN;
  wire wci_wslv_cEdge$EN;

  // register wci_wslv_cState
  reg [2 : 0] wci_wslv_cState;
  wire [2 : 0] wci_wslv_cState$D_IN;
  wire wci_wslv_cState$EN;

  // register wci_wslv_ctlAckReg
  reg wci_wslv_ctlAckReg;
  wire wci_wslv_ctlAckReg$D_IN, wci_wslv_ctlAckReg$EN;

  // register wci_wslv_ctlOpActive
  reg wci_wslv_ctlOpActive;
  wire wci_wslv_ctlOpActive$D_IN, wci_wslv_ctlOpActive$EN;

  // register wci_wslv_illegalEdge
  reg wci_wslv_illegalEdge;
  wire wci_wslv_illegalEdge$D_IN, wci_wslv_illegalEdge$EN;

  // register wci_wslv_isReset_isInReset
  reg wci_wslv_isReset_isInReset;
  wire wci_wslv_isReset_isInReset$D_IN, wci_wslv_isReset_isInReset$EN;

  // register wci_wslv_nState
  reg [2 : 0] wci_wslv_nState;
  reg [2 : 0] wci_wslv_nState$D_IN;
  wire wci_wslv_nState$EN;

  // register wci_wslv_reqF_countReg
  reg [1 : 0] wci_wslv_reqF_countReg;
  wire [1 : 0] wci_wslv_reqF_countReg$D_IN;
  wire wci_wslv_reqF_countReg$EN;

  // register wci_wslv_respF_c_r
  reg [1 : 0] wci_wslv_respF_c_r;
  wire [1 : 0] wci_wslv_respF_c_r$D_IN;
  wire wci_wslv_respF_c_r$EN;

  // register wci_wslv_respF_q_0
  reg [33 : 0] wci_wslv_respF_q_0;
  reg [33 : 0] wci_wslv_respF_q_0$D_IN;
  wire wci_wslv_respF_q_0$EN;

  // register wci_wslv_respF_q_1
  reg [33 : 0] wci_wslv_respF_q_1;
  reg [33 : 0] wci_wslv_respF_q_1$D_IN;
  wire wci_wslv_respF_q_1$EN;

  // register wci_wslv_sFlagReg
  reg wci_wslv_sFlagReg;
  wire wci_wslv_sFlagReg$D_IN, wci_wslv_sFlagReg$EN;

  // register wci_wslv_sThreadBusy_d
  reg wci_wslv_sThreadBusy_d;
  wire wci_wslv_sThreadBusy_d$D_IN, wci_wslv_sThreadBusy_d$EN;

  // register wsiM_burstKind
  reg [1 : 0] wsiM_burstKind;
  wire [1 : 0] wsiM_burstKind$D_IN;
  wire wsiM_burstKind$EN;

  // register wsiM_errorSticky
  reg wsiM_errorSticky;
  wire wsiM_errorSticky$D_IN, wsiM_errorSticky$EN;

  // register wsiM_iMesgCount
  reg [31 : 0] wsiM_iMesgCount;
  wire [31 : 0] wsiM_iMesgCount$D_IN;
  wire wsiM_iMesgCount$EN;

  // register wsiM_isReset_isInReset
  reg wsiM_isReset_isInReset;
  wire wsiM_isReset_isInReset$D_IN, wsiM_isReset_isInReset$EN;

  // register wsiM_operateD
  reg wsiM_operateD;
  wire wsiM_operateD$D_IN, wsiM_operateD$EN;

  // register wsiM_pMesgCount
  reg [31 : 0] wsiM_pMesgCount;
  wire [31 : 0] wsiM_pMesgCount$D_IN;
  wire wsiM_pMesgCount$EN;

  // register wsiM_peerIsReady
  reg wsiM_peerIsReady;
  wire wsiM_peerIsReady$D_IN, wsiM_peerIsReady$EN;

  // register wsiM_reqFifo_c_r
  reg [1 : 0] wsiM_reqFifo_c_r;
  wire [1 : 0] wsiM_reqFifo_c_r$D_IN;
  wire wsiM_reqFifo_c_r$EN;

  // register wsiM_reqFifo_q_0
  reg [60 : 0] wsiM_reqFifo_q_0;
  reg [60 : 0] wsiM_reqFifo_q_0$D_IN;
  wire wsiM_reqFifo_q_0$EN;

  // register wsiM_reqFifo_q_1
  reg [60 : 0] wsiM_reqFifo_q_1;
  reg [60 : 0] wsiM_reqFifo_q_1$D_IN;
  wire wsiM_reqFifo_q_1$EN;

  // register wsiM_sThreadBusy_d
  reg wsiM_sThreadBusy_d;
  wire wsiM_sThreadBusy_d$D_IN, wsiM_sThreadBusy_d$EN;

  // register wsiM_statusR
  reg [7 : 0] wsiM_statusR;
  wire [7 : 0] wsiM_statusR$D_IN;
  wire wsiM_statusR$EN;

  // register wsiM_tBusyCount
  reg [31 : 0] wsiM_tBusyCount;
  wire [31 : 0] wsiM_tBusyCount$D_IN;
  wire wsiM_tBusyCount$EN;

  // register wsiM_trafficSticky
  reg wsiM_trafficSticky;
  wire wsiM_trafficSticky$D_IN, wsiM_trafficSticky$EN;

  // ports of submodule dataBram_memory
  wire [31 : 0] dataBram_memory$DIA,
		dataBram_memory$DIB,
		dataBram_memory$DOA,
		dataBram_memory$DOB;
  wire [9 : 0] dataBram_memory$ADDRA, dataBram_memory$ADDRB;
  wire dataBram_memory$ENA,
       dataBram_memory$ENB,
       dataBram_memory$WEA,
       dataBram_memory$WEB;

  // ports of submodule dataBram_serverAdapterA_outDataCore
  wire [31 : 0] dataBram_serverAdapterA_outDataCore$D_IN,
		dataBram_serverAdapterA_outDataCore$D_OUT;
  wire dataBram_serverAdapterA_outDataCore$CLR,
       dataBram_serverAdapterA_outDataCore$DEQ,
       dataBram_serverAdapterA_outDataCore$EMPTY_N,
       dataBram_serverAdapterA_outDataCore$ENQ,
       dataBram_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule dataBram_serverAdapterB_outDataCore
  wire [31 : 0] dataBram_serverAdapterB_outDataCore$D_IN,
		dataBram_serverAdapterB_outDataCore$D_OUT;
  wire dataBram_serverAdapterB_outDataCore$CLR,
       dataBram_serverAdapterB_outDataCore$DEQ,
       dataBram_serverAdapterB_outDataCore$EMPTY_N,
       dataBram_serverAdapterB_outDataCore$ENQ,
       dataBram_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule loopReqInFlightF
  wire loopReqInFlightF$CLR,
       loopReqInFlightF$DEQ,
       loopReqInFlightF$EMPTY_N,
       loopReqInFlightF$ENQ,
       loopReqInFlightF$FULL_N;

  // ports of submodule metaBram_memory
  wire [31 : 0] metaBram_memory$DIA,
		metaBram_memory$DIB,
		metaBram_memory$DOA,
		metaBram_memory$DOB;
  wire [9 : 0] metaBram_memory$ADDRA, metaBram_memory$ADDRB;
  wire metaBram_memory$ENA,
       metaBram_memory$ENB,
       metaBram_memory$WEA,
       metaBram_memory$WEB;

  // ports of submodule metaBram_memory_1
  wire [31 : 0] metaBram_memory_1$DIA,
		metaBram_memory_1$DIB,
		metaBram_memory_1$DOA,
		metaBram_memory_1$DOB;
  wire [9 : 0] metaBram_memory_1$ADDRA, metaBram_memory_1$ADDRB;
  wire metaBram_memory_1$ENA,
       metaBram_memory_1$ENB,
       metaBram_memory_1$WEA,
       metaBram_memory_1$WEB;

  // ports of submodule metaBram_memory_2
  wire [31 : 0] metaBram_memory_2$DIA,
		metaBram_memory_2$DIB,
		metaBram_memory_2$DOA,
		metaBram_memory_2$DOB;
  wire [9 : 0] metaBram_memory_2$ADDRA, metaBram_memory_2$ADDRB;
  wire metaBram_memory_2$ENA,
       metaBram_memory_2$ENB,
       metaBram_memory_2$WEA,
       metaBram_memory_2$WEB;

  // ports of submodule metaBram_memory_3
  wire [31 : 0] metaBram_memory_3$DIA,
		metaBram_memory_3$DIB,
		metaBram_memory_3$DOA,
		metaBram_memory_3$DOB;
  wire [9 : 0] metaBram_memory_3$ADDRA, metaBram_memory_3$ADDRB;
  wire metaBram_memory_3$ENA,
       metaBram_memory_3$ENB,
       metaBram_memory_3$WEA,
       metaBram_memory_3$WEB;

  // ports of submodule metaBram_serverAdapterA_1_outDataCore
  wire [31 : 0] metaBram_serverAdapterA_1_outDataCore$D_IN,
		metaBram_serverAdapterA_1_outDataCore$D_OUT;
  wire metaBram_serverAdapterA_1_outDataCore$CLR,
       metaBram_serverAdapterA_1_outDataCore$DEQ,
       metaBram_serverAdapterA_1_outDataCore$EMPTY_N,
       metaBram_serverAdapterA_1_outDataCore$ENQ,
       metaBram_serverAdapterA_1_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterA_2_outDataCore
  wire [31 : 0] metaBram_serverAdapterA_2_outDataCore$D_IN,
		metaBram_serverAdapterA_2_outDataCore$D_OUT;
  wire metaBram_serverAdapterA_2_outDataCore$CLR,
       metaBram_serverAdapterA_2_outDataCore$DEQ,
       metaBram_serverAdapterA_2_outDataCore$EMPTY_N,
       metaBram_serverAdapterA_2_outDataCore$ENQ,
       metaBram_serverAdapterA_2_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterA_3_outDataCore
  wire [31 : 0] metaBram_serverAdapterA_3_outDataCore$D_IN,
		metaBram_serverAdapterA_3_outDataCore$D_OUT;
  wire metaBram_serverAdapterA_3_outDataCore$CLR,
       metaBram_serverAdapterA_3_outDataCore$DEQ,
       metaBram_serverAdapterA_3_outDataCore$EMPTY_N,
       metaBram_serverAdapterA_3_outDataCore$ENQ,
       metaBram_serverAdapterA_3_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterA_outDataCore
  wire [31 : 0] metaBram_serverAdapterA_outDataCore$D_IN,
		metaBram_serverAdapterA_outDataCore$D_OUT;
  wire metaBram_serverAdapterA_outDataCore$CLR,
       metaBram_serverAdapterA_outDataCore$DEQ,
       metaBram_serverAdapterA_outDataCore$EMPTY_N,
       metaBram_serverAdapterA_outDataCore$ENQ,
       metaBram_serverAdapterA_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterB_1_outDataCore
  wire [31 : 0] metaBram_serverAdapterB_1_outDataCore$D_IN,
		metaBram_serverAdapterB_1_outDataCore$D_OUT;
  wire metaBram_serverAdapterB_1_outDataCore$CLR,
       metaBram_serverAdapterB_1_outDataCore$DEQ,
       metaBram_serverAdapterB_1_outDataCore$EMPTY_N,
       metaBram_serverAdapterB_1_outDataCore$ENQ,
       metaBram_serverAdapterB_1_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterB_2_outDataCore
  wire [31 : 0] metaBram_serverAdapterB_2_outDataCore$D_IN,
		metaBram_serverAdapterB_2_outDataCore$D_OUT;
  wire metaBram_serverAdapterB_2_outDataCore$CLR,
       metaBram_serverAdapterB_2_outDataCore$DEQ,
       metaBram_serverAdapterB_2_outDataCore$EMPTY_N,
       metaBram_serverAdapterB_2_outDataCore$ENQ,
       metaBram_serverAdapterB_2_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterB_3_outDataCore
  wire [31 : 0] metaBram_serverAdapterB_3_outDataCore$D_IN,
		metaBram_serverAdapterB_3_outDataCore$D_OUT;
  wire metaBram_serverAdapterB_3_outDataCore$CLR,
       metaBram_serverAdapterB_3_outDataCore$DEQ,
       metaBram_serverAdapterB_3_outDataCore$EMPTY_N,
       metaBram_serverAdapterB_3_outDataCore$ENQ,
       metaBram_serverAdapterB_3_outDataCore$FULL_N;

  // ports of submodule metaBram_serverAdapterB_outDataCore
  wire [31 : 0] metaBram_serverAdapterB_outDataCore$D_IN,
		metaBram_serverAdapterB_outDataCore$D_OUT;
  wire metaBram_serverAdapterB_outDataCore$CLR,
       metaBram_serverAdapterB_outDataCore$DEQ,
       metaBram_serverAdapterB_outDataCore$EMPTY_N,
       metaBram_serverAdapterB_outDataCore$ENQ,
       metaBram_serverAdapterB_outDataCore$FULL_N;

  // ports of submodule metaReqInFlightF
  wire metaReqInFlightF$CLR,
       metaReqInFlightF$DEQ,
       metaReqInFlightF$EMPTY_N,
       metaReqInFlightF$ENQ,
       metaReqInFlightF$FULL_N;

  // ports of submodule splaF
  wire [2 : 0] splaF$D_IN, splaF$D_OUT;
  wire splaF$CLR, splaF$DEQ, splaF$EMPTY_N, splaF$ENQ, splaF$FULL_N;

  // ports of submodule wci_wslv_reqF
  wire [71 : 0] wci_wslv_reqF$D_IN, wci_wslv_reqF$D_OUT;
  wire wci_wslv_reqF$CLR,
       wci_wslv_reqF$DEQ,
       wci_wslv_reqF$EMPTY_N,
       wci_wslv_reqF$ENQ;

  // rule scheduling signals
  wire CAN_FIRE_RL_wci_cfrd,
       CAN_FIRE_RL_wci_cfwr,
       WILL_FIRE_RL_dataBram_serverAdapterA_outData_enqAndDeq,
       WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways,
       WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterA_1_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterA_2_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterA_3_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterA_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways,
       WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq,
       WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq,
       WILL_FIRE_RL_wci_cfrd,
       WILL_FIRE_RL_wci_cfwr,
       WILL_FIRE_RL_wci_ctrl_IsO,
       WILL_FIRE_RL_wci_ctrl_OrE,
       WILL_FIRE_RL_wci_wslv_ctl_op_complete,
       WILL_FIRE_RL_wci_wslv_ctl_op_start,
       WILL_FIRE_RL_wci_wslv_respF_both,
       WILL_FIRE_RL_wci_wslv_respF_decCtr,
       WILL_FIRE_RL_wci_wslv_respF_incCtr,
       WILL_FIRE_RL_wsiM_reqFifo_both,
       WILL_FIRE_RL_wsiM_reqFifo_decCtr,
       WILL_FIRE_RL_wsiM_reqFifo_deq,
       WILL_FIRE_RL_wsiM_reqFifo_incCtr;

  // inputs to muxes for submodule ports
  reg [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_2;
  wire [60 : 0] MUX_wsiM_reqFifo_q_0$write_1__VAL_1,
		MUX_wsiM_reqFifo_q_0$write_1__VAL_2,
		MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
  wire [33 : 0] MUX_wci_wslv_respF_q_0$write_1__VAL_1,
		MUX_wci_wslv_respF_q_1$write_1__VAL_1,
		MUX_wci_wslv_respF_x_wire$wset_1__VAL_1,
		MUX_wci_wslv_respF_x_wire$wset_1__VAL_2,
		MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
  wire [31 : 0] MUX_bytesRemain$write_1__VAL_2,
		MUX_dataCount$write_1__VAL_2,
		MUX_mesgCount$write_1__VAL_2,
		MUX_mesgRemain$write_1__VAL_2;
  wire [15 : 0] MUX_metaPtr_modulus$write_1__VAL_1,
		MUX_metaPtr_value$write_1__VAL_3,
		MUX_unrollCnt$write_1__VAL_1,
		MUX_unrollCnt$write_1__VAL_2;
  wire [1 : 0] MUX_wci_wslv_respF_c_r$write_1__VAL_1,
	       MUX_wci_wslv_respF_c_r$write_1__VAL_2,
	       MUX_wsiM_reqFifo_c_r$write_1__VAL_1,
	       MUX_wsiM_reqFifo_c_r$write_1__VAL_2;
  wire MUX_controlReg$write_1__SEL_1,
       MUX_controlReg$write_1__SEL_2,
       MUX_dataBram_memory$b_put_1__SEL_1,
       MUX_dataBram_memory$b_put_1__SEL_2,
       MUX_dataCount$write_1__SEL_1,
       MUX_mesgCount$write_1__SEL_1,
       MUX_mesgCount$write_1__SEL_2,
       MUX_mesgRemain$write_1__SEL_1,
       MUX_metaBram_memory$b_put_1__SEL_1,
       MUX_metaBram_memory$b_put_1__SEL_2,
       MUX_metaBram_memory_1$b_put_1__SEL_1,
       MUX_metaBram_memory_1$b_put_1__SEL_2,
       MUX_metaBram_memory_2$b_put_1__SEL_1,
       MUX_metaBram_memory_2$b_put_1__SEL_2,
       MUX_metaBram_memory_3$b_put_1__SEL_1,
       MUX_metaBram_memory_3$b_put_1__SEL_2,
       MUX_metaPtr_modulus$write_1__SEL_1,
       MUX_splitReadInFlight$write_1__SEL_1,
       MUX_unrollCnt$write_1__SEL_1,
       MUX_wci_wslv_illegalEdge$write_1__SEL_1,
       MUX_wci_wslv_illegalEdge$write_1__VAL_1,
       MUX_wci_wslv_respF_q_0$write_1__SEL_2,
       MUX_wci_wslv_respF_q_1$write_1__SEL_2,
       MUX_wci_wslv_respF_x_wire$wset_1__SEL_1,
       MUX_wci_wslv_respF_x_wire$wset_1__SEL_3,
       MUX_wsiM_reqFifo_q_0$write_1__SEL_2,
       MUX_wsiM_reqFifo_q_1$write_1__SEL_2;

  // remaining internal signals
  reg [63 : 0] v__h29716,
	       v__h30815,
	       v__h31317,
	       v__h31561,
	       v__h32120,
	       v__h32403,
	       v__h3725,
	       v__h3900,
	       v__h4044;
  reg [31 : 0] IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066,
	       v__h32384;
  reg CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1,
      IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033,
      IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1140;
  wire [31 : 0] b__h25414,
		g_data__h33410,
		rdat___1__h32570,
		rdat___1__h32625,
		rdat___1__h32639,
		rdat___1__h32647,
		residue__h25403,
		v__h24797,
		v__h29897,
		x__h25430,
		x__h26388,
		y_avValue__h30523,
		y_avValue__h30567,
		y_avValue__h30607,
		y_avValue__h30647,
		y_avValue__h30687;
  wire [11 : 0] x_burstLength__h26222;
  wire [3 : 0] x_byteEn__h26224;
  wire [2 : 0] dataBram_serverAdapterA_cnt_74_PLUS_IF_dataBra_ETC___d280,
	       dataBram_serverAdapterB_cnt_33_PLUS_IF_dataBra_ETC___d339,
	       metaBram_serverAdapterA_1_cnt_10_PLUS_IF_metaB_ETC___d516,
	       metaBram_serverAdapterA_2_cnt_28_PLUS_IF_metaB_ETC___d634,
	       metaBram_serverAdapterA_3_cnt_46_PLUS_IF_metaB_ETC___d752,
	       metaBram_serverAdapterA_cnt_92_PLUS_IF_metaBra_ETC___d398,
	       metaBram_serverAdapterB_1_cnt_69_PLUS_IF_metaB_ETC___d575,
	       metaBram_serverAdapterB_2_cnt_87_PLUS_IF_metaB_ETC___d693,
	       metaBram_serverAdapterB_3_cnt_05_PLUS_IF_metaB_ETC___d811,
	       metaBram_serverAdapterB_cnt_51_PLUS_IF_metaBra_ETC___d457;
  wire [1 : 0] ab__h11724, ab__h14842, ab__h17788, ab__h20734, ab__h23680;
  wire IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042,
       IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092,
       IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093,
       IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1422,
       dataBram_serverAdapterB_cnt_33_SLT_3___d1324,
       doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913,
       doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923,
       metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871,
       metaReqInFlightF_i_notEmpty__59_AND_metaBram_s_ETC___d875,
       splaF_i_notEmpty__011_AND_IF_splaF_first__012__ETC___d1044;

  // value method wciS0_sResp
  assign wciS0_SResp = wci_wslv_respF_q_0[33:32] ;

  // value method wciS0_sData
  assign wciS0_SData = wci_wslv_respF_q_0[31:0] ;

  // value method wciS0_sThreadBusy
  assign wciS0_SThreadBusy =
	     wci_wslv_reqF_countReg > 2'd1 || wci_wslv_isReset_isInReset ;

  // value method wciS0_sFlag
  assign wciS0_SFlag = { 1'd1, wci_wslv_sFlagReg } ;

  // value method wsiM0_mCmd
  assign wsiM0_MCmd = wsiM_sThreadBusy_d ? 3'd0 : wsiM_reqFifo_q_0[60:58] ;

  // value method wsiM0_mReqLast
  assign wsiM0_MReqLast = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[57] ;

  // value method wsiM0_mBurstPrecise
  assign wsiM0_MBurstPrecise = !wsiM_sThreadBusy_d && wsiM_reqFifo_q_0[56] ;

  // value method wsiM0_mBurstLength
  assign wsiM0_MBurstLength =
	     wsiM_sThreadBusy_d ? 12'd0 : wsiM_reqFifo_q_0[55:44] ;

  // value method wsiM0_mData
  assign wsiM0_MData = wsiM_reqFifo_q_0[43:12] ;

  // value method wsiM0_mByteEn
  assign wsiM0_MByteEn = wsiM_reqFifo_q_0[11:8] ;

  // value method wsiM0_mReqInfo
  assign wsiM0_MReqInfo = wsiM_sThreadBusy_d ? 8'd0 : wsiM_reqFifo_q_0[7:0] ;

  // value method wsiM0_mReset_n
  assign wsiM0_MReset_n = !wsiM_isReset_isInReset && wsiM_operateD ;

  // submodule dataBram_memory
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) dataBram_memory(.CLKA(wciS0_Clk),
					      .CLKB(wciS0_Clk),
					      .ADDRA(dataBram_memory$ADDRA),
					      .ADDRB(dataBram_memory$ADDRB),
					      .DIA(dataBram_memory$DIA),
					      .DIB(dataBram_memory$DIB),
					      .WEA(dataBram_memory$WEA),
					      .WEB(dataBram_memory$WEB),
					      .ENA(dataBram_memory$ENA),
					      .ENB(dataBram_memory$ENB),
					      .DOA(dataBram_memory$DOA),
					      .DOB(dataBram_memory$DOB));

  // submodule dataBram_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) dataBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
								   .CLK(wciS0_Clk),
								   .D_IN(dataBram_serverAdapterA_outDataCore$D_IN),
								   .ENQ(dataBram_serverAdapterA_outDataCore$ENQ),
								   .DEQ(dataBram_serverAdapterA_outDataCore$DEQ),
								   .CLR(dataBram_serverAdapterA_outDataCore$CLR),
								   .D_OUT(dataBram_serverAdapterA_outDataCore$D_OUT),
								   .FULL_N(dataBram_serverAdapterA_outDataCore$FULL_N),
								   .EMPTY_N(dataBram_serverAdapterA_outDataCore$EMPTY_N));

  // submodule dataBram_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) dataBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
								   .CLK(wciS0_Clk),
								   .D_IN(dataBram_serverAdapterB_outDataCore$D_IN),
								   .ENQ(dataBram_serverAdapterB_outDataCore$ENQ),
								   .DEQ(dataBram_serverAdapterB_outDataCore$DEQ),
								   .CLR(dataBram_serverAdapterB_outDataCore$CLR),
								   .D_OUT(dataBram_serverAdapterB_outDataCore$D_OUT),
								   .FULL_N(dataBram_serverAdapterB_outDataCore$FULL_N),
								   .EMPTY_N(dataBram_serverAdapterB_outDataCore$EMPTY_N));

  // submodule loopReqInFlightF
  FIFO10 #(.guarded(32'd1)) loopReqInFlightF(.RST(wciS0_MReset_n),
					     .CLK(wciS0_Clk),
					     .ENQ(loopReqInFlightF$ENQ),
					     .DEQ(loopReqInFlightF$DEQ),
					     .CLR(loopReqInFlightF$CLR),
					     .FULL_N(loopReqInFlightF$FULL_N),
					     .EMPTY_N(loopReqInFlightF$EMPTY_N));

  // submodule metaBram_memory
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) metaBram_memory(.CLKA(wciS0_Clk),
					      .CLKB(wciS0_Clk),
					      .ADDRA(metaBram_memory$ADDRA),
					      .ADDRB(metaBram_memory$ADDRB),
					      .DIA(metaBram_memory$DIA),
					      .DIB(metaBram_memory$DIB),
					      .WEA(metaBram_memory$WEA),
					      .WEB(metaBram_memory$WEB),
					      .ENA(metaBram_memory$ENA),
					      .ENB(metaBram_memory$ENB),
					      .DOA(metaBram_memory$DOA),
					      .DOB(metaBram_memory$DOB));

  // submodule metaBram_memory_1
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) metaBram_memory_1(.CLKA(wciS0_Clk),
						.CLKB(wciS0_Clk),
						.ADDRA(metaBram_memory_1$ADDRA),
						.ADDRB(metaBram_memory_1$ADDRB),
						.DIA(metaBram_memory_1$DIA),
						.DIB(metaBram_memory_1$DIB),
						.WEA(metaBram_memory_1$WEA),
						.WEB(metaBram_memory_1$WEB),
						.ENA(metaBram_memory_1$ENA),
						.ENB(metaBram_memory_1$ENB),
						.DOA(metaBram_memory_1$DOA),
						.DOB(metaBram_memory_1$DOB));

  // submodule metaBram_memory_2
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) metaBram_memory_2(.CLKA(wciS0_Clk),
						.CLKB(wciS0_Clk),
						.ADDRA(metaBram_memory_2$ADDRA),
						.ADDRB(metaBram_memory_2$ADDRB),
						.DIA(metaBram_memory_2$DIA),
						.DIB(metaBram_memory_2$DIB),
						.WEA(metaBram_memory_2$WEA),
						.WEB(metaBram_memory_2$WEB),
						.ENA(metaBram_memory_2$ENA),
						.ENB(metaBram_memory_2$ENB),
						.DOA(metaBram_memory_2$DOA),
						.DOB(metaBram_memory_2$DOB));

  // submodule metaBram_memory_3
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd10),
	  .DATA_WIDTH(32'd32),
	  .MEMSIZE(11'd1024)) metaBram_memory_3(.CLKA(wciS0_Clk),
						.CLKB(wciS0_Clk),
						.ADDRA(metaBram_memory_3$ADDRA),
						.ADDRB(metaBram_memory_3$ADDRB),
						.DIA(metaBram_memory_3$DIA),
						.DIB(metaBram_memory_3$DIB),
						.WEA(metaBram_memory_3$WEA),
						.WEB(metaBram_memory_3$WEB),
						.ENA(metaBram_memory_3$ENA),
						.ENB(metaBram_memory_3$ENB),
						.DOA(metaBram_memory_3$DOA),
						.DOB(metaBram_memory_3$DOB));

  // submodule metaBram_serverAdapterA_1_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterA_1_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterA_1_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterA_1_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterA_1_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterA_1_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterA_1_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterA_1_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterA_1_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterA_2_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterA_2_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterA_2_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterA_2_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterA_2_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterA_2_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterA_2_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterA_2_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterA_2_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterA_3_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterA_3_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterA_3_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterA_3_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterA_3_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterA_3_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterA_3_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterA_3_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterA_3_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterA_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterA_outDataCore(.RST(wciS0_MReset_n),
								   .CLK(wciS0_Clk),
								   .D_IN(metaBram_serverAdapterA_outDataCore$D_IN),
								   .ENQ(metaBram_serverAdapterA_outDataCore$ENQ),
								   .DEQ(metaBram_serverAdapterA_outDataCore$DEQ),
								   .CLR(metaBram_serverAdapterA_outDataCore$CLR),
								   .D_OUT(metaBram_serverAdapterA_outDataCore$D_OUT),
								   .FULL_N(metaBram_serverAdapterA_outDataCore$FULL_N),
								   .EMPTY_N(metaBram_serverAdapterA_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterB_1_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterB_1_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterB_1_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterB_1_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterB_1_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterB_1_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterB_1_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterB_1_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterB_1_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterB_2_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterB_2_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterB_2_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterB_2_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterB_2_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterB_2_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterB_2_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterB_2_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterB_2_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterB_3_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterB_3_outDataCore(.RST(wciS0_MReset_n),
								     .CLK(wciS0_Clk),
								     .D_IN(metaBram_serverAdapterB_3_outDataCore$D_IN),
								     .ENQ(metaBram_serverAdapterB_3_outDataCore$ENQ),
								     .DEQ(metaBram_serverAdapterB_3_outDataCore$DEQ),
								     .CLR(metaBram_serverAdapterB_3_outDataCore$CLR),
								     .D_OUT(metaBram_serverAdapterB_3_outDataCore$D_OUT),
								     .FULL_N(metaBram_serverAdapterB_3_outDataCore$FULL_N),
								     .EMPTY_N(metaBram_serverAdapterB_3_outDataCore$EMPTY_N));

  // submodule metaBram_serverAdapterB_outDataCore
  SizedFIFO #(.p1width(32'd32),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) metaBram_serverAdapterB_outDataCore(.RST(wciS0_MReset_n),
								   .CLK(wciS0_Clk),
								   .D_IN(metaBram_serverAdapterB_outDataCore$D_IN),
								   .ENQ(metaBram_serverAdapterB_outDataCore$ENQ),
								   .DEQ(metaBram_serverAdapterB_outDataCore$DEQ),
								   .CLR(metaBram_serverAdapterB_outDataCore$CLR),
								   .D_OUT(metaBram_serverAdapterB_outDataCore$D_OUT),
								   .FULL_N(metaBram_serverAdapterB_outDataCore$FULL_N),
								   .EMPTY_N(metaBram_serverAdapterB_outDataCore$EMPTY_N));

  // submodule metaReqInFlightF
  FIFO10 #(.guarded(32'd1)) metaReqInFlightF(.RST(wciS0_MReset_n),
					     .CLK(wciS0_Clk),
					     .ENQ(metaReqInFlightF$ENQ),
					     .DEQ(metaReqInFlightF$DEQ),
					     .CLR(metaReqInFlightF$CLR),
					     .FULL_N(metaReqInFlightF$FULL_N),
					     .EMPTY_N(metaReqInFlightF$EMPTY_N));

  // submodule splaF
  FIFO2 #(.width(32'd3), .guarded(32'd1)) splaF(.RST(wciS0_MReset_n),
						.CLK(wciS0_Clk),
						.D_IN(splaF$D_IN),
						.ENQ(splaF$ENQ),
						.DEQ(splaF$DEQ),
						.CLR(splaF$CLR),
						.D_OUT(splaF$D_OUT),
						.FULL_N(splaF$FULL_N),
						.EMPTY_N(splaF$EMPTY_N));

  // submodule wci_wslv_reqF
  SizedFIFO #(.p1width(32'd72),
	      .p2depth(32'd3),
	      .p3cntr_width(32'd1),
	      .guarded(32'd1)) wci_wslv_reqF(.RST(wciS0_MReset_n),
					     .CLK(wciS0_Clk),
					     .D_IN(wci_wslv_reqF$D_IN),
					     .ENQ(wci_wslv_reqF$ENQ),
					     .DEQ(wci_wslv_reqF$DEQ),
					     .CLR(wci_wslv_reqF$CLR),
					     .D_OUT(wci_wslv_reqF$D_OUT),
					     .FULL_N(),
					     .EMPTY_N(wci_wslv_reqF$EMPTY_N));

  // rule RL_wci_wslv_ctl_op_start
  assign WILL_FIRE_RL_wci_wslv_ctl_op_start =
	     wci_wslv_reqF$EMPTY_N && wci_wslv_wci_ctrl_pw$whas &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wci_ctrl_IsO
  assign WILL_FIRE_RL_wci_ctrl_IsO =
	     wci_wslv_wci_ctrl_pw$whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd1 &&
	     wci_wslv_reqF$D_OUT[36:34] == 3'd1 ;

  // rule RL_wci_ctrl_OrE
  assign WILL_FIRE_RL_wci_ctrl_OrE =
	     wci_wslv_wci_ctrl_pw$whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd2 &&
	     wci_wslv_reqF$D_OUT[36:34] == 3'd3 ;

  // rule RL_wci_cfrd
  assign CAN_FIRE_RL_wci_cfrd =
	     wci_wslv_reqF$EMPTY_N &&
	     IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1140 &&
	     (wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
	      wci_wslv_reqF$D_OUT[63:52] == 12'h400 ||
	      wci_wslv_respF_c_r != 2'd2) &&
	     wci_wslv_wci_cfrd_pw$whas ;
  assign WILL_FIRE_RL_wci_cfrd =
	     CAN_FIRE_RL_wci_cfrd && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wsiM_reqFifo_deq
  assign WILL_FIRE_RL_wsiM_reqFifo_deq =
	     wsiM_reqFifo_c_r != 2'd0 && !wsiM_sThreadBusy_d ;

  // rule RL_dataBram_serverAdapterA_stageReadResponseAlways
  assign WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways =
	     (dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
	     bytesRemain != 32'd0 ;

  // rule RL_wsiM_reqFifo_incCtr
  assign WILL_FIRE_RL_wsiM_reqFifo_incCtr =
	     ((wsiM_reqFifo_c_r == 2'd0) ?
		wsiM_reqFifo_enqueueing$whas :
		wsiM_reqFifo_c_r != 2'd1 || wsiM_reqFifo_enqueueing$whas) &&
	     wsiM_reqFifo_enqueueing$whas &&
	     !WILL_FIRE_RL_wsiM_reqFifo_deq ;

  // rule RL_wsiM_reqFifo_decCtr
  assign WILL_FIRE_RL_wsiM_reqFifo_decCtr =
	     WILL_FIRE_RL_wsiM_reqFifo_deq && !wsiM_reqFifo_enqueueing$whas ;

  // rule RL_wsiM_reqFifo_both
  assign WILL_FIRE_RL_wsiM_reqFifo_both =
	     ((wsiM_reqFifo_c_r == 2'd1) ?
		wsiM_reqFifo_enqueueing$whas :
		wsiM_reqFifo_c_r != 2'd2 || wsiM_reqFifo_enqueueing$whas) &&
	     WILL_FIRE_RL_wsiM_reqFifo_deq &&
	     wsiM_reqFifo_enqueueing$whas ;

  // rule RL_dataBram_serverAdapterA_outData_enqAndDeq
  assign WILL_FIRE_RL_dataBram_serverAdapterA_outData_enqAndDeq =
	     dataBram_serverAdapterA_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterA_outDataCore$FULL_N &&
	     dataBram_serverAdapterA_outData_deqCalled$whas &&
	     dataBram_serverAdapterA_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterA_stageReadResponseAlways
  assign WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways =
	     (metaBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
	     (metaBram_serverAdapterA_1_cnt ^ 3'h4) < 3'd7 &&
	     (metaBram_serverAdapterA_2_cnt ^ 3'h4) < 3'd7 &&
	     (metaBram_serverAdapterA_3_cnt ^ 3'h4) < 3'd7 &&
	     metaReqInFlightF$FULL_N &&
	     loopReqInFlightF$FULL_N &&
	     wci_wslv_cState == 3'd2 &&
	     controlReg[0] &&
	     mesgRemain != 32'd0 ;

  // rule RL_wci_cfwr
  assign CAN_FIRE_RL_wci_cfwr =
	     wci_wslv_respF_c_r != 2'd2 && wci_wslv_reqF$EMPTY_N &&
	     ((wci_wslv_reqF$D_OUT[63:52] == 12'h800) ?
		dataBram_serverAdapterB_cnt_33_SLT_3___d1324 :
		wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
		IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1422) &&
	     wci_wslv_wci_cfwr_pw$whas ;
  assign WILL_FIRE_RL_wci_cfwr =
	     CAN_FIRE_RL_wci_cfwr && !WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;

  // rule RL_wci_wslv_ctl_op_complete
  assign WILL_FIRE_RL_wci_wslv_ctl_op_complete =
	     wci_wslv_respF_c_r != 2'd2 && wci_wslv_ctlOpActive &&
	     wci_wslv_ctlAckReg ;

  // rule RL_metaBram_serverAdapterA_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterA_outData_enqAndDeq =
	     metaBram_serverAdapterA_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_outDataCore$FULL_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterA_1_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterA_1_outData_enqAndDeq =
	     metaBram_serverAdapterA_1_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_1_outDataCore$FULL_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_1_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterA_2_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterA_2_outData_enqAndDeq =
	     metaBram_serverAdapterA_2_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_2_outDataCore$FULL_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_2_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterA_3_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterA_3_outData_enqAndDeq =
	     metaBram_serverAdapterA_3_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_3_outDataCore$FULL_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_3_outData_enqData$whas ;

  // rule RL_wci_wslv_respF_incCtr
  assign WILL_FIRE_RL_wci_wslv_respF_incCtr =
	     ((wci_wslv_respF_c_r == 2'd0) ?
		wci_wslv_respF_x_wire$whas :
		wci_wslv_respF_c_r != 2'd1 || wci_wslv_respF_x_wire$whas) &&
	     wci_wslv_respF_enqueueing$whas &&
	     !(wci_wslv_respF_c_r != 2'd0) ;

  // rule RL_wci_wslv_respF_decCtr
  assign WILL_FIRE_RL_wci_wslv_respF_decCtr =
	     wci_wslv_respF_c_r != 2'd0 && !wci_wslv_respF_enqueueing$whas ;

  // rule RL_wci_wslv_respF_both
  assign WILL_FIRE_RL_wci_wslv_respF_both =
	     ((wci_wslv_respF_c_r == 2'd1) ?
		wci_wslv_respF_x_wire$whas :
		wci_wslv_respF_c_r != 2'd2 || wci_wslv_respF_x_wire$whas) &&
	     wci_wslv_respF_c_r != 2'd0 &&
	     wci_wslv_respF_enqueueing$whas ;

  // rule RL_dataBram_serverAdapterB_outData_enqAndDeq
  assign WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq =
	     dataBram_serverAdapterB_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterB_outDataCore$FULL_N &&
	     dataBram_serverAdapterB_outData_deqCalled$whas &&
	     dataBram_serverAdapterB_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterB_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq =
	     metaBram_serverAdapterB_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_outDataCore$FULL_N &&
	     metaBram_serverAdapterB_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterB_1_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq =
	     metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_1_outDataCore$FULL_N &&
	     metaBram_serverAdapterB_1_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_1_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterB_2_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq =
	     metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_2_outDataCore$FULL_N &&
	     metaBram_serverAdapterB_2_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_2_outData_enqData$whas ;

  // rule RL_metaBram_serverAdapterB_3_outData_enqAndDeq
  assign WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq =
	     metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_3_outDataCore$FULL_N &&
	     metaBram_serverAdapterB_3_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_3_outData_enqData$whas ;

  // inputs to muxes for submodule ports
  assign MUX_controlReg$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h0 ;
  assign MUX_controlReg$write_1__SEL_2 =
	     wci_wslv_wci_ctrl_pw$whas &&
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     wci_wslv_cState == 3'd0 &&
	     wci_wslv_reqF$D_OUT[36:34] == 3'd0 ;
  assign MUX_dataBram_memory$b_put_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ;
  assign MUX_dataBram_memory$b_put_1__SEL_2 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ;
  assign MUX_dataCount$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h0C ;
  assign MUX_mesgCount$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h08 ;
  assign MUX_mesgCount$write_1__SEL_2 =
	     wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1 ;
  assign MUX_mesgRemain$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h10 ;
  assign MUX_metaBram_memory$b_put_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd0 ;
  assign MUX_metaBram_memory$b_put_1__SEL_2 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd0 ;
  assign MUX_metaBram_memory_1$b_put_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd1 ;
  assign MUX_metaBram_memory_1$b_put_1__SEL_2 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd1 ;
  assign MUX_metaBram_memory_2$b_put_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd2 ;
  assign MUX_metaBram_memory_2$b_put_1__SEL_2 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd2 ;
  assign MUX_metaBram_memory_3$b_put_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd3 ;
  assign MUX_metaBram_memory_3$b_put_1__SEL_2 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd3 ;
  assign MUX_metaPtr_modulus$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h04 ;
  assign MUX_splitReadInFlight$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd &&
	     (wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
	      wci_wslv_reqF$D_OUT[63:52] == 12'h400) ;
  assign MUX_unrollCnt$write_1__SEL_1 =
	     metaReqInFlightF_i_notEmpty__59_AND_metaBram_s_ETC___d875 &&
	     wci_wslv_cState == 3'd2 &&
	     mesgRemain != 32'd0 ;
  assign MUX_wci_wslv_illegalEdge$write_1__SEL_1 =
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState != 3'd0 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd1 && wci_wslv_cState != 3'd1 &&
	      wci_wslv_cState != 3'd3 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState != 3'd2 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd3 && wci_wslv_cState != 3'd3 &&
	      wci_wslv_cState != 3'd2 &&
	      wci_wslv_cState != 3'd1 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd4 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd5 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd6 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd7) ;
  assign MUX_wci_wslv_respF_q_0$write_1__SEL_2 =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_c_r == 2'd0 ;
  assign MUX_wci_wslv_respF_q_1$write_1__SEL_2 =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_c_r == 2'd1 ;
  assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
	     wci_wslv_reqF$D_OUT[63:52] != 12'h400 ;
  assign MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 =
	     wci_wslv_respF_c_r != 2'd2 &&
	     splaF_i_notEmpty__011_AND_IF_splaF_first__012__ETC___d1044 &&
	     !wci_wslv_wci_cfwr_pw$whas &&
	     splitReadInFlight &&
	     !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
  assign MUX_wsiM_reqFifo_q_0$write_1__SEL_2 =
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ;
  assign MUX_wsiM_reqFifo_q_1$write_1__SEL_2 =
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ;
  assign MUX_bytesRemain$write_1__VAL_2 =
	     (bytesRemain < 32'd4) ? 32'd0 : bytesRemain - 32'd4 ;
  assign MUX_dataCount$write_1__VAL_2 = dataCount + 32'd1 ;
  assign MUX_mesgCount$write_1__VAL_2 = mesgCount + 32'd1 ;
  assign MUX_mesgRemain$write_1__VAL_2 = mesgRemain - 32'd1 ;
  assign MUX_metaPtr_modulus$write_1__VAL_1 =
	     wci_wslv_reqF$D_OUT[15:0] - 16'd1 ;
  assign MUX_metaPtr_value$write_1__VAL_3 =
	     (metaPtr_value == metaPtr_modulus) ?
	       16'd0 :
	       metaPtr_value + 16'd1 ;
  assign MUX_unrollCnt$write_1__VAL_1 =
	     (v__h24797 == 32'd0) ? 16'd1 : b__h25414[15:0] ;
  assign MUX_unrollCnt$write_1__VAL_2 = unrollCnt - 16'd1 ;
  assign MUX_wci_wslv_illegalEdge$write_1__VAL_1 =
	     wci_wslv_reqF$D_OUT[36:34] != 3'd4 &&
	     wci_wslv_reqF$D_OUT[36:34] != 3'd5 &&
	     wci_wslv_reqF$D_OUT[36:34] != 3'd6 ;
  assign MUX_wci_wslv_respF_c_r$write_1__VAL_1 = wci_wslv_respF_c_r + 2'd1 ;
  assign MUX_wci_wslv_respF_c_r$write_1__VAL_2 = wci_wslv_respF_c_r - 2'd1 ;
  assign MUX_wci_wslv_respF_q_0$write_1__VAL_1 =
	     (wci_wslv_respF_c_r == 2'd1) ?
	       MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
	       wci_wslv_respF_q_1 ;
  always@(MUX_wci_wslv_respF_x_wire$wset_1__SEL_1 or
	  MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 or
	  WILL_FIRE_RL_wci_wslv_ctl_op_complete or
	  MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 or
	  MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 or
	  MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 or WILL_FIRE_RL_wci_cfwr)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_wci_wslv_respF_x_wire$wset_1__SEL_1:
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
	      MUX_wci_wslv_respF_x_wire$wset_1__VAL_1;
      WILL_FIRE_RL_wci_wslv_ctl_op_complete:
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
	      MUX_wci_wslv_respF_x_wire$wset_1__VAL_2;
      MUX_wci_wslv_respF_x_wire$wset_1__SEL_3:
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
	      MUX_wci_wslv_respF_x_wire$wset_1__VAL_3;
      WILL_FIRE_RL_wci_cfwr:
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 = 34'h1C0DE4201;
      default: MUX_wci_wslv_respF_q_0$write_1__VAL_2 =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign MUX_wci_wslv_respF_q_1$write_1__VAL_1 =
	     (wci_wslv_respF_c_r == 2'd2) ?
	       MUX_wci_wslv_respF_q_0$write_1__VAL_2 :
	       34'h0AAAAAAAA ;
  assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_1 = { 2'd1, g_data__h33410 } ;
  assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_2 =
	     wci_wslv_illegalEdge ? 34'h3C0DE4202 : 34'h1C0DE4201 ;
  assign MUX_wci_wslv_respF_x_wire$wset_1__VAL_3 = { 2'd1, v__h29897 } ;
  assign MUX_wsiM_reqFifo_c_r$write_1__VAL_1 = wsiM_reqFifo_c_r + 2'd1 ;
  assign MUX_wsiM_reqFifo_c_r$write_1__VAL_2 = wsiM_reqFifo_c_r - 2'd1 ;
  assign MUX_wsiM_reqFifo_q_0$write_1__VAL_1 =
	     (wsiM_reqFifo_c_r == 2'd1) ?
	       MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
	       wsiM_reqFifo_q_1 ;
  assign MUX_wsiM_reqFifo_q_0$write_1__VAL_2 =
	     { 3'd1,
	       unrollCnt == 16'd1,
	       1'd0,
	       x_burstLength__h26222,
	       dataBram_serverAdapterA_outData_outData$wget,
	       x_byteEn__h26224,
	       thisOpcode[7:0] } ;
  assign MUX_wsiM_reqFifo_q_1$write_1__VAL_1 =
	     (wsiM_reqFifo_c_r == 2'd2) ?
	       MUX_wsiM_reqFifo_q_0$write_1__VAL_2 :
	       61'h00000AAAAAAAAA00 ;

  // inlined wires
  assign wci_wslv_wciReq$wget =
	     { wciS0_MCmd,
	       wciS0_MAddrSpace,
	       wciS0_MByteEn,
	       wciS0_MAddr,
	       wciS0_MData } ;
  assign wci_wslv_wciReq$whas = 1'd1 ;
  assign wci_wslv_respF_x_wire$wget = MUX_wci_wslv_respF_q_0$write_1__VAL_2 ;
  assign wci_wslv_respF_x_wire$whas =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
	     wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ||
	     WILL_FIRE_RL_wci_cfwr ;
  assign wci_wslv_wEdge$wget = wci_wslv_reqF$D_OUT[36:34] ;
  assign wci_wslv_wEdge$whas = WILL_FIRE_RL_wci_wslv_ctl_op_start ;
  assign wci_wslv_sFlagReg_1$wget = 1'b0 ;
  assign wci_wslv_sFlagReg_1$whas = 1'b0 ;
  assign wci_wslv_ctlAckReg_1$wget = 1'd1 ;
  assign wci_wslv_ctlAckReg_1$whas =
	     WILL_FIRE_RL_wci_ctrl_OrE || WILL_FIRE_RL_wci_ctrl_IsO ||
	     MUX_controlReg$write_1__SEL_2 ;
  assign wci_wci_Es_mCmd_w$wget = wciS0_MCmd ;
  assign wci_wci_Es_mCmd_w$whas = 1'd1 ;
  assign wci_wci_Es_mAddrSpace_w$wget = wciS0_MAddrSpace ;
  assign wci_wci_Es_mAddrSpace_w$whas = 1'd1 ;
  assign wci_wci_Es_mByteEn_w$wget = wciS0_MByteEn ;
  assign wci_wci_Es_mByteEn_w$whas = 1'd1 ;
  assign wci_wci_Es_mAddr_w$wget = wciS0_MAddr ;
  assign wci_wci_Es_mAddr_w$whas = 1'd1 ;
  assign wci_wci_Es_mData_w$wget = wciS0_MData ;
  assign wci_wci_Es_mData_w$whas = 1'd1 ;
  assign wsiM_reqFifo_x_wire$wget = MUX_wsiM_reqFifo_q_0$write_1__VAL_2 ;
  assign wsiM_reqFifo_x_wire$whas = wsiM_reqFifo_enqueueing$whas ;
  assign wsiM_operateD_1$wget = 1'd1 ;
  assign wsiM_operateD_1$whas = wci_wslv_cState == 3'd2 ;
  assign wsiM_peerIsReady_1$wget = 1'd1 ;
  assign wsiM_peerIsReady_1$whas = wsiM0_SReset_n ;
  assign statusReg_w$wget = 32'hA0240A0A ;
  assign statusReg_w$whas = 1'd1 ;
  assign dataBram_serverAdapterA_outData_enqData$wget = dataBram_memory$DOA ;
  assign dataBram_serverAdapterA_outData_enqData$whas =
	     (!dataBram_serverAdapterA_s1[0] ||
	      dataBram_serverAdapterA_outDataCore$FULL_N) &&
	     dataBram_serverAdapterA_s1[1] &&
	     dataBram_serverAdapterA_s1[0] ;
  assign dataBram_serverAdapterA_outData_outData$wget =
	     dataBram_serverAdapterA_outDataCore$EMPTY_N ?
	       dataBram_serverAdapterA_outDataCore$D_OUT :
	       dataBram_memory$DOA ;
  assign dataBram_serverAdapterA_outData_outData$whas =
	     dataBram_serverAdapterA_outDataCore$EMPTY_N ||
	     !dataBram_serverAdapterA_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterA_outData_enqData$whas ;
  assign dataBram_serverAdapterA_cnt_1$wget = 3'd1 ;
  assign dataBram_serverAdapterA_cnt_1$whas =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ;
  assign dataBram_serverAdapterA_cnt_2$wget = 3'd7 ;
  assign dataBram_serverAdapterA_cnt_2$whas =
	     dataBram_serverAdapterA_outData_deqCalled$whas ;
  assign dataBram_serverAdapterA_cnt_3$wget = 3'h0 ;
  assign dataBram_serverAdapterA_cnt_3$whas = 1'b0 ;
  assign dataBram_serverAdapterA_writeWithResp$wget = 2'd0 ;
  assign dataBram_serverAdapterA_writeWithResp$whas =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ;
  assign dataBram_serverAdapterA_s1_1$wget = 2'd3 ;
  assign dataBram_serverAdapterA_s1_1$whas =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ;
  assign dataBram_serverAdapterB_outData_enqData$wget = dataBram_memory$DOB ;
  assign dataBram_serverAdapterB_outData_enqData$whas =
	     (!dataBram_serverAdapterB_s1[0] ||
	      dataBram_serverAdapterB_outDataCore$FULL_N) &&
	     dataBram_serverAdapterB_s1[1] &&
	     dataBram_serverAdapterB_s1[0] ;
  assign dataBram_serverAdapterB_outData_outData$wget = y_avValue__h30523 ;
  assign dataBram_serverAdapterB_outData_outData$whas =
	     dataBram_serverAdapterB_outDataCore$EMPTY_N ||
	     !dataBram_serverAdapterB_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterB_outData_enqData$whas ;
  assign dataBram_serverAdapterB_cnt_1$wget = 3'd1 ;
  assign dataBram_serverAdapterB_cnt_1$whas =
	     (MUX_dataBram_memory$b_put_1__SEL_1 ||
	      MUX_dataBram_memory$b_put_1__SEL_2) &&
	     (!ab__h11724[1] || ab__h11724[0]) ;
  assign dataBram_serverAdapterB_cnt_2$wget = 3'd7 ;
  assign dataBram_serverAdapterB_cnt_2$whas =
	     dataBram_serverAdapterB_outData_deqCalled$whas ;
  assign dataBram_serverAdapterB_cnt_3$wget = 3'h0 ;
  assign dataBram_serverAdapterB_cnt_3$whas = 1'b0 ;
  assign dataBram_serverAdapterB_writeWithResp$wget = ab__h11724 ;
  assign dataBram_serverAdapterB_writeWithResp$whas =
	     MUX_dataBram_memory$b_put_1__SEL_1 ||
	     MUX_dataBram_memory$b_put_1__SEL_2 ;
  assign dataBram_serverAdapterB_s1_1$wget =
	     { 1'd1, !ab__h11724[1] || ab__h11724[0] } ;
  assign dataBram_serverAdapterB_s1_1$whas =
	     dataBram_serverAdapterB_writeWithResp$whas ;
  assign metaBram_serverAdapterA_outData_enqData$wget = metaBram_memory$DOA ;
  assign metaBram_serverAdapterA_outData_enqData$whas =
	     (!metaBram_serverAdapterA_s1[0] ||
	      metaBram_serverAdapterA_outDataCore$FULL_N) &&
	     metaBram_serverAdapterA_s1[1] &&
	     metaBram_serverAdapterA_s1[0] ;
  assign metaBram_serverAdapterA_outData_outData$wget = v__h24797 ;
  assign metaBram_serverAdapterA_outData_outData$whas =
	     metaBram_serverAdapterA_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterA_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_outData_enqData$whas ;
  assign metaBram_serverAdapterA_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterA_cnt_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterA_cnt_2$whas = MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterA_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterA_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterA_writeWithResp$wget = 2'd0 ;
  assign metaBram_serverAdapterA_writeWithResp$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_s1_1$wget = 2'd3 ;
  assign metaBram_serverAdapterA_s1_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterB_outData_enqData$wget = metaBram_memory$DOB ;
  assign metaBram_serverAdapterB_outData_enqData$whas =
	     (!metaBram_serverAdapterB_s1[0] ||
	      metaBram_serverAdapterB_outDataCore$FULL_N) &&
	     metaBram_serverAdapterB_s1[1] &&
	     metaBram_serverAdapterB_s1[0] ;
  assign metaBram_serverAdapterB_outData_outData$wget = y_avValue__h30567 ;
  assign metaBram_serverAdapterB_outData_outData$whas =
	     metaBram_serverAdapterB_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterB_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_outData_enqData$whas ;
  assign metaBram_serverAdapterB_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterB_cnt_1$whas =
	     (MUX_metaBram_memory$b_put_1__SEL_1 ||
	      MUX_metaBram_memory$b_put_1__SEL_2) &&
	     (!ab__h14842[1] || ab__h14842[0]) ;
  assign metaBram_serverAdapterB_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterB_cnt_2$whas =
	     metaBram_serverAdapterB_outData_deqCalled$whas ;
  assign metaBram_serverAdapterB_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterB_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterB_writeWithResp$wget = ab__h14842 ;
  assign metaBram_serverAdapterB_writeWithResp$whas =
	     MUX_metaBram_memory$b_put_1__SEL_1 ||
	     MUX_metaBram_memory$b_put_1__SEL_2 ;
  assign metaBram_serverAdapterB_s1_1$wget =
	     { 1'd1, !ab__h14842[1] || ab__h14842[0] } ;
  assign metaBram_serverAdapterB_s1_1$whas =
	     metaBram_serverAdapterB_writeWithResp$whas ;
  assign metaBram_serverAdapterA_1_outData_enqData$wget =
	     metaBram_memory_1$DOA ;
  assign metaBram_serverAdapterA_1_outData_enqData$whas =
	     (!metaBram_serverAdapterA_1_s1[0] ||
	      metaBram_serverAdapterA_1_outDataCore$FULL_N) &&
	     metaBram_serverAdapterA_1_s1[1] &&
	     metaBram_serverAdapterA_1_s1[0] ;
  assign metaBram_serverAdapterA_1_outData_outData$wget =
	     metaBram_serverAdapterA_1_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterA_1_outDataCore$D_OUT :
	       metaBram_memory_1$DOA ;
  assign metaBram_serverAdapterA_1_outData_outData$whas =
	     metaBram_serverAdapterA_1_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterA_1_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_1_outData_enqData$whas ;
  assign metaBram_serverAdapterA_1_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterA_1_cnt_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_1_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterA_1_cnt_2$whas = MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterA_1_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterA_1_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterA_1_writeWithResp$wget = 2'd0 ;
  assign metaBram_serverAdapterA_1_writeWithResp$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_1_s1_1$wget = 2'd3 ;
  assign metaBram_serverAdapterA_1_s1_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterB_1_outData_enqData$wget =
	     metaBram_memory_1$DOB ;
  assign metaBram_serverAdapterB_1_outData_enqData$whas =
	     (!metaBram_serverAdapterB_1_s1[0] ||
	      metaBram_serverAdapterB_1_outDataCore$FULL_N) &&
	     metaBram_serverAdapterB_1_s1[1] &&
	     metaBram_serverAdapterB_1_s1[0] ;
  assign metaBram_serverAdapterB_1_outData_outData$wget = y_avValue__h30607 ;
  assign metaBram_serverAdapterB_1_outData_outData$whas =
	     metaBram_serverAdapterB_1_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_1_outData_enqData$whas ;
  assign metaBram_serverAdapterB_1_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterB_1_cnt_1$whas =
	     (MUX_metaBram_memory_1$b_put_1__SEL_1 ||
	      MUX_metaBram_memory_1$b_put_1__SEL_2) &&
	     (!ab__h17788[1] || ab__h17788[0]) ;
  assign metaBram_serverAdapterB_1_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterB_1_cnt_2$whas =
	     metaBram_serverAdapterB_1_outData_deqCalled$whas ;
  assign metaBram_serverAdapterB_1_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterB_1_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterB_1_writeWithResp$wget = ab__h17788 ;
  assign metaBram_serverAdapterB_1_writeWithResp$whas =
	     MUX_metaBram_memory_1$b_put_1__SEL_1 ||
	     MUX_metaBram_memory_1$b_put_1__SEL_2 ;
  assign metaBram_serverAdapterB_1_s1_1$wget =
	     { 1'd1, !ab__h17788[1] || ab__h17788[0] } ;
  assign metaBram_serverAdapterB_1_s1_1$whas =
	     metaBram_serverAdapterB_1_writeWithResp$whas ;
  assign metaBram_serverAdapterA_2_outData_enqData$wget =
	     metaBram_memory_2$DOA ;
  assign metaBram_serverAdapterA_2_outData_enqData$whas =
	     (!metaBram_serverAdapterA_2_s1[0] ||
	      metaBram_serverAdapterA_2_outDataCore$FULL_N) &&
	     metaBram_serverAdapterA_2_s1[1] &&
	     metaBram_serverAdapterA_2_s1[0] ;
  assign metaBram_serverAdapterA_2_outData_outData$wget =
	     metaBram_serverAdapterA_2_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterA_2_outDataCore$D_OUT :
	       metaBram_memory_2$DOA ;
  assign metaBram_serverAdapterA_2_outData_outData$whas =
	     metaBram_serverAdapterA_2_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterA_2_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_2_outData_enqData$whas ;
  assign metaBram_serverAdapterA_2_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterA_2_cnt_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_2_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterA_2_cnt_2$whas = MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterA_2_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterA_2_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterA_2_writeWithResp$wget = 2'd0 ;
  assign metaBram_serverAdapterA_2_writeWithResp$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_2_s1_1$wget = 2'd3 ;
  assign metaBram_serverAdapterA_2_s1_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterB_2_outData_enqData$wget =
	     metaBram_memory_2$DOB ;
  assign metaBram_serverAdapterB_2_outData_enqData$whas =
	     (!metaBram_serverAdapterB_2_s1[0] ||
	      metaBram_serverAdapterB_2_outDataCore$FULL_N) &&
	     metaBram_serverAdapterB_2_s1[1] &&
	     metaBram_serverAdapterB_2_s1[0] ;
  assign metaBram_serverAdapterB_2_outData_outData$wget = y_avValue__h30647 ;
  assign metaBram_serverAdapterB_2_outData_outData$whas =
	     metaBram_serverAdapterB_2_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_2_outData_enqData$whas ;
  assign metaBram_serverAdapterB_2_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterB_2_cnt_1$whas =
	     (MUX_metaBram_memory_2$b_put_1__SEL_1 ||
	      MUX_metaBram_memory_2$b_put_1__SEL_2) &&
	     (!ab__h20734[1] || ab__h20734[0]) ;
  assign metaBram_serverAdapterB_2_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterB_2_cnt_2$whas =
	     metaBram_serverAdapterB_2_outData_deqCalled$whas ;
  assign metaBram_serverAdapterB_2_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterB_2_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterB_2_writeWithResp$wget = ab__h20734 ;
  assign metaBram_serverAdapterB_2_writeWithResp$whas =
	     MUX_metaBram_memory_2$b_put_1__SEL_1 ||
	     MUX_metaBram_memory_2$b_put_1__SEL_2 ;
  assign metaBram_serverAdapterB_2_s1_1$wget =
	     { 1'd1, !ab__h20734[1] || ab__h20734[0] } ;
  assign metaBram_serverAdapterB_2_s1_1$whas =
	     metaBram_serverAdapterB_2_writeWithResp$whas ;
  assign metaBram_serverAdapterA_3_outData_enqData$wget =
	     metaBram_memory_3$DOA ;
  assign metaBram_serverAdapterA_3_outData_enqData$whas =
	     (!metaBram_serverAdapterA_3_s1[0] ||
	      metaBram_serverAdapterA_3_outDataCore$FULL_N) &&
	     metaBram_serverAdapterA_3_s1[1] &&
	     metaBram_serverAdapterA_3_s1[0] ;
  assign metaBram_serverAdapterA_3_outData_outData$wget =
	     metaBram_serverAdapterA_3_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterA_3_outDataCore$D_OUT :
	       metaBram_memory_3$DOA ;
  assign metaBram_serverAdapterA_3_outData_outData$whas =
	     metaBram_serverAdapterA_3_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterA_3_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterA_3_outData_enqData$whas ;
  assign metaBram_serverAdapterA_3_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterA_3_cnt_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_3_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterA_3_cnt_2$whas = MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterA_3_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterA_3_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterA_3_writeWithResp$wget = 2'd0 ;
  assign metaBram_serverAdapterA_3_writeWithResp$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterA_3_s1_1$wget = 2'd3 ;
  assign metaBram_serverAdapterA_3_s1_1$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_serverAdapterB_3_outData_enqData$wget =
	     metaBram_memory_3$DOB ;
  assign metaBram_serverAdapterB_3_outData_enqData$whas =
	     (!metaBram_serverAdapterB_3_s1[0] ||
	      metaBram_serverAdapterB_3_outDataCore$FULL_N) &&
	     metaBram_serverAdapterB_3_s1[1] &&
	     metaBram_serverAdapterB_3_s1[0] ;
  assign metaBram_serverAdapterB_3_outData_outData$wget = y_avValue__h30687 ;
  assign metaBram_serverAdapterB_3_outData_outData$whas =
	     metaBram_serverAdapterB_3_outDataCore$EMPTY_N ||
	     !metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_3_outData_enqData$whas ;
  assign metaBram_serverAdapterB_3_cnt_1$wget = 3'd1 ;
  assign metaBram_serverAdapterB_3_cnt_1$whas =
	     (MUX_metaBram_memory_3$b_put_1__SEL_1 ||
	      MUX_metaBram_memory_3$b_put_1__SEL_2) &&
	     (!ab__h23680[1] || ab__h23680[0]) ;
  assign metaBram_serverAdapterB_3_cnt_2$wget = 3'd7 ;
  assign metaBram_serverAdapterB_3_cnt_2$whas =
	     metaBram_serverAdapterB_3_outData_deqCalled$whas ;
  assign metaBram_serverAdapterB_3_cnt_3$wget = 3'h0 ;
  assign metaBram_serverAdapterB_3_cnt_3$whas = 1'b0 ;
  assign metaBram_serverAdapterB_3_writeWithResp$wget = ab__h23680 ;
  assign metaBram_serverAdapterB_3_writeWithResp$whas =
	     MUX_metaBram_memory_3$b_put_1__SEL_1 ||
	     MUX_metaBram_memory_3$b_put_1__SEL_2 ;
  assign metaBram_serverAdapterB_3_s1_1$wget =
	     { 1'd1, !ab__h23680[1] || ab__h23680[0] } ;
  assign metaBram_serverAdapterB_3_s1_1$whas =
	     metaBram_serverAdapterB_3_writeWithResp$whas ;
  assign wci_wslv_reqF_r_enq$whas = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
  assign wci_wslv_reqF_r_deq$whas =
	     WILL_FIRE_RL_wci_cfrd || WILL_FIRE_RL_wci_cfwr ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_start ;
  assign wci_wslv_reqF_r_clr$whas = 1'b0 ;
  assign wci_wslv_respF_enqueueing$whas =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] != 12'h800 &&
	     wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ||
	     WILL_FIRE_RL_wci_cfwr ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
  assign wci_wslv_respF_dequeueing$whas = wci_wslv_respF_c_r != 2'd0 ;
  assign wci_wslv_sThreadBusy_pw$whas = 1'b0 ;
  assign wci_wslv_wci_cfwr_pw$whas =
	     wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
	     wci_wslv_reqF$D_OUT[71:69] == 3'd1 ;
  assign wci_wslv_wci_cfrd_pw$whas =
	     wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[68] &&
	     wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
  assign wci_wslv_wci_ctrl_pw$whas =
	     wci_wslv_reqF$EMPTY_N && !wci_wslv_reqF$D_OUT[68] &&
	     wci_wslv_reqF$D_OUT[71:69] == 3'd2 ;
  assign wsiM_reqFifo_enqueueing$whas =
	     wsiM_reqFifo_c_r != 2'd2 &&
	     doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923 &&
	     wci_wslv_cState == 3'd2 ;
  assign wsiM_reqFifo_dequeueing$whas = WILL_FIRE_RL_wsiM_reqFifo_deq ;
  assign wsiM_sThreadBusy_pw$whas = wsiM0_SThreadBusy ;
  assign metaPtr_incAction$whas =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaPtr_decAction$whas = 1'b0 ;
  assign dataBram_serverAdapterA_outData_deqCalled$whas =
	     wsiM_reqFifo_enqueueing$whas && !doZLM ;
  assign dataBram_serverAdapterB_outData_deqCalled$whas =
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && splaF$D_OUT[2] &&
	     splaF$D_OUT[1:0] == 2'd0 ;
  assign metaBram_serverAdapterA_outData_deqCalled$whas =
	     MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterB_outData_deqCalled$whas =
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] &&
	     splaF$D_OUT[1:0] == 2'd0 ;
  assign metaBram_serverAdapterA_1_outData_deqCalled$whas =
	     MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterB_1_outData_deqCalled$whas =
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] &&
	     splaF$D_OUT[1:0] == 2'd1 ;
  assign metaBram_serverAdapterA_2_outData_deqCalled$whas =
	     MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterB_2_outData_deqCalled$whas =
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] &&
	     splaF$D_OUT[1:0] == 2'd2 ;
  assign metaBram_serverAdapterA_3_outData_deqCalled$whas =
	     MUX_unrollCnt$write_1__SEL_1 ;
  assign metaBram_serverAdapterB_3_outData_deqCalled$whas =
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 && !splaF$D_OUT[2] &&
	     splaF$D_OUT[1:0] == 2'd3 ;
  assign wsiM_extStatusW$wget =
	     { wsiM_pMesgCount, wsiM_iMesgCount, wsiM_tBusyCount } ;
  assign metaPtr_modulus_bw$wget = metaPtr_modulus ;

  // register bytesRemain
  assign bytesRemain$D_IN =
	     MUX_unrollCnt$write_1__SEL_1 ?
	       v__h24797 :
	       MUX_bytesRemain$write_1__VAL_2 ;
  assign bytesRemain$EN =
	     MUX_unrollCnt$write_1__SEL_1 ||
	     (dataBram_serverAdapterA_cnt ^ 3'h4) < 3'd7 &&
	     bytesRemain != 32'd0 ;

  // register controlReg
  assign controlReg$D_IN =
	     MUX_controlReg$write_1__SEL_1 ?
	       wci_wslv_reqF$D_OUT[31:0] :
	       32'd0 ;
  assign controlReg$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h0 ||
	     MUX_controlReg$write_1__SEL_2 ;

  // register dataBram_serverAdapterA_cnt
  assign dataBram_serverAdapterA_cnt$D_IN =
	     dataBram_serverAdapterA_cnt_74_PLUS_IF_dataBra_ETC___d280 ;
  assign dataBram_serverAdapterA_cnt$EN =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ||
	     dataBram_serverAdapterA_outData_deqCalled$whas ;

  // register dataBram_serverAdapterA_s1
  assign dataBram_serverAdapterA_s1$D_IN =
	     { WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways,
	       1'b1 } ;
  assign dataBram_serverAdapterA_s1$EN = 1'd1 ;

  // register dataBram_serverAdapterB_cnt
  assign dataBram_serverAdapterB_cnt$D_IN =
	     dataBram_serverAdapterB_cnt_33_PLUS_IF_dataBra_ETC___d339 ;
  assign dataBram_serverAdapterB_cnt$EN =
	     dataBram_serverAdapterB_cnt_1$whas ||
	     dataBram_serverAdapterB_outData_deqCalled$whas ;

  // register dataBram_serverAdapterB_s1
  assign dataBram_serverAdapterB_s1$D_IN =
	     { dataBram_serverAdapterB_writeWithResp$whas &&
	       dataBram_serverAdapterB_s1_1$wget[1],
	       dataBram_serverAdapterB_s1_1$wget[0] } ;
  assign dataBram_serverAdapterB_s1$EN = 1'd1 ;

  // register dataCount
  always@(MUX_dataCount$write_1__SEL_1 or
	  wci_wslv_reqF$D_OUT or
	  wsiM_reqFifo_enqueueing$whas or
	  MUX_dataCount$write_1__VAL_2 or MUX_controlReg$write_1__SEL_2)
  case (1'b1)
    MUX_dataCount$write_1__SEL_1: dataCount$D_IN = wci_wslv_reqF$D_OUT[31:0];
    wsiM_reqFifo_enqueueing$whas:
	dataCount$D_IN = MUX_dataCount$write_1__VAL_2;
    MUX_controlReg$write_1__SEL_2: dataCount$D_IN = 32'd0;
    default: dataCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign dataCount$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h0C ||
	     wsiM_reqFifo_enqueueing$whas ||
	     MUX_controlReg$write_1__SEL_2 ;

  // register dataPtr
  assign dataPtr$D_IN =
	     (bytesRemain == 32'd4 && !controlReg[1]) ?
	       32'd0 :
	       dataPtr + 32'd1 ;
  assign dataPtr$EN =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ;

  // register doZLM
  assign doZLM$D_IN = MUX_unrollCnt$write_1__SEL_1 && v__h24797 == 32'd0 ;
  assign doZLM$EN =
	     wsiM_reqFifo_enqueueing$whas && doZLM ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register isFirst
  assign isFirst$D_IN = 1'b0 ;
  assign isFirst$EN = 1'b0 ;

  // register mesgCount
  always@(MUX_mesgCount$write_1__SEL_1 or
	  wci_wslv_reqF$D_OUT or
	  MUX_mesgCount$write_1__SEL_2 or
	  MUX_mesgCount$write_1__VAL_2 or MUX_controlReg$write_1__SEL_2)
  case (1'b1)
    MUX_mesgCount$write_1__SEL_1: mesgCount$D_IN = wci_wslv_reqF$D_OUT[31:0];
    MUX_mesgCount$write_1__SEL_2:
	mesgCount$D_IN = MUX_mesgCount$write_1__VAL_2;
    MUX_controlReg$write_1__SEL_2: mesgCount$D_IN = 32'd0;
    default: mesgCount$D_IN = 32'hAAAAAAAA /* unspecified value */ ;
  endcase
  assign mesgCount$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h08 ||
	     wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1 ||
	     MUX_controlReg$write_1__SEL_2 ;

  // register mesgLengthSoFar
  assign mesgLengthSoFar$D_IN = 14'h0 ;
  assign mesgLengthSoFar$EN = 1'b0 ;

  // register mesgRemain
  assign mesgRemain$D_IN =
	     MUX_mesgRemain$write_1__SEL_1 ?
	       wci_wslv_reqF$D_OUT[31:0] :
	       MUX_mesgRemain$write_1__VAL_2 ;
  assign mesgRemain$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h10 ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register metaBram_serverAdapterA_1_cnt
  assign metaBram_serverAdapterA_1_cnt$D_IN =
	     metaBram_serverAdapterA_1_cnt_10_PLUS_IF_metaB_ETC___d516 ;
  assign metaBram_serverAdapterA_1_cnt$EN =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register metaBram_serverAdapterA_1_s1
  assign metaBram_serverAdapterA_1_s1$D_IN =
	     { WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways,
	       1'b1 } ;
  assign metaBram_serverAdapterA_1_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterA_2_cnt
  assign metaBram_serverAdapterA_2_cnt$D_IN =
	     metaBram_serverAdapterA_2_cnt_28_PLUS_IF_metaB_ETC___d634 ;
  assign metaBram_serverAdapterA_2_cnt$EN =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register metaBram_serverAdapterA_2_s1
  assign metaBram_serverAdapterA_2_s1$D_IN =
	     { WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways,
	       1'b1 } ;
  assign metaBram_serverAdapterA_2_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterA_3_cnt
  assign metaBram_serverAdapterA_3_cnt$D_IN =
	     metaBram_serverAdapterA_3_cnt_46_PLUS_IF_metaB_ETC___d752 ;
  assign metaBram_serverAdapterA_3_cnt$EN =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register metaBram_serverAdapterA_3_s1
  assign metaBram_serverAdapterA_3_s1$D_IN =
	     { WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways,
	       1'b1 } ;
  assign metaBram_serverAdapterA_3_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterA_cnt
  assign metaBram_serverAdapterA_cnt$D_IN =
	     metaBram_serverAdapterA_cnt_92_PLUS_IF_metaBra_ETC___d398 ;
  assign metaBram_serverAdapterA_cnt$EN =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ||
	     MUX_unrollCnt$write_1__SEL_1 ;

  // register metaBram_serverAdapterA_s1
  assign metaBram_serverAdapterA_s1$D_IN =
	     { WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways,
	       1'b1 } ;
  assign metaBram_serverAdapterA_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterB_1_cnt
  assign metaBram_serverAdapterB_1_cnt$D_IN =
	     metaBram_serverAdapterB_1_cnt_69_PLUS_IF_metaB_ETC___d575 ;
  assign metaBram_serverAdapterB_1_cnt$EN =
	     metaBram_serverAdapterB_1_cnt_1$whas ||
	     metaBram_serverAdapterB_1_outData_deqCalled$whas ;

  // register metaBram_serverAdapterB_1_s1
  assign metaBram_serverAdapterB_1_s1$D_IN =
	     { metaBram_serverAdapterB_1_writeWithResp$whas &&
	       metaBram_serverAdapterB_1_s1_1$wget[1],
	       metaBram_serverAdapterB_1_s1_1$wget[0] } ;
  assign metaBram_serverAdapterB_1_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterB_2_cnt
  assign metaBram_serverAdapterB_2_cnt$D_IN =
	     metaBram_serverAdapterB_2_cnt_87_PLUS_IF_metaB_ETC___d693 ;
  assign metaBram_serverAdapterB_2_cnt$EN =
	     metaBram_serverAdapterB_2_cnt_1$whas ||
	     metaBram_serverAdapterB_2_outData_deqCalled$whas ;

  // register metaBram_serverAdapterB_2_s1
  assign metaBram_serverAdapterB_2_s1$D_IN =
	     { metaBram_serverAdapterB_2_writeWithResp$whas &&
	       metaBram_serverAdapterB_2_s1_1$wget[1],
	       metaBram_serverAdapterB_2_s1_1$wget[0] } ;
  assign metaBram_serverAdapterB_2_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterB_3_cnt
  assign metaBram_serverAdapterB_3_cnt$D_IN =
	     metaBram_serverAdapterB_3_cnt_05_PLUS_IF_metaB_ETC___d811 ;
  assign metaBram_serverAdapterB_3_cnt$EN =
	     metaBram_serverAdapterB_3_cnt_1$whas ||
	     metaBram_serverAdapterB_3_outData_deqCalled$whas ;

  // register metaBram_serverAdapterB_3_s1
  assign metaBram_serverAdapterB_3_s1$D_IN =
	     { metaBram_serverAdapterB_3_writeWithResp$whas &&
	       metaBram_serverAdapterB_3_s1_1$wget[1],
	       metaBram_serverAdapterB_3_s1_1$wget[0] } ;
  assign metaBram_serverAdapterB_3_s1$EN = 1'd1 ;

  // register metaBram_serverAdapterB_cnt
  assign metaBram_serverAdapterB_cnt$D_IN =
	     metaBram_serverAdapterB_cnt_51_PLUS_IF_metaBra_ETC___d457 ;
  assign metaBram_serverAdapterB_cnt$EN =
	     metaBram_serverAdapterB_cnt_1$whas ||
	     metaBram_serverAdapterB_outData_deqCalled$whas ;

  // register metaBram_serverAdapterB_s1
  assign metaBram_serverAdapterB_s1$D_IN =
	     { metaBram_serverAdapterB_writeWithResp$whas &&
	       metaBram_serverAdapterB_s1_1$wget[1],
	       metaBram_serverAdapterB_s1_1$wget[0] } ;
  assign metaBram_serverAdapterB_s1$EN = 1'd1 ;

  // register metaPtr_modulus
  assign metaPtr_modulus$D_IN =
	     MUX_metaPtr_modulus$write_1__SEL_1 ?
	       MUX_metaPtr_modulus$write_1__VAL_1 :
	       16'd0 ;
  assign metaPtr_modulus$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h04 ||
	     MUX_controlReg$write_1__SEL_2 ;

  // register metaPtr_value
  assign metaPtr_value$D_IN =
	     MUX_metaPtr_modulus$write_1__SEL_1 ?
	       16'd0 :
	       MUX_metaPtr_value$write_1__VAL_3 ;
  assign metaPtr_value$EN =
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0 &&
	     wci_wslv_reqF$D_OUT[39:32] == 8'h04 ||
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;

  // register splitReadInFlight
  assign splitReadInFlight$D_IN = MUX_splitReadInFlight$write_1__SEL_1 ;
  assign splitReadInFlight$EN =
	     WILL_FIRE_RL_wci_cfrd &&
	     (wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
	      wci_wslv_reqF$D_OUT[63:52] == 12'h400) ||
	     MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ;

  // register thisLength
  assign thisLength$D_IN = v__h24797 ;
  assign thisLength$EN = MUX_unrollCnt$write_1__SEL_1 ;

  // register thisOpcode
  assign thisOpcode$D_IN = metaBram_serverAdapterA_1_outData_outData$wget ;
  assign thisOpcode$EN = MUX_unrollCnt$write_1__SEL_1 ;

  // register thisTLS
  assign thisTLS$D_IN = metaBram_serverAdapterA_3_outData_outData$wget ;
  assign thisTLS$EN = MUX_unrollCnt$write_1__SEL_1 ;

  // register thisTMS
  assign thisTMS$D_IN = metaBram_serverAdapterA_2_outData_outData$wget ;
  assign thisTMS$EN = MUX_unrollCnt$write_1__SEL_1 ;

  // register unrollCnt
  assign unrollCnt$D_IN =
	     MUX_unrollCnt$write_1__SEL_1 ?
	       MUX_unrollCnt$write_1__VAL_1 :
	       MUX_unrollCnt$write_1__VAL_2 ;
  assign unrollCnt$EN =
	     MUX_unrollCnt$write_1__SEL_1 || wsiM_reqFifo_enqueueing$whas ;

  // register wci_wslv_cEdge
  assign wci_wslv_cEdge$D_IN = wci_wslv_reqF$D_OUT[36:34] ;
  assign wci_wslv_cEdge$EN = WILL_FIRE_RL_wci_wslv_ctl_op_start ;

  // register wci_wslv_cState
  assign wci_wslv_cState$D_IN = wci_wslv_nState ;
  assign wci_wslv_cState$EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge ;

  // register wci_wslv_ctlAckReg
  assign wci_wslv_ctlAckReg$D_IN = wci_wslv_ctlAckReg_1$whas ;
  assign wci_wslv_ctlAckReg$EN = 1'd1 ;

  // register wci_wslv_ctlOpActive
  assign wci_wslv_ctlOpActive$D_IN = !WILL_FIRE_RL_wci_wslv_ctl_op_complete ;
  assign wci_wslv_ctlOpActive$EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_start ;

  // register wci_wslv_illegalEdge
  assign wci_wslv_illegalEdge$D_IN =
	     MUX_wci_wslv_illegalEdge$write_1__SEL_1 &&
	     MUX_wci_wslv_illegalEdge$write_1__VAL_1 ;
  assign wci_wslv_illegalEdge$EN =
	     MUX_wci_wslv_illegalEdge$write_1__SEL_1 ||
	     WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge ;

  // register wci_wslv_isReset_isInReset
  assign wci_wslv_isReset_isInReset$D_IN = 1'd0 ;
  assign wci_wslv_isReset_isInReset$EN = wci_wslv_isReset_isInReset ;

  // register wci_wslv_nState
  always@(wci_wslv_reqF$D_OUT)
  begin
    case (wci_wslv_reqF$D_OUT[36:34])
      3'd0: wci_wslv_nState$D_IN = 3'd1;
      3'd1: wci_wslv_nState$D_IN = 3'd2;
      3'd2: wci_wslv_nState$D_IN = 3'd3;
      default: wci_wslv_nState$D_IN = 3'd0;
    endcase
  end
  assign wci_wslv_nState$EN =
	     WILL_FIRE_RL_wci_wslv_ctl_op_start &&
	     (wci_wslv_reqF$D_OUT[36:34] == 3'd0 && wci_wslv_cState == 3'd0 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd1 &&
	      (wci_wslv_cState == 3'd1 || wci_wslv_cState == 3'd3) ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd2 && wci_wslv_cState == 3'd2 ||
	      wci_wslv_reqF$D_OUT[36:34] == 3'd3 &&
	      (wci_wslv_cState == 3'd3 || wci_wslv_cState == 3'd2 ||
	       wci_wslv_cState == 3'd1)) ;

  // register wci_wslv_reqF_countReg
  assign wci_wslv_reqF_countReg$D_IN =
	     (wci_wslv_wciReq$wget[71:69] != 3'd0) ?
	       wci_wslv_reqF_countReg + 2'd1 :
	       wci_wslv_reqF_countReg - 2'd1 ;
  assign wci_wslv_reqF_countReg$EN =
	     (wci_wslv_wciReq$wget[71:69] != 3'd0) !=
	     wci_wslv_reqF_r_deq$whas ;

  // register wci_wslv_respF_c_r
  assign wci_wslv_respF_c_r$D_IN =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr ?
	       MUX_wci_wslv_respF_c_r$write_1__VAL_1 :
	       MUX_wci_wslv_respF_c_r$write_1__VAL_2 ;
  assign wci_wslv_respF_c_r$EN =
	     WILL_FIRE_RL_wci_wslv_respF_incCtr ||
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ;

  // register wci_wslv_respF_q_0
  always@(WILL_FIRE_RL_wci_wslv_respF_both or
	  MUX_wci_wslv_respF_q_0$write_1__VAL_1 or
	  MUX_wci_wslv_respF_q_0$write_1__SEL_2 or
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_wci_wslv_respF_decCtr or wci_wslv_respF_q_1)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_wci_wslv_respF_both:
	  wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_1;
      MUX_wci_wslv_respF_q_0$write_1__SEL_2:
	  wci_wslv_respF_q_0$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
      WILL_FIRE_RL_wci_wslv_respF_decCtr:
	  wci_wslv_respF_q_0$D_IN = wci_wslv_respF_q_1;
      default: wci_wslv_respF_q_0$D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wci_wslv_respF_q_0$EN =
	     WILL_FIRE_RL_wci_wslv_respF_both ||
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_c_r == 2'd0 ||
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ;

  // register wci_wslv_respF_q_1
  always@(WILL_FIRE_RL_wci_wslv_respF_both or
	  MUX_wci_wslv_respF_q_1$write_1__VAL_1 or
	  MUX_wci_wslv_respF_q_1$write_1__SEL_2 or
	  MUX_wci_wslv_respF_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_wci_wslv_respF_decCtr)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_wci_wslv_respF_both:
	  wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_1$write_1__VAL_1;
      MUX_wci_wslv_respF_q_1$write_1__SEL_2:
	  wci_wslv_respF_q_1$D_IN = MUX_wci_wslv_respF_q_0$write_1__VAL_2;
      WILL_FIRE_RL_wci_wslv_respF_decCtr:
	  wci_wslv_respF_q_1$D_IN = 34'h0AAAAAAAA;
      default: wci_wslv_respF_q_1$D_IN =
		   34'h2AAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wci_wslv_respF_q_1$EN =
	     WILL_FIRE_RL_wci_wslv_respF_both ||
	     WILL_FIRE_RL_wci_wslv_respF_incCtr &&
	     wci_wslv_respF_c_r == 2'd1 ||
	     WILL_FIRE_RL_wci_wslv_respF_decCtr ;

  // register wci_wslv_sFlagReg
  assign wci_wslv_sFlagReg$D_IN = 1'b0 ;
  assign wci_wslv_sFlagReg$EN = 1'd1 ;

  // register wci_wslv_sThreadBusy_d
  assign wci_wslv_sThreadBusy_d$D_IN = 1'b0 ;
  assign wci_wslv_sThreadBusy_d$EN = 1'd1 ;

  // register wsiM_burstKind
  assign wsiM_burstKind$D_IN =
	     (wsiM_burstKind == 2'd0) ?
	       (wsiM_reqFifo_q_0[56] ? 2'd1 : 2'd2) :
	       2'd0 ;
  assign wsiM_burstKind$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_deq &&
	     wsiM_reqFifo_q_0[60:58] == 3'd1 &&
	     (wsiM_burstKind == 2'd0 ||
	      (wsiM_burstKind == 2'd1 || wsiM_burstKind == 2'd2) &&
	      wsiM_reqFifo_q_0[57]) ;

  // register wsiM_errorSticky
  assign wsiM_errorSticky$D_IN = 1'b0 ;
  assign wsiM_errorSticky$EN = 1'b0 ;

  // register wsiM_iMesgCount
  assign wsiM_iMesgCount$D_IN = wsiM_iMesgCount + 32'd1 ;
  assign wsiM_iMesgCount$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_deq &&
	     wsiM_reqFifo_q_0[60:58] == 3'd1 &&
	     wsiM_burstKind == 2'd2 &&
	     wsiM_reqFifo_q_0[57] ;

  // register wsiM_isReset_isInReset
  assign wsiM_isReset_isInReset$D_IN = 1'd0 ;
  assign wsiM_isReset_isInReset$EN = wsiM_isReset_isInReset ;

  // register wsiM_operateD
  assign wsiM_operateD$D_IN = wci_wslv_cState == 3'd2 ;
  assign wsiM_operateD$EN = 1'd1 ;

  // register wsiM_pMesgCount
  assign wsiM_pMesgCount$D_IN = wsiM_pMesgCount + 32'd1 ;
  assign wsiM_pMesgCount$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_deq &&
	     wsiM_reqFifo_q_0[60:58] == 3'd1 &&
	     wsiM_burstKind == 2'd1 &&
	     wsiM_reqFifo_q_0[57] ;

  // register wsiM_peerIsReady
  assign wsiM_peerIsReady$D_IN = wsiM0_SReset_n ;
  assign wsiM_peerIsReady$EN = 1'd1 ;

  // register wsiM_reqFifo_c_r
  assign wsiM_reqFifo_c_r$D_IN =
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr ?
	       MUX_wsiM_reqFifo_c_r$write_1__VAL_1 :
	       MUX_wsiM_reqFifo_c_r$write_1__VAL_2 ;
  assign wsiM_reqFifo_c_r$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr ||
	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;

  // register wsiM_reqFifo_q_0
  always@(WILL_FIRE_RL_wsiM_reqFifo_both or
	  MUX_wsiM_reqFifo_q_0$write_1__VAL_1 or
	  MUX_wsiM_reqFifo_q_0$write_1__SEL_2 or
	  MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_wsiM_reqFifo_decCtr or wsiM_reqFifo_q_1)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_wsiM_reqFifo_both:
	  wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_1;
      MUX_wsiM_reqFifo_q_0$write_1__SEL_2:
	  wsiM_reqFifo_q_0$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
      WILL_FIRE_RL_wsiM_reqFifo_decCtr:
	  wsiM_reqFifo_q_0$D_IN = wsiM_reqFifo_q_1;
      default: wsiM_reqFifo_q_0$D_IN =
		   61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wsiM_reqFifo_q_0$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_both ||
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd0 ||
	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;

  // register wsiM_reqFifo_q_1
  always@(WILL_FIRE_RL_wsiM_reqFifo_both or
	  MUX_wsiM_reqFifo_q_1$write_1__VAL_1 or
	  MUX_wsiM_reqFifo_q_1$write_1__SEL_2 or
	  MUX_wsiM_reqFifo_q_0$write_1__VAL_2 or
	  WILL_FIRE_RL_wsiM_reqFifo_decCtr)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_wsiM_reqFifo_both:
	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_1$write_1__VAL_1;
      MUX_wsiM_reqFifo_q_1$write_1__SEL_2:
	  wsiM_reqFifo_q_1$D_IN = MUX_wsiM_reqFifo_q_0$write_1__VAL_2;
      WILL_FIRE_RL_wsiM_reqFifo_decCtr:
	  wsiM_reqFifo_q_1$D_IN = 61'h00000AAAAAAAAA00;
      default: wsiM_reqFifo_q_1$D_IN =
		   61'h0AAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign wsiM_reqFifo_q_1$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_both ||
	     WILL_FIRE_RL_wsiM_reqFifo_incCtr && wsiM_reqFifo_c_r == 2'd1 ||
	     WILL_FIRE_RL_wsiM_reqFifo_decCtr ;

  // register wsiM_sThreadBusy_d
  assign wsiM_sThreadBusy_d$D_IN = wsiM0_SThreadBusy ;
  assign wsiM_sThreadBusy_d$EN = 1'd1 ;

  // register wsiM_statusR
  assign wsiM_statusR$D_IN =
	     { wsiM_isReset_isInReset,
	       !wsiM_peerIsReady,
	       !wsiM_operateD,
	       wsiM_errorSticky,
	       wsiM_burstKind != 2'd0,
	       wsiM_sThreadBusy_d,
	       1'd0,
	       wsiM_trafficSticky } ;
  assign wsiM_statusR$EN = 1'd1 ;

  // register wsiM_tBusyCount
  assign wsiM_tBusyCount$D_IN = wsiM_tBusyCount + 32'd1 ;
  assign wsiM_tBusyCount$EN =
	     wsiM_operateD && wsiM_peerIsReady && wsiM_sThreadBusy_d ;

  // register wsiM_trafficSticky
  assign wsiM_trafficSticky$D_IN = 1'd1 ;
  assign wsiM_trafficSticky$EN =
	     WILL_FIRE_RL_wsiM_reqFifo_deq &&
	     wsiM_reqFifo_q_0[60:58] == 3'd1 ;

  // submodule dataBram_memory
  assign dataBram_memory$ADDRA = dataPtr[9:0] ;
  assign dataBram_memory$ADDRB = wci_wslv_reqF$D_OUT[43:34] ;
  assign dataBram_memory$DIA = 32'd0 ;
  assign dataBram_memory$DIB =
	     MUX_dataBram_memory$b_put_1__SEL_1 ?
	       32'd0 :
	       wci_wslv_reqF$D_OUT[31:0] ;
  assign dataBram_memory$WEA = 1'd0 ;
  assign dataBram_memory$WEB = !MUX_dataBram_memory$b_put_1__SEL_1 ;
  assign dataBram_memory$ENA =
	     WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ;
  assign dataBram_memory$ENB =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ||
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h800 ;

  // submodule dataBram_serverAdapterA_outDataCore
  assign dataBram_serverAdapterA_outDataCore$D_IN = dataBram_memory$DOA ;
  assign dataBram_serverAdapterA_outDataCore$ENQ =
	     WILL_FIRE_RL_dataBram_serverAdapterA_outData_enqAndDeq ||
	     dataBram_serverAdapterA_outDataCore$FULL_N &&
	     !dataBram_serverAdapterA_outData_deqCalled$whas &&
	     dataBram_serverAdapterA_outData_enqData$whas ;
  assign dataBram_serverAdapterA_outDataCore$DEQ =
	     WILL_FIRE_RL_dataBram_serverAdapterA_outData_enqAndDeq ||
	     dataBram_serverAdapterA_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterA_outData_deqCalled$whas &&
	     !dataBram_serverAdapterA_outData_enqData$whas ;
  assign dataBram_serverAdapterA_outDataCore$CLR = 1'b0 ;

  // submodule dataBram_serverAdapterB_outDataCore
  assign dataBram_serverAdapterB_outDataCore$D_IN = dataBram_memory$DOB ;
  assign dataBram_serverAdapterB_outDataCore$ENQ =
	     WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq ||
	     dataBram_serverAdapterB_outDataCore$FULL_N &&
	     !dataBram_serverAdapterB_outData_deqCalled$whas &&
	     dataBram_serverAdapterB_outData_enqData$whas ;
  assign dataBram_serverAdapterB_outDataCore$DEQ =
	     WILL_FIRE_RL_dataBram_serverAdapterB_outData_enqAndDeq ||
	     dataBram_serverAdapterB_outDataCore$EMPTY_N &&
	     dataBram_serverAdapterB_outData_deqCalled$whas &&
	     !dataBram_serverAdapterB_outData_enqData$whas ;
  assign dataBram_serverAdapterB_outDataCore$CLR = 1'b0 ;

  // submodule loopReqInFlightF
  assign loopReqInFlightF$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign loopReqInFlightF$DEQ =
	     wsiM_reqFifo_enqueueing$whas &&
	     (thisLength == 32'd0 || unrollCnt == 16'd1) ;
  assign loopReqInFlightF$CLR = 1'b0 ;

  // submodule metaBram_memory
  assign metaBram_memory$ADDRA = metaPtr_value[9:0] ;
  assign metaBram_memory$ADDRB = wci_wslv_reqF$D_OUT[45:36] ;
  assign metaBram_memory$DIA = 32'd0 ;
  assign metaBram_memory$DIB =
	     MUX_metaBram_memory$b_put_1__SEL_1 ?
	       32'd0 :
	       wci_wslv_reqF$D_OUT[31:0] ;
  assign metaBram_memory$WEA = 1'd0 ;
  assign metaBram_memory$WEB = !MUX_metaBram_memory$b_put_1__SEL_1 ;
  assign metaBram_memory$ENA =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_memory$ENB =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd0 ||
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd0 ;

  // submodule metaBram_memory_1
  assign metaBram_memory_1$ADDRA = metaPtr_value[9:0] ;
  assign metaBram_memory_1$ADDRB = wci_wslv_reqF$D_OUT[45:36] ;
  assign metaBram_memory_1$DIA = 32'd0 ;
  assign metaBram_memory_1$DIB =
	     MUX_metaBram_memory_1$b_put_1__SEL_1 ?
	       32'd0 :
	       wci_wslv_reqF$D_OUT[31:0] ;
  assign metaBram_memory_1$WEA = 1'd0 ;
  assign metaBram_memory_1$WEB = !MUX_metaBram_memory_1$b_put_1__SEL_1 ;
  assign metaBram_memory_1$ENA =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_memory_1$ENB =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd1 ||
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd1 ;

  // submodule metaBram_memory_2
  assign metaBram_memory_2$ADDRA = metaPtr_value[9:0] ;
  assign metaBram_memory_2$ADDRB = wci_wslv_reqF$D_OUT[45:36] ;
  assign metaBram_memory_2$DIA = 32'd0 ;
  assign metaBram_memory_2$DIB =
	     MUX_metaBram_memory_2$b_put_1__SEL_1 ?
	       32'd0 :
	       wci_wslv_reqF$D_OUT[31:0] ;
  assign metaBram_memory_2$WEA = 1'd0 ;
  assign metaBram_memory_2$WEB = !MUX_metaBram_memory_2$b_put_1__SEL_1 ;
  assign metaBram_memory_2$ENA =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_memory_2$ENB =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd2 ||
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd2 ;

  // submodule metaBram_memory_3
  assign metaBram_memory_3$ADDRA = metaPtr_value[9:0] ;
  assign metaBram_memory_3$ADDRB = wci_wslv_reqF$D_OUT[45:36] ;
  assign metaBram_memory_3$DIA = 32'd0 ;
  assign metaBram_memory_3$DIB =
	     MUX_metaBram_memory_3$b_put_1__SEL_1 ?
	       32'd0 :
	       wci_wslv_reqF$D_OUT[31:0] ;
  assign metaBram_memory_3$WEA = 1'd0 ;
  assign metaBram_memory_3$WEB = !MUX_metaBram_memory_3$b_put_1__SEL_1 ;
  assign metaBram_memory_3$ENA =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaBram_memory_3$ENB =
	     WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd3 ||
	     WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400 &&
	     wci_wslv_reqF$D_OUT[35:34] == 2'd3 ;

  // submodule metaBram_serverAdapterA_1_outDataCore
  assign metaBram_serverAdapterA_1_outDataCore$D_IN = metaBram_memory_1$DOA ;
  assign metaBram_serverAdapterA_1_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_1_outData_enqAndDeq ||
	     metaBram_serverAdapterA_1_outDataCore$FULL_N &&
	     !MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_1_outData_enqData$whas ;
  assign metaBram_serverAdapterA_1_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_1_outData_enqAndDeq ||
	     metaBram_serverAdapterA_1_outDataCore$EMPTY_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     !metaBram_serverAdapterA_1_outData_enqData$whas ;
  assign metaBram_serverAdapterA_1_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterA_2_outDataCore
  assign metaBram_serverAdapterA_2_outDataCore$D_IN = metaBram_memory_2$DOA ;
  assign metaBram_serverAdapterA_2_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_2_outData_enqAndDeq ||
	     metaBram_serverAdapterA_2_outDataCore$FULL_N &&
	     !MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_2_outData_enqData$whas ;
  assign metaBram_serverAdapterA_2_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_2_outData_enqAndDeq ||
	     metaBram_serverAdapterA_2_outDataCore$EMPTY_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     !metaBram_serverAdapterA_2_outData_enqData$whas ;
  assign metaBram_serverAdapterA_2_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterA_3_outDataCore
  assign metaBram_serverAdapterA_3_outDataCore$D_IN = metaBram_memory_3$DOA ;
  assign metaBram_serverAdapterA_3_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_3_outData_enqAndDeq ||
	     metaBram_serverAdapterA_3_outDataCore$FULL_N &&
	     !MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_3_outData_enqData$whas ;
  assign metaBram_serverAdapterA_3_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_3_outData_enqAndDeq ||
	     metaBram_serverAdapterA_3_outDataCore$EMPTY_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     !metaBram_serverAdapterA_3_outData_enqData$whas ;
  assign metaBram_serverAdapterA_3_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterA_outDataCore
  assign metaBram_serverAdapterA_outDataCore$D_IN = metaBram_memory$DOA ;
  assign metaBram_serverAdapterA_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_outData_enqAndDeq ||
	     metaBram_serverAdapterA_outDataCore$FULL_N &&
	     !MUX_unrollCnt$write_1__SEL_1 &&
	     metaBram_serverAdapterA_outData_enqData$whas ;
  assign metaBram_serverAdapterA_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_outData_enqAndDeq ||
	     metaBram_serverAdapterA_outDataCore$EMPTY_N &&
	     MUX_unrollCnt$write_1__SEL_1 &&
	     !metaBram_serverAdapterA_outData_enqData$whas ;
  assign metaBram_serverAdapterA_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterB_1_outDataCore
  assign metaBram_serverAdapterB_1_outDataCore$D_IN = metaBram_memory_1$DOB ;
  assign metaBram_serverAdapterB_1_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq ||
	     metaBram_serverAdapterB_1_outDataCore$FULL_N &&
	     !metaBram_serverAdapterB_1_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_1_outData_enqData$whas ;
  assign metaBram_serverAdapterB_1_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_1_outData_enqAndDeq ||
	     metaBram_serverAdapterB_1_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_1_outData_deqCalled$whas &&
	     !metaBram_serverAdapterB_1_outData_enqData$whas ;
  assign metaBram_serverAdapterB_1_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterB_2_outDataCore
  assign metaBram_serverAdapterB_2_outDataCore$D_IN = metaBram_memory_2$DOB ;
  assign metaBram_serverAdapterB_2_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq ||
	     metaBram_serverAdapterB_2_outDataCore$FULL_N &&
	     !metaBram_serverAdapterB_2_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_2_outData_enqData$whas ;
  assign metaBram_serverAdapterB_2_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_2_outData_enqAndDeq ||
	     metaBram_serverAdapterB_2_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_2_outData_deqCalled$whas &&
	     !metaBram_serverAdapterB_2_outData_enqData$whas ;
  assign metaBram_serverAdapterB_2_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterB_3_outDataCore
  assign metaBram_serverAdapterB_3_outDataCore$D_IN = metaBram_memory_3$DOB ;
  assign metaBram_serverAdapterB_3_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq ||
	     metaBram_serverAdapterB_3_outDataCore$FULL_N &&
	     !metaBram_serverAdapterB_3_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_3_outData_enqData$whas ;
  assign metaBram_serverAdapterB_3_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_3_outData_enqAndDeq ||
	     metaBram_serverAdapterB_3_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_3_outData_deqCalled$whas &&
	     !metaBram_serverAdapterB_3_outData_enqData$whas ;
  assign metaBram_serverAdapterB_3_outDataCore$CLR = 1'b0 ;

  // submodule metaBram_serverAdapterB_outDataCore
  assign metaBram_serverAdapterB_outDataCore$D_IN = metaBram_memory$DOB ;
  assign metaBram_serverAdapterB_outDataCore$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq ||
	     metaBram_serverAdapterB_outDataCore$FULL_N &&
	     !metaBram_serverAdapterB_outData_deqCalled$whas &&
	     metaBram_serverAdapterB_outData_enqData$whas ;
  assign metaBram_serverAdapterB_outDataCore$DEQ =
	     WILL_FIRE_RL_metaBram_serverAdapterB_outData_enqAndDeq ||
	     metaBram_serverAdapterB_outDataCore$EMPTY_N &&
	     metaBram_serverAdapterB_outData_deqCalled$whas &&
	     !metaBram_serverAdapterB_outData_enqData$whas ;
  assign metaBram_serverAdapterB_outDataCore$CLR = 1'b0 ;

  // submodule metaReqInFlightF
  assign metaReqInFlightF$ENQ =
	     WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ;
  assign metaReqInFlightF$DEQ = MUX_unrollCnt$write_1__SEL_1 ;
  assign metaReqInFlightF$CLR = 1'b0 ;

  // submodule splaF
  assign splaF$D_IN =
	     (wci_wslv_reqF$D_OUT[63:52] == 12'h800) ?
	       3'd4 :
	       { 1'd0, wci_wslv_reqF$D_OUT[35:34] } ;
  assign splaF$ENQ = MUX_splitReadInFlight$write_1__SEL_1 ;
  assign splaF$DEQ = MUX_wci_wslv_respF_x_wire$wset_1__SEL_3 ;
  assign splaF$CLR = 1'b0 ;

  // submodule wci_wslv_reqF
  assign wci_wslv_reqF$D_IN = wci_wslv_wciReq$wget ;
  assign wci_wslv_reqF$ENQ = wci_wslv_wciReq$wget[71:69] != 3'd0 ;
  assign wci_wslv_reqF$DEQ = wci_wslv_reqF_r_deq$whas ;
  assign wci_wslv_reqF$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042 =
	     IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 &&
	     CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 ;
  assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092 =
	     (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd2) ?
	       (metaBram_serverAdapterB_2_cnt ^ 3'h4) < 3'd7 :
	       !wci_wslv_reqF$EMPTY_N || wci_wslv_reqF$D_OUT[35:34] != 2'd3 ||
	       (metaBram_serverAdapterB_3_cnt ^ 3'h4) < 3'd7 ;
  assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093 =
	     (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd1) ?
	       (metaBram_serverAdapterB_1_cnt ^ 3'h4) < 3'd7 :
	       IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1092 ;
  assign IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1422 =
	     (wci_wslv_reqF$EMPTY_N && wci_wslv_reqF$D_OUT[35:34] == 2'd0) ?
	       (metaBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 :
	       IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1093 ;
  assign ab__h11724 = MUX_dataBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ;
  assign ab__h14842 = MUX_metaBram_memory$b_put_1__SEL_1 ? 2'd0 : 2'd2 ;
  assign ab__h17788 = MUX_metaBram_memory_1$b_put_1__SEL_1 ? 2'd0 : 2'd2 ;
  assign ab__h20734 = MUX_metaBram_memory_2$b_put_1__SEL_1 ? 2'd0 : 2'd2 ;
  assign ab__h23680 = MUX_metaBram_memory_3$b_put_1__SEL_1 ? 2'd0 : 2'd2 ;
  assign b__h25414 = x__h25430 + residue__h25403 ;
  assign dataBram_serverAdapterA_cnt_74_PLUS_IF_dataBra_ETC___d280 =
	     dataBram_serverAdapterA_cnt +
	     (WILL_FIRE_RL_dataBram_serverAdapterA_stageReadResponseAlways ?
		3'd1 :
		3'd0) +
	     (dataBram_serverAdapterA_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign dataBram_serverAdapterB_cnt_33_PLUS_IF_dataBra_ETC___d339 =
	     dataBram_serverAdapterB_cnt +
	     (dataBram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
	     (dataBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign dataBram_serverAdapterB_cnt_33_SLT_3___d1324 =
	     (dataBram_serverAdapterB_cnt ^ 3'h4) < 3'd7 ;
  assign doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913 =
	     doZLM ||
	     (dataBram_serverAdapterA_outDataCore$EMPTY_N ||
	      dataBram_serverAdapterA_outData_enqData$whas) &&
	     dataBram_serverAdapterA_outData_outData$whas ;
  assign doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d923 =
	     doZLM_09_OR_dataBram_serverAdapterA_outDataCor_ETC___d913 &&
	     (thisLength != 32'd0 && unrollCnt != 16'd1 ||
	      loopReqInFlightF$EMPTY_N) ;
  assign g_data__h33410 =
	     (wci_wslv_reqF$D_OUT[63:52] == 12'h0) ? v__h32384 : 32'd0 ;
  assign metaBram_serverAdapterA_1_cnt_10_PLUS_IF_metaB_ETC___d516 =
	     metaBram_serverAdapterA_1_cnt +
	     (WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ?
		3'd1 :
		3'd0) +
	     (MUX_unrollCnt$write_1__SEL_1 ? 3'd7 : 3'd0) ;
  assign metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871 =
	     metaBram_serverAdapterA_1_outData_outData$whas &&
	     (metaBram_serverAdapterA_2_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterA_2_outData_enqData$whas) &&
	     metaBram_serverAdapterA_2_outData_outData$whas &&
	     (metaBram_serverAdapterA_3_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterA_3_outData_enqData$whas) &&
	     metaBram_serverAdapterA_3_outData_outData$whas ;
  assign metaBram_serverAdapterA_2_cnt_28_PLUS_IF_metaB_ETC___d634 =
	     metaBram_serverAdapterA_2_cnt +
	     (WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ?
		3'd1 :
		3'd0) +
	     (MUX_unrollCnt$write_1__SEL_1 ? 3'd7 : 3'd0) ;
  assign metaBram_serverAdapterA_3_cnt_46_PLUS_IF_metaB_ETC___d752 =
	     metaBram_serverAdapterA_3_cnt +
	     (WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ?
		3'd1 :
		3'd0) +
	     (MUX_unrollCnt$write_1__SEL_1 ? 3'd7 : 3'd0) ;
  assign metaBram_serverAdapterA_cnt_92_PLUS_IF_metaBra_ETC___d398 =
	     metaBram_serverAdapterA_cnt +
	     (WILL_FIRE_RL_metaBram_serverAdapterA_stageReadResponseAlways ?
		3'd1 :
		3'd0) +
	     (MUX_unrollCnt$write_1__SEL_1 ? 3'd7 : 3'd0) ;
  assign metaBram_serverAdapterB_1_cnt_69_PLUS_IF_metaB_ETC___d575 =
	     metaBram_serverAdapterB_1_cnt +
	     (metaBram_serverAdapterB_1_cnt_1$whas ? 3'd1 : 3'd0) +
	     (metaBram_serverAdapterB_1_outData_deqCalled$whas ?
		3'd7 :
		3'd0) ;
  assign metaBram_serverAdapterB_2_cnt_87_PLUS_IF_metaB_ETC___d693 =
	     metaBram_serverAdapterB_2_cnt +
	     (metaBram_serverAdapterB_2_cnt_1$whas ? 3'd1 : 3'd0) +
	     (metaBram_serverAdapterB_2_outData_deqCalled$whas ?
		3'd7 :
		3'd0) ;
  assign metaBram_serverAdapterB_3_cnt_05_PLUS_IF_metaB_ETC___d811 =
	     metaBram_serverAdapterB_3_cnt +
	     (metaBram_serverAdapterB_3_cnt_1$whas ? 3'd1 : 3'd0) +
	     (metaBram_serverAdapterB_3_outData_deqCalled$whas ?
		3'd7 :
		3'd0) ;
  assign metaBram_serverAdapterB_cnt_51_PLUS_IF_metaBra_ETC___d457 =
	     metaBram_serverAdapterB_cnt +
	     (metaBram_serverAdapterB_cnt_1$whas ? 3'd1 : 3'd0) +
	     (metaBram_serverAdapterB_outData_deqCalled$whas ? 3'd7 : 3'd0) ;
  assign metaReqInFlightF_i_notEmpty__59_AND_metaBram_s_ETC___d875 =
	     metaReqInFlightF$EMPTY_N &&
	     (metaBram_serverAdapterA_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterA_outData_enqData$whas) &&
	     metaBram_serverAdapterA_outData_outData$whas &&
	     (metaBram_serverAdapterA_1_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterA_1_outData_enqData$whas) &&
	     metaBram_serverAdapterA_1_outData_outData_whas_ETC___d871 ;
  assign rdat___1__h32570 = hasDebugLogic ? { 24'd0, wsiM_statusR } : 32'd0 ;
  assign rdat___1__h32625 =
	     hasDebugLogic ? wsiM_extStatusW$wget[95:64] : 32'd0 ;
  assign rdat___1__h32639 =
	     hasDebugLogic ? wsiM_extStatusW$wget[63:32] : 32'd0 ;
  assign rdat___1__h32647 =
	     hasDebugLogic ? wsiM_extStatusW$wget[31:0] : 32'd0 ;
  assign residue__h25403 =
	     ({ 4'd0, v__h24797[1:0] } == 6'd0) ? 32'd0 : 32'd1 ;
  assign splaF_i_notEmpty__011_AND_IF_splaF_first__012__ETC___d1044 =
	     splaF$EMPTY_N &&
	     (splaF$D_OUT[2] ?
		(splaF$D_OUT[1:0] != 2'd0 ||
		 dataBram_serverAdapterB_outDataCore$EMPTY_N ||
		 dataBram_serverAdapterB_outData_enqData$whas) &&
		(splaF$D_OUT[1:0] != 2'd0 ||
		 dataBram_serverAdapterB_outData_outData$whas) :
		IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1042) ;
  assign v__h24797 =
	     metaBram_serverAdapterA_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterA_outDataCore$D_OUT :
	       metaBram_memory$DOA ;
  assign v__h29897 =
	     splaF$D_OUT[2] ?
	       y_avValue__h30523 :
	       IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 ;
  assign x__h25430 = { 2'd0, v__h24797[31:2] } ;
  assign x__h26388 =
	     ({ 4'd0, thisLength[1:0] } == 6'd0) ?
	       32'hFFFFFFFF :
	       (({ 4'd0, thisLength[1:0] } <= 6'd1) ?
		  32'd1 :
		  (({ 4'd0, thisLength[1:0] } <= 6'd2) ?
		     32'd3 :
		     (({ 4'd0, thisLength[1:0] } <= 6'd3) ?
			32'd7 :
			(({ 4'd0, thisLength[1:0] } <= 6'd4) ?
			   32'd15 :
			   (({ 4'd0, thisLength[1:0] } <= 6'd5) ?
			      32'd31 :
			      (({ 4'd0, thisLength[1:0] } <= 6'd6) ?
				 32'd63 :
				 (({ 4'd0, thisLength[1:0] } <= 6'd7) ?
				    32'd127 :
				    (({ 4'd0, thisLength[1:0] } <= 6'd8) ?
				       32'd255 :
				       (({ 4'd0, thisLength[1:0] } <= 6'd9) ?
					  32'd511 :
					  (({ 4'd0, thisLength[1:0] } <=
					    6'd10) ?
					     32'd1023 :
					     (({ 4'd0, thisLength[1:0] } <=
					       6'd11) ?
						32'd2047 :
						(({ 4'd0, thisLength[1:0] } <=
						  6'd12) ?
						   32'd4095 :
						   (({ 4'd0,
						       thisLength[1:0] } <=
						     6'd13) ?
						      32'd8191 :
						      (({ 4'd0,
							  thisLength[1:0] } <=
							6'd14) ?
							 32'd16383 :
							 (({ 4'd0,
							     thisLength[1:0] } <=
							   6'd15) ?
							    32'd32767 :
							    (({ 4'd0,
								thisLength[1:0] } <=
							      6'd16) ?
							       32'd65535 :
							       (({ 4'd0,
								   thisLength[1:0] } <=
								 6'd17) ?
								  32'd131071 :
								  (({ 4'd0,
								      thisLength[1:0] } <=
								    6'd18) ?
								     32'd262143 :
								     (({ 4'd0,
									 thisLength[1:0] } <=
								       6'd19) ?
									32'd524287 :
									(({ 4'd0,
									    thisLength[1:0] } <=
									  6'd20) ?
									   32'd1048575 :
									   (({ 4'd0,
									       thisLength[1:0] } <=
									     6'd21) ?
									      32'd2097151 :
									      (({ 4'd0,
										  thisLength[1:0] } <=
										6'd22) ?
										 32'd4194303 :
										 (({ 4'd0,
										     thisLength[1:0] } <=
										   6'd23) ?
										    32'd8388607 :
										    (({ 4'd0,
											thisLength[1:0] } <=
										      6'd24) ?
										       32'd16777215 :
										       (({ 4'd0,
											   thisLength[1:0] } <=
											 6'd25) ?
											  32'd33554431 :
											  (({ 4'd0,
											      thisLength[1:0] } <=
											    6'd26) ?
											     32'd67108863 :
											     (({ 4'd0,
												 thisLength[1:0] } <=
											       6'd27) ?
												32'd134217727 :
												(({ 4'd0,
												    thisLength[1:0] } <=
												  6'd28) ?
												   32'd268435455 :
												   (({ 4'd0,
												       thisLength[1:0] } <=
												     6'd29) ?
												      32'd536870911 :
												      (({ 4'd0,
													  thisLength[1:0] } <=
													6'd30) ?
													 32'd1073741823 :
													 (({ 4'd0,
													     thisLength[1:0] } <=
													   6'd31) ?
													    32'h7FFFFFFF :
													    32'hFFFFFFFF))))))))))))))))))))))))))))))) ;
  assign x_burstLength__h26222 =
	     (thisLength == 32'd0 || unrollCnt == 16'd1) ? 12'd1 : 12'd4095 ;
  assign x_byteEn__h26224 =
	     (thisLength == 32'd0) ?
	       4'd0 :
	       ((unrollCnt == 16'd1) ? x__h26388[3:0] : 4'd15) ;
  assign y_avValue__h30523 =
	     dataBram_serverAdapterB_outDataCore$EMPTY_N ?
	       dataBram_serverAdapterB_outDataCore$D_OUT :
	       dataBram_memory$DOB ;
  assign y_avValue__h30567 =
	     metaBram_serverAdapterB_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterB_outDataCore$D_OUT :
	       metaBram_memory$DOB ;
  assign y_avValue__h30607 =
	     metaBram_serverAdapterB_1_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterB_1_outDataCore$D_OUT :
	       metaBram_memory_1$DOB ;
  assign y_avValue__h30647 =
	     metaBram_serverAdapterB_2_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterB_2_outDataCore$D_OUT :
	       metaBram_memory_2$DOB ;
  assign y_avValue__h30687 =
	     metaBram_serverAdapterB_3_outDataCore$EMPTY_N ?
	       metaBram_serverAdapterB_3_outDataCore$D_OUT :
	       metaBram_memory_3$DOB ;
  always@(wci_wslv_reqF$D_OUT or
	  controlReg or
	  mesgCount or
	  dataCount or
	  mesgRemain or
	  rdat___1__h32570 or
	  rdat___1__h32625 or rdat___1__h32639 or rdat___1__h32647)
  begin
    case (wci_wslv_reqF$D_OUT[39:32])
      8'h0: v__h32384 = controlReg;
      8'h08: v__h32384 = mesgCount;
      8'h0C: v__h32384 = dataCount;
      8'h10: v__h32384 = mesgRemain;
      8'h1C: v__h32384 = 32'hA0240A0A;
      8'h20: v__h32384 = rdat___1__h32570;
      8'h24: v__h32384 = rdat___1__h32625;
      8'h28: v__h32384 = rdat___1__h32639;
      8'h2C: v__h32384 = rdat___1__h32647;
      default: v__h32384 = 32'd0;
    endcase
  end
  always@(splaF$D_OUT or
	  y_avValue__h30687 or
	  y_avValue__h30567 or y_avValue__h30607 or y_avValue__h30647)
  begin
    case (splaF$D_OUT[1:0])
      2'd0:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 =
	      y_avValue__h30567;
      2'd1:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 =
	      y_avValue__h30607;
      2'd2:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 =
	      y_avValue__h30647;
      2'd3:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1066 =
	      y_avValue__h30687;
    endcase
  end
  always@(wci_wslv_reqF$D_OUT or
	  splaF$FULL_N or
	  IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1422 or
	  dataBram_serverAdapterB_cnt_33_SLT_3___d1324)
  begin
    case (wci_wslv_reqF$D_OUT[63:52])
      12'h0:
	  IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1140 = 1'b1;
      12'h800:
	  IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1140 =
	      dataBram_serverAdapterB_cnt_33_SLT_3___d1324 && splaF$FULL_N;
      default: IF_wci_wslv_reqF_first__5_BITS_63_TO_52_070_EQ_ETC___d1140 =
		   wci_wslv_reqF$D_OUT[63:52] != 12'h400 ||
		   splaF$FULL_N &&
		   IF_wci_wslv_reqF_i_notEmpty__4_AND_wci_wslv_re_ETC___d1422;
    endcase
  end
  always@(splaF$D_OUT or
	  metaBram_serverAdapterB_3_outDataCore$EMPTY_N or
	  metaBram_serverAdapterB_3_outData_enqData$whas or
	  metaBram_serverAdapterB_outDataCore$EMPTY_N or
	  metaBram_serverAdapterB_outData_enqData$whas or
	  metaBram_serverAdapterB_1_outDataCore$EMPTY_N or
	  metaBram_serverAdapterB_1_outData_enqData$whas or
	  metaBram_serverAdapterB_2_outDataCore$EMPTY_N or
	  metaBram_serverAdapterB_2_outData_enqData$whas)
  begin
    case (splaF$D_OUT[1:0])
      2'd0:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 =
	      metaBram_serverAdapterB_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterB_outData_enqData$whas;
      2'd1:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 =
	      metaBram_serverAdapterB_1_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterB_1_outData_enqData$whas;
      2'd2:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 =
	      metaBram_serverAdapterB_2_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterB_2_outData_enqData$whas;
      2'd3:
	  IF_splaF_first__012_BITS_1_TO_0_014_EQ_0_015_T_ETC___d1033 =
	      splaF$D_OUT[1:0] != 2'd3 ||
	      metaBram_serverAdapterB_3_outDataCore$EMPTY_N ||
	      metaBram_serverAdapterB_3_outData_enqData$whas;
    endcase
  end
  always@(splaF$D_OUT or
	  metaBram_serverAdapterB_3_outData_outData$whas or
	  metaBram_serverAdapterB_outData_outData$whas or
	  metaBram_serverAdapterB_1_outData_outData$whas or
	  metaBram_serverAdapterB_2_outData_outData$whas)
  begin
    case (splaF$D_OUT[1:0])
      2'd0:
	  CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 =
	      metaBram_serverAdapterB_outData_outData$whas;
      2'd1:
	  CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 =
	      metaBram_serverAdapterB_1_outData_outData$whas;
      2'd2:
	  CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 =
	      metaBram_serverAdapterB_2_outData_outData$whas;
      2'd3:
	  CASE_splaFD_OUT_BITS_1_TO_0_NOT_splaFD_OUT_B_ETC__q1 =
	      splaF$D_OUT[1:0] != 2'd3 ||
	      metaBram_serverAdapterB_3_outData_outData$whas;
    endcase
  end

  // handling of inlined registers

  always@(posedge wciS0_Clk)
  begin
    if (wciS0_MReset_n == `BSV_RESET_VALUE)
      begin
        bytesRemain <= `BSV_ASSIGNMENT_DELAY 32'd0;
	dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	dataPtr <= `BSV_ASSIGNMENT_DELAY 32'd0;
	doZLM <= `BSV_ASSIGNMENT_DELAY 1'd0;
	isFirst <= `BSV_ASSIGNMENT_DELAY 1'd1;
	mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY 14'd0;
	mesgRemain <= `BSV_ASSIGNMENT_DELAY 32'd1;
	metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY 3'd0;
	metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY 2'd0;
	metaPtr_modulus <= `BSV_ASSIGNMENT_DELAY 16'd65535;
	metaPtr_value <= `BSV_ASSIGNMENT_DELAY 16'd0;
	splitReadInFlight <= `BSV_ASSIGNMENT_DELAY 1'd0;
	thisLength <= `BSV_ASSIGNMENT_DELAY 32'd0;
	thisOpcode <= `BSV_ASSIGNMENT_DELAY 32'd0;
	thisTLS <= `BSV_ASSIGNMENT_DELAY 32'd0;
	thisTMS <= `BSV_ASSIGNMENT_DELAY 32'd0;
	unrollCnt <= `BSV_ASSIGNMENT_DELAY 16'd0;
	wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY 3'h2;
	wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY 3'd0;
	wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY 3'd0;
	wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
	wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY 34'h0AAAAAAAA;
	wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
	wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
	wsiM_operateD <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
	wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY 1'd0;
	wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY 2'd0;
	wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
	wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY 61'h00000AAAAAAAAA00;
	wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY 1'd1;
	wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY 32'd0;
	wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (bytesRemain$EN)
	  bytesRemain <= `BSV_ASSIGNMENT_DELAY bytesRemain$D_IN;
	if (dataBram_serverAdapterA_cnt$EN)
	  dataBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
	      dataBram_serverAdapterA_cnt$D_IN;
	if (dataBram_serverAdapterA_s1$EN)
	  dataBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
	      dataBram_serverAdapterA_s1$D_IN;
	if (dataBram_serverAdapterB_cnt$EN)
	  dataBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
	      dataBram_serverAdapterB_cnt$D_IN;
	if (dataBram_serverAdapterB_s1$EN)
	  dataBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
	      dataBram_serverAdapterB_s1$D_IN;
	if (dataPtr$EN) dataPtr <= `BSV_ASSIGNMENT_DELAY dataPtr$D_IN;
	if (doZLM$EN) doZLM <= `BSV_ASSIGNMENT_DELAY doZLM$D_IN;
	if (isFirst$EN) isFirst <= `BSV_ASSIGNMENT_DELAY isFirst$D_IN;
	if (mesgLengthSoFar$EN)
	  mesgLengthSoFar <= `BSV_ASSIGNMENT_DELAY mesgLengthSoFar$D_IN;
	if (mesgRemain$EN)
	  mesgRemain <= `BSV_ASSIGNMENT_DELAY mesgRemain$D_IN;
	if (metaBram_serverAdapterA_1_cnt$EN)
	  metaBram_serverAdapterA_1_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_1_cnt$D_IN;
	if (metaBram_serverAdapterA_1_s1$EN)
	  metaBram_serverAdapterA_1_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_1_s1$D_IN;
	if (metaBram_serverAdapterA_2_cnt$EN)
	  metaBram_serverAdapterA_2_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_2_cnt$D_IN;
	if (metaBram_serverAdapterA_2_s1$EN)
	  metaBram_serverAdapterA_2_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_2_s1$D_IN;
	if (metaBram_serverAdapterA_3_cnt$EN)
	  metaBram_serverAdapterA_3_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_3_cnt$D_IN;
	if (metaBram_serverAdapterA_3_s1$EN)
	  metaBram_serverAdapterA_3_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_3_s1$D_IN;
	if (metaBram_serverAdapterA_cnt$EN)
	  metaBram_serverAdapterA_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_cnt$D_IN;
	if (metaBram_serverAdapterA_s1$EN)
	  metaBram_serverAdapterA_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterA_s1$D_IN;
	if (metaBram_serverAdapterB_1_cnt$EN)
	  metaBram_serverAdapterB_1_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_1_cnt$D_IN;
	if (metaBram_serverAdapterB_1_s1$EN)
	  metaBram_serverAdapterB_1_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_1_s1$D_IN;
	if (metaBram_serverAdapterB_2_cnt$EN)
	  metaBram_serverAdapterB_2_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_2_cnt$D_IN;
	if (metaBram_serverAdapterB_2_s1$EN)
	  metaBram_serverAdapterB_2_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_2_s1$D_IN;
	if (metaBram_serverAdapterB_3_cnt$EN)
	  metaBram_serverAdapterB_3_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_3_cnt$D_IN;
	if (metaBram_serverAdapterB_3_s1$EN)
	  metaBram_serverAdapterB_3_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_3_s1$D_IN;
	if (metaBram_serverAdapterB_cnt$EN)
	  metaBram_serverAdapterB_cnt <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_cnt$D_IN;
	if (metaBram_serverAdapterB_s1$EN)
	  metaBram_serverAdapterB_s1 <= `BSV_ASSIGNMENT_DELAY
	      metaBram_serverAdapterB_s1$D_IN;
	if (metaPtr_modulus$EN)
	  metaPtr_modulus <= `BSV_ASSIGNMENT_DELAY metaPtr_modulus$D_IN;
	if (metaPtr_value$EN)
	  metaPtr_value <= `BSV_ASSIGNMENT_DELAY metaPtr_value$D_IN;
	if (splitReadInFlight$EN)
	  splitReadInFlight <= `BSV_ASSIGNMENT_DELAY splitReadInFlight$D_IN;
	if (thisLength$EN)
	  thisLength <= `BSV_ASSIGNMENT_DELAY thisLength$D_IN;
	if (thisOpcode$EN)
	  thisOpcode <= `BSV_ASSIGNMENT_DELAY thisOpcode$D_IN;
	if (thisTLS$EN) thisTLS <= `BSV_ASSIGNMENT_DELAY thisTLS$D_IN;
	if (thisTMS$EN) thisTMS <= `BSV_ASSIGNMENT_DELAY thisTMS$D_IN;
	if (unrollCnt$EN) unrollCnt <= `BSV_ASSIGNMENT_DELAY unrollCnt$D_IN;
	if (wci_wslv_cEdge$EN)
	  wci_wslv_cEdge <= `BSV_ASSIGNMENT_DELAY wci_wslv_cEdge$D_IN;
	if (wci_wslv_cState$EN)
	  wci_wslv_cState <= `BSV_ASSIGNMENT_DELAY wci_wslv_cState$D_IN;
	if (wci_wslv_ctlAckReg$EN)
	  wci_wslv_ctlAckReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_ctlAckReg$D_IN;
	if (wci_wslv_ctlOpActive$EN)
	  wci_wslv_ctlOpActive <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_ctlOpActive$D_IN;
	if (wci_wslv_illegalEdge$EN)
	  wci_wslv_illegalEdge <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_illegalEdge$D_IN;
	if (wci_wslv_nState$EN)
	  wci_wslv_nState <= `BSV_ASSIGNMENT_DELAY wci_wslv_nState$D_IN;
	if (wci_wslv_reqF_countReg$EN)
	  wci_wslv_reqF_countReg <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_reqF_countReg$D_IN;
	if (wci_wslv_respF_c_r$EN)
	  wci_wslv_respF_c_r <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_c_r$D_IN;
	if (wci_wslv_respF_q_0$EN)
	  wci_wslv_respF_q_0 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_0$D_IN;
	if (wci_wslv_respF_q_1$EN)
	  wci_wslv_respF_q_1 <= `BSV_ASSIGNMENT_DELAY wci_wslv_respF_q_1$D_IN;
	if (wci_wslv_sFlagReg$EN)
	  wci_wslv_sFlagReg <= `BSV_ASSIGNMENT_DELAY wci_wslv_sFlagReg$D_IN;
	if (wci_wslv_sThreadBusy_d$EN)
	  wci_wslv_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY
	      wci_wslv_sThreadBusy_d$D_IN;
	if (wsiM_burstKind$EN)
	  wsiM_burstKind <= `BSV_ASSIGNMENT_DELAY wsiM_burstKind$D_IN;
	if (wsiM_errorSticky$EN)
	  wsiM_errorSticky <= `BSV_ASSIGNMENT_DELAY wsiM_errorSticky$D_IN;
	if (wsiM_iMesgCount$EN)
	  wsiM_iMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_iMesgCount$D_IN;
	if (wsiM_operateD$EN)
	  wsiM_operateD <= `BSV_ASSIGNMENT_DELAY wsiM_operateD$D_IN;
	if (wsiM_pMesgCount$EN)
	  wsiM_pMesgCount <= `BSV_ASSIGNMENT_DELAY wsiM_pMesgCount$D_IN;
	if (wsiM_peerIsReady$EN)
	  wsiM_peerIsReady <= `BSV_ASSIGNMENT_DELAY wsiM_peerIsReady$D_IN;
	if (wsiM_reqFifo_c_r$EN)
	  wsiM_reqFifo_c_r <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_c_r$D_IN;
	if (wsiM_reqFifo_q_0$EN)
	  wsiM_reqFifo_q_0 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_0$D_IN;
	if (wsiM_reqFifo_q_1$EN)
	  wsiM_reqFifo_q_1 <= `BSV_ASSIGNMENT_DELAY wsiM_reqFifo_q_1$D_IN;
	if (wsiM_sThreadBusy_d$EN)
	  wsiM_sThreadBusy_d <= `BSV_ASSIGNMENT_DELAY wsiM_sThreadBusy_d$D_IN;
	if (wsiM_tBusyCount$EN)
	  wsiM_tBusyCount <= `BSV_ASSIGNMENT_DELAY wsiM_tBusyCount$D_IN;
	if (wsiM_trafficSticky$EN)
	  wsiM_trafficSticky <= `BSV_ASSIGNMENT_DELAY wsiM_trafficSticky$D_IN;
      end
    if (controlReg$EN) controlReg <= `BSV_ASSIGNMENT_DELAY controlReg$D_IN;
    if (dataCount$EN) dataCount <= `BSV_ASSIGNMENT_DELAY dataCount$D_IN;
    if (mesgCount$EN) mesgCount <= `BSV_ASSIGNMENT_DELAY mesgCount$D_IN;
    if (wsiM_statusR$EN)
      wsiM_statusR <= `BSV_ASSIGNMENT_DELAY wsiM_statusR$D_IN;
  end

  always@(posedge wciS0_Clk or `BSV_RESET_EDGE wciS0_MReset_n)
  if (wciS0_MReset_n == `BSV_RESET_VALUE)
    begin
      wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
      wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY 1'd1;
    end
  else
    begin
      if (wci_wslv_isReset_isInReset$EN)
	wci_wslv_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
	    wci_wslv_isReset_isInReset$D_IN;
      if (wsiM_isReset_isInReset$EN)
	wsiM_isReset_isInReset <= `BSV_ASSIGNMENT_DELAY
	    wsiM_isReset_isInReset$D_IN;
    end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    bytesRemain = 32'hAAAAAAAA;
    controlReg = 32'hAAAAAAAA;
    dataBram_serverAdapterA_cnt = 3'h2;
    dataBram_serverAdapterA_s1 = 2'h2;
    dataBram_serverAdapterB_cnt = 3'h2;
    dataBram_serverAdapterB_s1 = 2'h2;
    dataCount = 32'hAAAAAAAA;
    dataPtr = 32'hAAAAAAAA;
    doZLM = 1'h0;
    isFirst = 1'h0;
    mesgCount = 32'hAAAAAAAA;
    mesgLengthSoFar = 14'h2AAA;
    mesgRemain = 32'hAAAAAAAA;
    metaBram_serverAdapterA_1_cnt = 3'h2;
    metaBram_serverAdapterA_1_s1 = 2'h2;
    metaBram_serverAdapterA_2_cnt = 3'h2;
    metaBram_serverAdapterA_2_s1 = 2'h2;
    metaBram_serverAdapterA_3_cnt = 3'h2;
    metaBram_serverAdapterA_3_s1 = 2'h2;
    metaBram_serverAdapterA_cnt = 3'h2;
    metaBram_serverAdapterA_s1 = 2'h2;
    metaBram_serverAdapterB_1_cnt = 3'h2;
    metaBram_serverAdapterB_1_s1 = 2'h2;
    metaBram_serverAdapterB_2_cnt = 3'h2;
    metaBram_serverAdapterB_2_s1 = 2'h2;
    metaBram_serverAdapterB_3_cnt = 3'h2;
    metaBram_serverAdapterB_3_s1 = 2'h2;
    metaBram_serverAdapterB_cnt = 3'h2;
    metaBram_serverAdapterB_s1 = 2'h2;
    metaPtr_modulus = 16'hAAAA;
    metaPtr_value = 16'hAAAA;
    splitReadInFlight = 1'h0;
    thisLength = 32'hAAAAAAAA;
    thisOpcode = 32'hAAAAAAAA;
    thisTLS = 32'hAAAAAAAA;
    thisTMS = 32'hAAAAAAAA;
    unrollCnt = 16'hAAAA;
    wci_wslv_cEdge = 3'h2;
    wci_wslv_cState = 3'h2;
    wci_wslv_ctlAckReg = 1'h0;
    wci_wslv_ctlOpActive = 1'h0;
    wci_wslv_illegalEdge = 1'h0;
    wci_wslv_isReset_isInReset = 1'h0;
    wci_wslv_nState = 3'h2;
    wci_wslv_reqF_countReg = 2'h2;
    wci_wslv_respF_c_r = 2'h2;
    wci_wslv_respF_q_0 = 34'h2AAAAAAAA;
    wci_wslv_respF_q_1 = 34'h2AAAAAAAA;
    wci_wslv_sFlagReg = 1'h0;
    wci_wslv_sThreadBusy_d = 1'h0;
    wsiM_burstKind = 2'h2;
    wsiM_errorSticky = 1'h0;
    wsiM_iMesgCount = 32'hAAAAAAAA;
    wsiM_isReset_isInReset = 1'h0;
    wsiM_operateD = 1'h0;
    wsiM_pMesgCount = 32'hAAAAAAAA;
    wsiM_peerIsReady = 1'h0;
    wsiM_reqFifo_c_r = 2'h2;
    wsiM_reqFifo_q_0 = 61'h0AAAAAAAAAAAAAAA;
    wsiM_reqFifo_q_1 = 61'h0AAAAAAAAAAAAAAA;
    wsiM_sThreadBusy_d = 1'h0;
    wsiM_statusR = 8'hAA;
    wsiM_tBusyCount = 32'hAAAAAAAA;
    wsiM_trafficSticky = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge wciS0_Clk)
  begin
    #0;
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
	begin
	  v__h3725 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_start)
	$display("[%0d]: %m: WCI ControlOp: Starting-transition edge:%x from:%x",
		 v__h3725,
		 wci_wslv_reqF$D_OUT[36:34],
		 wci_wslv_cState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0)
	begin
	  v__h32403 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && wci_wslv_reqF$D_OUT[63:52] == 12'h0)
	$display("[%0d]: %m: WCI CONFIG READ Addr:%0x BE:%0x Data:%0x",
		 v__h32403,
		 wci_wslv_reqF$D_OUT[63:32],
		 wci_wslv_reqF$D_OUT[67:64],
		 v__h32384);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (dataBram_serverAdapterA_s1[1] &&
	  !dataBram_serverAdapterA_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1)
	begin
	  v__h29716 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (wsiM_reqFifo_enqueueing$whas && unrollCnt == 16'd1)
	$display("[%0d]: %m: wsi_source: End of WSI Producer Egress: mesgCount:%0x thisOpcode:%0x thisLength:%0x",
		 v__h29716,
		 mesgCount,
		 thisOpcode,
		 thisLength);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (dataBram_serverAdapterB_s1[1] &&
	  !dataBram_serverAdapterB_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterA_s1[1] &&
	  !metaBram_serverAdapterA_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterB_s1[1] &&
	  !metaBram_serverAdapterB_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterA_1_s1[1] &&
	  !metaBram_serverAdapterA_1_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterB_1_s1[1] &&
	  !metaBram_serverAdapterB_1_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterA_2_s1[1] &&
	  !metaBram_serverAdapterA_2_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterB_2_s1[1] &&
	  !metaBram_serverAdapterB_2_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterA_3_s1[1] &&
	  !metaBram_serverAdapterA_3_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0)
	begin
	  v__h31317 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h0)
	$display("[%0d]: %m: WCI CONFIG WRITE Addr:%0x BE:%0x Data:%0x",
		 v__h31317,
		 wci_wslv_reqF$D_OUT[63:32],
		 wci_wslv_reqF$D_OUT[67:64],
		 wci_wslv_reqF$D_OUT[31:0]);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h800)
	begin
	  v__h31561 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h800)
	$display("[%0d]: %m: Write to Pattern Gen DATA region addr:%0x data:%0x",
		 v__h31561,
		 wci_wslv_reqF$D_OUT[63:32],
		 wci_wslv_reqF$D_OUT[31:0]);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400)
	begin
	  v__h32120 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && wci_wslv_reqF$D_OUT[63:52] == 12'h400)
	$display("[%0d]: %m: Write to Pattern Gen META region addr:%0x data:%0x",
		 v__h32120,
		 wci_wslv_reqF$D_OUT[63:32],
		 wci_wslv_reqF$D_OUT[31:0]);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
	begin
	  v__h4044 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && wci_wslv_illegalEdge)
	$display("[%0d]: %m: WCI ControlOp: ILLEGAL-EDGE Completed-transition edge:%x from:%x",
		 v__h4044,
		 wci_wslv_cEdge,
		 wci_wslv_cState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
	begin
	  v__h3900 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_wslv_ctl_op_complete && !wci_wslv_illegalEdge)
	$display("[%0d]: %m: WCI ControlOp: Completed-transition edge:%x from:%x to:%x",
		 v__h3900,
		 wci_wslv_cEdge,
		 wci_wslv_cState,
		 wci_wslv_nState);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (metaBram_serverAdapterB_3_s1[1] &&
	  !metaBram_serverAdapterB_3_outDataCore$FULL_N)
	$display("ERROR: %m: mkBRAMSeverAdapter overrun");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	begin
	  v__h30815 = $time;
	  #0;
	end
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("[%0d]: %m: WCI SPLIT READ Data:%0x", v__h30815, v__h29897);
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_advance_split_response] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && MUX_controlReg$write_1__SEL_2)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and\n  [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfwr && WILL_FIRE_RL_wci_cfrd)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 28: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfwr] and [RL_wci_cfrd] )\n  fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_advance_split_response] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_cfrd && MUX_controlReg$write_1__SEL_2)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 38: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_cfrd] and\n  [RL_wci_ctrl_EiI] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (MUX_controlReg$write_1__SEL_2 &&
	  MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n  [RL_advance_split_response] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (MUX_controlReg$write_1__SEL_2 && WILL_FIRE_RL_wci_ctrl_IsO)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 48: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_EiI] and\n  [RL_wci_ctrl_IsO] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_IsO &&
	  MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 62: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n  [RL_advance_split_response] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_IsO && WILL_FIRE_RL_wci_ctrl_OrE)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 62: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_IsO] and\n  [RL_wci_ctrl_OrE] ) fired in the same clock cycle.\n");
    if (wciS0_MReset_n != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_wci_ctrl_OrE &&
	  MUX_wci_wslv_respF_x_wire$wset_1__SEL_3)
	$display("Error: \"bsv/wrk/WSIPatternWorker.bsv\", line 227, column 76: (R0001)\n  Mutually exclusive rules (from the ME sets [RL_wci_ctrl_OrE] and\n  [RL_advance_split_response] ) fired in the same clock cycle.\n");
  end
  // synopsys translate_on
endmodule  // mkWSIPatternWorker4B